Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 1 | // Geode GX2/LX VGA functions |
| 2 | // |
| 3 | // Copyright (C) 2009 Chris Kindt |
| 4 | // |
| 5 | // Writen for Google Summer of Code 2009 for the coreboot project |
| 6 | // |
| 7 | // This file may be distributed under the terms of the GNU LGPLv3 license. |
| 8 | |
| 9 | #ifndef GEODEVGA_H |
| 10 | #define GEODEVGA_H |
| 11 | |
| 12 | #define VRC_INDEX 0xAC1C // Index register |
| 13 | #define VRC_DATA 0xAC1E // Data register |
| 14 | #define VR_UNLOCK 0xFC53 // Virtual register unlock code |
| 15 | |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 16 | // Graphics-specific registers: |
| 17 | #define OEM_BAR0 0x50 |
| 18 | #define OEM_BAR1 0x54 |
| 19 | #define OEM_BAR2 0x58 |
| 20 | #define OEM_BAR3 0x5C |
| 21 | |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 22 | #define DC_LOCK_LOCK 0x00000000 |
| 23 | #define DC_LOCK_UNLOCK 0x00004758 |
| 24 | |
| 25 | /* LX MSRs */ |
| 26 | #define MSR_GLIU0 (1 << 28) |
Nils | 24ddd86 | 2012-01-14 12:15:14 -0500 | [diff] [blame] | 27 | #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* LX */ |
| 28 | #define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) /* GX2 */ |
Christian Gmeiner | 9de339d | 2012-09-01 17:12:56 +0200 | [diff] [blame^] | 29 | #define GLIU0_P2D_RO (MSR_GLIU0 + 0x29) |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 30 | #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) |
| 31 | #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) |
| 32 | #define DC_SPARE 0x80000011 |
Nils | 24ddd86 | 2012-01-14 12:15:14 -0500 | [diff] [blame] | 33 | #define VP_MSR_CONFIG_GX2 0xc0002001 /* GX2 */ |
| 34 | #define VP_MSR_CONFIG_LX 0x48002001 /* LX */ |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 35 | |
| 36 | /* DC REG OFFSET */ |
| 37 | #define DC_UNLOCK 0x0 |
| 38 | #define DC_GENERAL_CFG 0x4 |
| 39 | #define DC_DISPLAY_CFG 0x8 |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 40 | #define DC_FB_ST_OFFSET 0x10 |
| 41 | #define DC_CB_ST_OFFSET 0x14 |
| 42 | #define DC_CURS_ST_OFFSET 0x18 |
| 43 | #define DC_GLIU0_MEM_OFFSET 0x84 |
| 44 | |
| 45 | /* VP REG OFFSET */ |
| 46 | #define VP_VCFG 0x0 |
| 47 | #define VP_DCFG 0x8 |
| 48 | #define VP_MISC 0x50 |
| 49 | |
| 50 | |
| 51 | /* DC bits */ |
| 52 | #define DC_VGAE (1 << 7) |
| 53 | #define DC_GDEN (1 << 3) |
| 54 | #define DC_TRUP (1 << 6) |
| 55 | |
| 56 | /* VP bits */ |
| 57 | #define VP_CRT_EN (1 << 0) |
| 58 | #define VP_HSYNC_EN (1 << 1) |
| 59 | #define VP_VSYNC_EN (1 << 2) |
| 60 | #define VP_DAC_BL_EN (1 << 3) |
| 61 | #define VP_CRT_SKEW (1 << 16) |
| 62 | #define VP_BYP_BOTH (1 << 0) |
| 63 | |
Nils | e8b184f | 2012-01-14 12:13:34 -0500 | [diff] [blame] | 64 | /* Mask */ |
Nils | 31eabf9 | 2012-01-14 12:11:41 -0500 | [diff] [blame] | 65 | #define DC_CFG_MSK 0xf000a6 |
| 66 | |
| 67 | int geodevga_init(); |
| 68 | |
| 69 | #endif |