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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
Kevin O'Connor9a79b912014-01-15 11:08:22 -05008#include "byteorder.h" // le64_to_cpu
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04009#include "config.h" // CONFIG_*
10#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
Paolo Bonzini40d03122014-05-15 13:22:26 +020011#include "dev-piix.h" // PIIX_*
Kevin O'Connorc167e542015-09-29 09:40:46 -040012#include "e820map.h" // e820_add
Kevin O'Connor4ade5232013-09-18 21:41:48 -040013#include "hw/ata.h" // PORT_ATA1_CMD_BASE
Kevin O'Connor5d369d82013-09-02 20:48:46 -040014#include "hw/pci.h" // pci_config_readl
Kevin O'Connor4d8510c2016-02-03 01:28:20 -050015#include "hw/pcidevice.h" // pci_probe_devices
Kevin O'Connor5d369d82013-09-02 20:48:46 -040016#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
17#include "hw/pci_regs.h" // PCI_COMMAND
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +030018#include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE
Kevin O'Connora88c1972013-06-08 21:51:46 -040019#include "list.h" // struct hlist_node
Kevin O'Connor9dea5902013-09-14 20:23:54 -040020#include "malloc.h" // free
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040021#include "output.h" // dprintf
22#include "paravirt.h" // RamSize
Kevin O'Connor9a79b912014-01-15 11:08:22 -050023#include "romfile.h" // romfile_loadint
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040024#include "string.h" // memset
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040025#include "util.h" // pci_setup
Kevin O'Connor4ade5232013-09-18 21:41:48 -040026#include "x86.h" // outb
Isaku Yamahata72a590e2012-11-28 10:17:33 +010027
Gerd Hoffmann67a3c7c2013-11-26 13:12:04 +010028#define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
29#define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
30#define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090031
Kevin O'Connor62ff9d52016-02-03 00:47:27 -050032#define PCI_ROM_SLOT 6
33#define PCI_NUM_REGIONS 7
34#define PCI_BRIDGE_NUM_REGIONS 2
35
36enum pci_region_type {
37 PCI_REGION_TYPE_IO,
38 PCI_REGION_TYPE_MEM,
39 PCI_REGION_TYPE_PREFMEM,
40 PCI_REGION_TYPE_COUNT,
41};
42
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020043static const char *region_type_name[] = {
44 [ PCI_REGION_TYPE_IO ] = "io",
45 [ PCI_REGION_TYPE_MEM ] = "mem",
46 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
47};
48
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020049u64 pcimem_start = BUILD_PCIMEM_START;
50u64 pcimem_end = BUILD_PCIMEM_END;
51u64 pcimem64_start = BUILD_PCIMEM64_START;
52u64 pcimem64_end = BUILD_PCIMEM64_END;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +020053u64 pci_io_low_end = 0xa000;
Gerd Hoffmann96a8d132022-09-09 10:17:15 +020054u32 pci_use_64bit = 0;
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020055
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120056struct pci_region_entry {
57 struct pci_device *dev;
58 int bar;
Alexey Korolev030288f2012-04-19 17:44:55 +120059 u64 size;
60 u64 align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120061 int is64;
62 enum pci_region_type type;
Kevin O'Connora88c1972013-06-08 21:51:46 -040063 struct hlist_node node;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120064};
65
Alexey Korolev35a770f2012-04-19 17:47:19 +120066struct pci_region {
Alexey Korolev35a770f2012-04-19 17:47:19 +120067 /* pci region assignments */
68 u64 base;
Kevin O'Connora88c1972013-06-08 21:51:46 -040069 struct hlist_head list;
Alexey Korolev35a770f2012-04-19 17:47:19 +120070};
71
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040072struct pci_bus {
Alexey Korolev35a770f2012-04-19 17:47:19 +120073 struct pci_region r[PCI_REGION_TYPE_COUNT];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -040074 struct pci_device *bus_dev;
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040075};
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020076
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040077static u32 pci_bar(struct pci_device *pci, int region_num)
Isaku Yamahataa65821d2010-06-22 17:57:50 +090078{
79 if (region_num != PCI_ROM_SLOT) {
80 return PCI_BASE_ADDRESS_0 + region_num * 4;
81 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090082
83#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040084 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
Isaku Yamahata5d0de152010-06-22 17:57:51 +090085 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090086}
87
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040088static void
Alexey Korolev030288f2012-04-19 17:44:55 +120089pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
Kevin O'Connor0525d292008-07-04 06:18:30 -040090{
Alexey Korolev030288f2012-04-19 17:44:55 +120091 u32 ofs = pci_bar(pci, bar);
92 pci_config_writel(pci->bdf, ofs, addr);
93 if (is64)
94 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090095}
96
Kevin O'Connor5bab7e62011-10-01 11:33:31 -040097
98/****************************************************************
99 * Misc. device init
100 ****************************************************************/
101
102/* host irqs corresponding to PCI irqs A-D */
103const u8 pci_irqs[4] = {
104 10, 10, 11, 11
105};
106
Alex Williamsondbb7a662013-02-21 09:12:23 -0700107static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
108{
109 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
110
111 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
112}
113
114static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
115 dummy_pci_slot_get_irq;
Alex Williamsonb9490402013-02-15 14:11:41 -0700116
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400117// Return the global irq number corresponding to a host bus device irq pin.
Alex Williamsonb9490402013-02-15 14:11:41 -0700118static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400119{
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200120 int slot_addend = 0;
121
122 while (pci->parent != NULL) {
123 slot_addend += pci_bdf_to_dev(pci->bdf);
124 pci = pci->parent;
125 }
126 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400127 return pci_irqs[(pin - 1 + slot_addend) & 3];
Kevin O'Connor0525d292008-07-04 06:18:30 -0400128}
129
Alex Williamsonb9490402013-02-15 14:11:41 -0700130static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
131{
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500132 int pin_addend = 0;
Alex Williamsonb9490402013-02-15 14:11:41 -0700133 while (pci->parent != NULL) {
134 pin_addend += pci_bdf_to_dev(pci->bdf);
135 pci = pci->parent;
136 }
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500137 u8 slot = pci_bdf_to_dev(pci->bdf);
138 if (slot <= 24)
139 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
140 with a different starting index - see q35-acpi-dsdt.dsl */
141 return pci_irqs[(pin - 1 + pin_addend + slot) & 3];
Alex Williamsonb9490402013-02-15 14:11:41 -0700142 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500143 return pci_irqs[(pin - 1 + pin_addend) & 3];
Alex Williamsonb9490402013-02-15 14:11:41 -0700144}
145
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400146/* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500147static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400148{
149 int i, irq;
150 u8 elcr[2];
151
152 elcr[0] = 0x00;
153 elcr[1] = 0x00;
154 for (i = 0; i < 4; i++) {
155 irq = pci_irqs[i];
156 /* set to trigger level */
157 elcr[irq >> 3] |= (1 << (irq & 7));
158 /* activate irq remapping in PIIX */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400159 pci_config_writeb(pci->bdf, 0x60 + i, irq);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400160 }
Paolo Bonzini40d03122014-05-15 13:22:26 +0200161 outb(elcr[0], PIIX_PORT_ELCR1);
162 outb(elcr[1], PIIX_PORT_ELCR2);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400163 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
164}
165
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200166static void mch_isa_lpc_setup(u16 bdf)
167{
168 /* pm io base */
169 pci_config_writel(bdf, ICH9_LPC_PMBASE,
170 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
171
172 /* acpi enable, SCI: IRQ9 000b = irq9*/
173 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
174
175 /* set root complex register block BAR */
176 pci_config_writel(bdf, ICH9_LPC_RCBA,
177 ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
178}
179
180static int ICH9LpcBDF = -1;
181
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100182/* ICH9 LPC PCI to ISA bridge */
183/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500184static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100185{
186 u16 bdf = dev->bdf;
187 int i, irq;
188 u8 elcr[2];
189
190 elcr[0] = 0x00;
191 elcr[1] = 0x00;
192
193 for (i = 0; i < 4; i++) {
194 irq = pci_irqs[i];
195 /* set to trigger level */
196 elcr[irq >> 3] |= (1 << (irq & 7));
197
198 /* activate irq remapping in LPC */
199
200 /* PIRQ[A-D] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700201 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100202 /* PIRQ[E-H] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700203 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100204 }
205 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
206 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
207 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
208
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200209 ICH9LpcBDF = bdf;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100210
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200211 mch_isa_lpc_setup(bdf);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100212
Kevin O'Connorc167e542015-09-29 09:40:46 -0400213 e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
Paulo Alcantara7f50afc2015-07-09 21:04:01 -0300214
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200215 acpi_pm1a_cnt = acpi_pm_base + 0x04;
216 pmtimer_setup(acpi_pm_base + 0x08);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100217}
218
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500219static void storage_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400220{
221 /* IDE: we map it as in ISA mode */
Alexey Korolev030288f2012-04-19 17:44:55 +1200222 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
223 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
224 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
225 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400226}
227
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400228/* PIIX3/PIIX4 IDE */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500229static void piix_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400230{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400231 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400232 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
233 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400234}
235
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500236static void pic_ibm_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400237{
238 /* PIC, IBM, MPIC & MPIC2 */
Alexey Korolev030288f2012-04-19 17:44:55 +1200239 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400240}
241
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500242static void apple_macio_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400243{
244 /* macio bridge */
Alexey Korolev030288f2012-04-19 17:44:55 +1200245 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400246}
247
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200248static void piix4_pm_config_setup(u16 bdf)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400249{
250 // acpi sci is hardwired to 9
251 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
252
Paolo Bonzini40d03122014-05-15 13:22:26 +0200253 pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
254 pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
255 pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
256 pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200257}
258
259static int PiixPmBDF = -1;
260
261/* PIIX4 Power Management device (for ACPI) */
262static void piix4_pm_setup(struct pci_device *pci, void *arg)
263{
264 PiixPmBDF = pci->bdf;
265 piix4_pm_config_setup(pci->bdf);
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200266
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200267 acpi_pm1a_cnt = acpi_pm_base + 0x04;
268 pmtimer_setup(acpi_pm_base + 0x08);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400269}
270
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200271static void ich9_smbus_enable(u16 bdf)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100272{
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100273 /* map smbus into io space */
274 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200275 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100276
277 /* enable SMBus */
278 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
279}
280
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200281static int ICH9SmbusBDF = -1;
282
283/* ICH9 SMBUS */
284/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
285static void ich9_smbus_setup(struct pci_device *dev, void *arg)
286{
287 ICH9SmbusBDF = dev->bdf;
288
289 ich9_smbus_enable(dev->bdf);
290}
291
Alex Williamson04259c52016-05-17 14:44:32 -0600292static void intel_igd_setup(struct pci_device *dev, void *arg)
293{
294 struct romfile_s *opregion = romfile_find("etc/igd-opregion");
295 u64 bdsm_size = le64_to_cpu(romfile_loadint("etc/igd-bdsm-size", 0));
Alex Williamson04259c52016-05-17 14:44:32 -0600296
297 /* Apply OpRegion to any Intel VGA device, more than one is undefined */
298 if (opregion && opregion->size) {
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400299 void *addr = memalign_high(PAGE_SIZE, opregion->size);
Alex Williamson04259c52016-05-17 14:44:32 -0600300 if (!addr) {
301 warn_noalloc();
302 return;
303 }
304
305 if (opregion->copy(opregion, addr, opregion->size) < 0) {
306 free(addr);
307 return;
308 }
309
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400310 pci_config_writel(dev->bdf, 0xFC, cpu_to_le32((u32)addr));
Alex Williamson04259c52016-05-17 14:44:32 -0600311
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400312 dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev %pP\n"
313 , (u32)addr, opregion->size >> 10, dev);
Alex Williamson04259c52016-05-17 14:44:32 -0600314 }
315
316 /* Apply BDSM only to Intel VGA at 00:02.0 */
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400317 if (bdsm_size && (dev->bdf == pci_to_bdf(0, 2, 0))) {
318 void *addr = memalign_tmphigh(1024 * 1024, bdsm_size);
Alex Williamson04259c52016-05-17 14:44:32 -0600319 if (!addr) {
320 warn_noalloc();
321 return;
322 }
323
324 e820_add((u32)addr, bdsm_size, E820_RESERVED);
325
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400326 pci_config_writel(dev->bdf, 0x5C, cpu_to_le32((u32)addr));
Alex Williamson04259c52016-05-17 14:44:32 -0600327
Kevin O'Connora9cf7822019-05-23 11:27:09 -0400328 dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %lldMB, dev %pP\n"
329 , (u32)addr, bdsm_size >> 20, dev);
Alex Williamson04259c52016-05-17 14:44:32 -0600330 }
331}
332
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400333static const struct pci_device_id pci_device_tbl[] = {
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500334 /* PIIX3/PIIX4 PCI to ISA bridge */
335 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500336 piix_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500337 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500338 piix_isa_bridge_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100339 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500340 mch_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500341
342 /* STORAGE IDE */
343 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500344 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500345 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500346 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500347 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500348 storage_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500349
Cao jine518c0f2016-01-30 15:50:38 +0800350 /* PIC, IBM, MPIC & MPIC2 */
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500351 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500352 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500353 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500354 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500355
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400356 /* PIIX4 Power Management device (for ACPI) */
357 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500358 piix4_pm_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100359 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500360 ich9_smbus_setup),
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400361
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500362 /* 0xff00 */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500363 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
364 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500365
Alex Williamson04259c52016-05-17 14:44:32 -0600366 /* Intel IGD OpRegion setup */
367 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
368 intel_igd_setup),
369
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400370 PCI_DEVICE_END,
371};
372
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200373static int MCHMmcfgBDF = -1;
374static void mch_mmconfig_setup(u16 bdf);
375
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200376void pci_resume(void)
377{
378 if (!CONFIG_QEMU) {
379 return;
380 }
381
382 if (PiixPmBDF >= 0) {
383 piix4_pm_config_setup(PiixPmBDF);
384 }
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200385
386 if (ICH9LpcBDF >= 0) {
387 mch_isa_lpc_setup(ICH9LpcBDF);
388 }
389
390 if (ICH9SmbusBDF >= 0) {
391 ich9_smbus_enable(ICH9SmbusBDF);
392 }
393
394 if(MCHMmcfgBDF >= 0) {
395 mch_mmconfig_setup(MCHMmcfgBDF);
396 }
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200397}
398
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400399static void pci_bios_init_device(struct pci_device *pci)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400400{
Kevin O'Connor7b673002016-02-03 03:03:15 -0500401 dprintf(1, "PCI: init bdf=%pP id=%04x:%04x\n"
402 , pci, pci->vendor, pci->device);
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400403
Kevin O'Connor0525d292008-07-04 06:18:30 -0400404 /* map the interrupt */
Kevin O'Connor7b673002016-02-03 03:03:15 -0500405 u16 bdf = pci->bdf;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400406 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
407 if (pin != 0)
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200408 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
Kevin O'Connor0525d292008-07-04 06:18:30 -0400409
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400410 pci_init_device(pci_device_tbl, pci, NULL);
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500411
412 /* enable memory mappings */
Isaku Yamahatad146ab82012-11-28 10:17:32 +0100413 pci_config_maskw(bdf, PCI_COMMAND, 0,
414 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
Chen Fan32ec3ee2015-01-28 16:05:13 +0800415 /* enable SERR# for forwarding */
416 if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
417 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
418 PCI_BRIDGE_CTL_SERR);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400419}
420
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400421static void pci_bios_init_devices(void)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900422{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400423 struct pci_device *pci;
424 foreachpci(pci) {
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400425 pci_bios_init_device(pci);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900426 }
427}
428
Alex Williamson7adfd712013-03-20 10:58:47 -0600429static void pci_enable_default_vga(void)
430{
431 struct pci_device *pci;
432
433 foreachpci(pci) {
434 if (is_pci_vga(pci)) {
Kevin O'Connor7b673002016-02-03 03:03:15 -0500435 dprintf(1, "PCI: Using %pP for primary VGA\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600436 return;
437 }
438 }
439
440 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
441 if (!pci) {
442 dprintf(1, "PCI: No VGA devices found\n");
443 return;
444 }
445
Kevin O'Connor7b673002016-02-03 03:03:15 -0500446 dprintf(1, "PCI: Enabling %pP for primary VGA\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600447
448 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
449 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
450
451 while (pci->parent) {
452 pci = pci->parent;
453
Kevin O'Connor7b673002016-02-03 03:03:15 -0500454 dprintf(1, "PCI: Setting VGA enable on bridge %pP\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600455
456 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
457 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
458 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
459 }
460}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400461
462/****************************************************************
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500463 * Platform device initialization
464 ****************************************************************/
465
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500466static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500467{
468 if (RamSize <= 0x80000000)
469 pcimem_start = 0x80000000;
470 else if (RamSize <= 0xc0000000)
471 pcimem_start = 0xc0000000;
Alex Williamsonb9490402013-02-15 14:11:41 -0700472
473 pci_slot_get_irq = piix_pci_slot_get_irq;
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500474}
475
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200476static void mch_mmconfig_setup(u16 bdf)
477{
478 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
479 u32 upper = addr >> 32;
480 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
481 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
482 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
483 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
Gerd Hoffmann6a3b59a2020-03-23 15:59:11 +0100484 pci_enable_mmconfig(Q35_HOST_BRIDGE_PCIEXBAR_ADDR, "q35");
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200485}
486
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500487static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100488{
489 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
490 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
491
492 /* setup mmconfig */
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200493 MCHMmcfgBDF = dev->bdf;
494 mch_mmconfig_setup(dev->bdf);
Kevin O'Connorc167e542015-09-29 09:40:46 -0400495 e820_add(addr, size, E820_RESERVED);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100496
497 /* setup pci i/o window (above mmconfig) */
498 pcimem_start = addr + size;
Alex Williamsonb9490402013-02-15 14:11:41 -0700499
500 pci_slot_get_irq = mch_pci_slot_get_irq;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200501
502 /* setup io address space */
503 if (acpi_pm_base < 0x1000)
504 pci_io_low_end = 0x10000;
505 else
506 pci_io_low_end = acpi_pm_base;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100507}
508
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500509static const struct pci_device_id pci_platform_tbl[] = {
510 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500511 i440fx_mem_addr_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100512 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500513 mch_mem_addr_setup),
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500514 PCI_DEVICE_END
515};
516
517static void pci_bios_init_platform(void)
518{
519 struct pci_device *pci;
520 foreachpci(pci) {
521 pci_init_device(pci_platform_tbl, pci, NULL);
522 }
523}
524
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300525static u8 pci_find_resource_reserve_capability(u16 bdf)
526{
Jing Liubcd82422018-08-24 16:53:01 +0800527 u16 device_id;
528
529 if (pci_config_readw(bdf, PCI_VENDOR_ID) != PCI_VENDOR_ID_REDHAT) {
530 dprintf(3, "PCI: This is non-QEMU bridge.\n");
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300531 return 0;
532 }
Jing Liubcd82422018-08-24 16:53:01 +0800533
534 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
535
536 if (device_id != PCI_DEVICE_ID_REDHAT_ROOT_PORT &&
537 device_id != PCI_DEVICE_ID_REDHAT_BRIDGE) {
538 dprintf(1, "PCI: QEMU resource reserve cap device ID doesn't match.\n");
539 return 0;
540 }
541 u8 cap = 0;
542
543 do {
544 cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap);
545 } while (cap &&
546 pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) !=
547 REDHAT_CAP_RESOURCE_RESERVE);
548 if (cap) {
549 u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS);
550 if (cap_len < RES_RESERVE_CAP_SIZE) {
551 dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n",
552 cap_len);
553 return 0;
554 }
555 } else {
556 dprintf(1, "PCI: QEMU resource reserve cap not found\n");
557 }
558 return cap;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300559}
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500560
561/****************************************************************
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400562 * Bus initialization
563 ****************************************************************/
564
Isaku Yamahataf4416662010-06-22 17:57:52 +0900565static void
566pci_bios_init_bus_rec(int bus, u8 *pci_bus)
567{
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400568 int bdf;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900569 u16 class;
570
571 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
572
573 /* prevent accidental access to unintended devices */
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400574 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900575 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
576 if (class == PCI_CLASS_BRIDGE_PCI) {
577 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
578 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
579 }
580 }
581
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400582 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900583 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
584 if (class != PCI_CLASS_BRIDGE_PCI) {
585 continue;
586 }
587 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
588
589 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
590 if (pribus != bus) {
591 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
592 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
593 } else {
594 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
595 }
596
597 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
598 (*pci_bus)++;
599 if (*pci_bus != secbus) {
600 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
601 secbus, *pci_bus);
602 secbus = *pci_bus;
603 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
604 } else {
605 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
606 }
607
608 /* set to max for access to all subordinate buses.
609 later set it to accurate value */
610 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
611 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
612
613 pci_bios_init_bus_rec(secbus, pci_bus);
614
615 if (subbus != *pci_bus) {
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300616 u8 res_bus = *pci_bus;
617 u8 cap = pci_find_resource_reserve_capability(bdf);
618
619 if (cap) {
620 u32 tmp_res_bus = pci_config_readl(bdf,
621 cap + RES_RESERVE_BUS_RES);
622 if (tmp_res_bus != (u32)-1) {
623 res_bus = tmp_res_bus & 0xFF;
624 if ((u8)(res_bus + secbus) < secbus ||
625 (u8)(res_bus + secbus) < res_bus) {
626 dprintf(1, "PCI: bus_reserve value %d is invalid\n",
627 res_bus);
628 res_bus = 0;
629 }
Marcel Apfelbaum14d91c32018-01-11 22:15:12 +0200630 if (secbus + res_bus > *pci_bus) {
631 dprintf(1, "PCI: QEMU resource reserve cap: bus = %u\n",
632 res_bus);
633 res_bus = secbus + res_bus;
634 }
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300635 }
636 }
Isaku Yamahataf4416662010-06-22 17:57:52 +0900637 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300638 subbus, res_bus);
639 subbus = res_bus;
640 *pci_bus = res_bus;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900641 } else {
642 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
643 }
644 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
645 }
646}
647
648static void
649pci_bios_init_bus(void)
650{
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200651 u8 extraroots = romfile_loadint("etc/extra-pci-roots", 0);
Isaku Yamahataf4416662010-06-22 17:57:52 +0900652 u8 pci_bus = 0;
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200653
Isaku Yamahataf4416662010-06-22 17:57:52 +0900654 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200655
656 if (extraroots) {
657 while (pci_bus < 0xff) {
658 pci_bus++;
659 pci_bios_init_bus_rec(pci_bus, &pci_bus);
660 }
661 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200662}
663
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400664
665/****************************************************************
666 * Bus sizing
667 ****************************************************************/
668
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400669static void
Alexey Korolev030288f2012-04-19 17:44:55 +1200670pci_bios_get_bar(struct pci_device *pci, int bar,
671 int *ptype, u64 *psize, int *pis64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200672{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400673 u32 ofs = pci_bar(pci, bar);
674 u16 bdf = pci->bdf;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200675 u32 old = pci_config_readl(bdf, ofs);
Alexey Korolev030288f2012-04-19 17:44:55 +1200676 int is64 = 0, type = PCI_REGION_TYPE_MEM;
677 u64 mask;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200678
679 if (bar == PCI_ROM_SLOT) {
680 mask = PCI_ROM_ADDRESS_MASK;
681 pci_config_writel(bdf, ofs, mask);
682 } else {
Alexey Korolev030288f2012-04-19 17:44:55 +1200683 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200684 mask = PCI_BASE_ADDRESS_IO_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200685 type = PCI_REGION_TYPE_IO;
686 } else {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200687 mask = PCI_BASE_ADDRESS_MEM_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200688 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
689 type = PCI_REGION_TYPE_PREFMEM;
690 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
691 == PCI_BASE_ADDRESS_MEM_TYPE_64);
692 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200693 pci_config_writel(bdf, ofs, ~0);
694 }
Alexey Korolev030288f2012-04-19 17:44:55 +1200695 u64 val = pci_config_readl(bdf, ofs);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200696 pci_config_writel(bdf, ofs, old);
Alexey Korolev030288f2012-04-19 17:44:55 +1200697 if (is64) {
698 u32 hold = pci_config_readl(bdf, ofs + 4);
699 pci_config_writel(bdf, ofs + 4, ~0);
700 u32 high = pci_config_readl(bdf, ofs + 4);
701 pci_config_writel(bdf, ofs + 4, hold);
702 val |= ((u64)high << 32);
703 mask |= ((u64)0xffffffff << 32);
704 *psize = (~(val & mask)) + 1;
705 } else {
706 *psize = ((~(val & mask)) + 1) & 0xffffffff;
707 }
708 *ptype = type;
709 *pis64 = is64;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200710}
711
Alexey Korolevac0cd582012-04-19 17:48:54 +1200712static int pci_bios_bridge_region_is64(struct pci_region *r,
713 struct pci_device *pci, int type)
714{
715 if (type != PCI_REGION_TYPE_PREFMEM)
716 return 0;
717 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
718 if (!pmem) {
719 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
720 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
721 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
722 }
723 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
724 return 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400725 struct pci_region_entry *entry;
726 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolevac0cd582012-04-19 17:48:54 +1200727 if (!entry->is64)
728 return 0;
Alexey Korolevac0cd582012-04-19 17:48:54 +1200729 }
730 return 1;
731}
732
Alexey Korolev37c111f2012-04-26 16:51:05 +1200733static u64 pci_region_align(struct pci_region *r)
734{
Kevin O'Connora88c1972013-06-08 21:51:46 -0400735 struct pci_region_entry *entry;
736 hlist_for_each_entry(entry, &r->list, node) {
737 // The first entry in the sorted list has the largest alignment
738 return entry->align;
739 }
740 return 1;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200741}
742
743static u64 pci_region_sum(struct pci_region *r)
744{
Alexey Korolev37c111f2012-04-26 16:51:05 +1200745 u64 sum = 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400746 struct pci_region_entry *entry;
747 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolev37c111f2012-04-26 16:51:05 +1200748 sum += entry->size;
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400749 }
750 return sum;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200751}
752
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200753static void pci_region_migrate_64bit_entries(struct pci_region *from,
754 struct pci_region *to)
755{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400756 struct hlist_node *n, **last = &to->list.first;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400757 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400758 hlist_for_each_entry_safe(entry, n, &from->list, node) {
Kevin O'Connora88c1972013-06-08 21:51:46 -0400759 if (!entry->is64)
Kevin O'Connord630d142012-04-26 22:20:56 -0400760 continue;
Gerd Hoffmanna247e672013-11-26 12:57:19 +0100761 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
762 continue;
Kevin O'Connord630d142012-04-26 22:20:56 -0400763 // Move from source list to destination list.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400764 hlist_del(&entry->node);
765 hlist_add(&entry->node, last);
Gerd Hoffmann95c5afc2013-11-26 11:21:23 +0100766 last = &entry->node.next;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200767 }
768}
769
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200770static struct pci_region_entry *
771pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
Alexey Korolev030288f2012-04-19 17:44:55 +1200772 int bar, u64 size, u64 align, int type, int is64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200773{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200774 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
775 if (!entry) {
776 warn_noalloc();
777 return NULL;
778 }
779 memset(entry, 0, sizeof(*entry));
780 entry->dev = dev;
781 entry->bar = bar;
782 entry->size = size;
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400783 entry->align = align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200784 entry->is64 = is64;
785 entry->type = type;
786 // Insert into list in sorted order.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400787 struct hlist_node **pprev;
788 struct pci_region_entry *pos;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400789 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400790 if (pos->align < align || (pos->align == align && pos->size < size))
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200791 break;
792 }
Kevin O'Connora88c1972013-06-08 21:51:46 -0400793 hlist_add(&entry->node, pprev);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200794 return entry;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200795}
796
Igor Mammedovb06d9562021-11-29 06:48:12 -0500797typedef enum hotplug_type_t {
798 HOTPLUG_NO_SUPPORTED = 0,
799 HOTPLUG_PCIE,
800 HOTPLUG_SHPC
801} hotplug_type_t;
802
803static hotplug_type_t pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300804{
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300805 u8 shpc_cap;
806
807 if (pcie_cap) {
808 u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf,
809 pcie_cap + PCI_EXP_FLAGS);
810 u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >>
811 (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1));
Igor Mammedovbba24ef2021-11-29 06:48:11 -0500812
813 if (port_type == PCI_EXP_TYPE_PCI_BRIDGE)
814 goto check_shpc;
815
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300816 u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) ||
817 (port_type == PCI_EXP_TYPE_ROOT_PORT);
818 /*
819 * PCI Express SPEC, 7.8.2:
820 * Slot Implemented – When Set, this bit indicates that the Link
821 * HwInit associated with this Port is connected to a slot (as
822 * compared to being connected to a system-integrated device or
823 * being disabled).
824 * This bit is valid for Downstream Ports. This bit is undefined
825 * for Upstream Ports.
826 */
827 u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT;
828
Igor Mammedovb06d9562021-11-29 06:48:12 -0500829 return downstream_port && slot_implemented ?
830 HOTPLUG_PCIE : HOTPLUG_NO_SUPPORTED;
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300831 }
832
Igor Mammedovbba24ef2021-11-29 06:48:11 -0500833check_shpc:
Aleksandr Bezzubikov7de1f652017-08-18 02:33:19 +0300834 shpc_cap = pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0);
Igor Mammedovb06d9562021-11-29 06:48:12 -0500835 return !!shpc_cap ? HOTPLUG_SHPC : HOTPLUG_NO_SUPPORTED;
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300836}
837
Kevin O'Connor62ff9d52016-02-03 00:47:27 -0500838/* Test whether bridge support forwarding of transactions
839 * of a specific type.
840 * Note: disables bridge's window registers as a side effect.
841 */
842static int pci_bridge_has_region(struct pci_device *pci,
843 enum pci_region_type region_type)
844{
845 u8 base;
846
847 switch (region_type) {
848 case PCI_REGION_TYPE_IO:
849 base = PCI_IO_BASE;
850 break;
851 case PCI_REGION_TYPE_PREFMEM:
852 base = PCI_PREF_MEMORY_BASE;
853 break;
854 default:
855 /* Regular memory support is mandatory */
856 return 1;
857 }
858
859 pci_config_writeb(pci->bdf, base, 0xFF);
860
861 return pci_config_readb(pci->bdf, base) != 0;
862}
863
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200864static int pci_bios_check_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200865{
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400866 dprintf(1, "PCI: check devices\n");
867
868 // Calculate resources needed for regular (non-bus) devices.
869 struct pci_device *pci;
870 foreachpci(pci) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200871 if (pci->class == PCI_CLASS_BRIDGE_PCI)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400872 busses[pci->secondary_bus].bus_dev = pci;
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200873
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400874 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
Marcel Apfelbaum0fe4c9e2015-02-16 19:29:20 +0200875 if (!bus->bus_dev)
876 /*
877 * Resources for all root busses go in busses[0]
878 */
879 bus = &busses[0];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400880 int i;
881 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200882 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
883 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
884 continue;
Alexey Korolev030288f2012-04-19 17:44:55 +1200885 int type, is64;
886 u64 size;
887 pci_bios_get_bar(pci, i, &type, &size, &is64);
888 if (size == 0)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400889 continue;
890
Alexey Korolev5fa24b52012-04-18 17:31:58 +1200891 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
892 size = PCI_DEVICE_MEM_MIN;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200893 struct pci_region_entry *entry = pci_region_create_entry(
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400894 bus, pci, i, size, size, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200895 if (!entry)
896 return -1;
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400897
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200898 if (is64)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400899 i++;
900 }
901 }
902
903 // Propagate required bus resources to parent busses.
904 int secondary_bus;
905 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
906 struct pci_bus *s = &busses[secondary_bus];
907 if (!s->bus_dev)
908 continue;
909 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
Marcel Apfelbaum0fe4c9e2015-02-16 19:29:20 +0200910 if (!parent->bus_dev)
911 /*
912 * Resources for all root busses go in busses[0]
913 */
914 parent = &busses[0];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400915 int type;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300916 u16 bdf = s->bus_dev->bdf;
917 u8 pcie_cap = pci_find_capability(bdf, PCI_CAP_ID_EXP, 0);
918 u8 qemu_cap = pci_find_resource_reserve_capability(bdf);
919
Igor Mammedovb06d9562021-11-29 06:48:12 -0500920 hotplug_type_t hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200921 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Alexey Korolev030288f2012-04-19 17:44:55 +1200922 u64 align = (type == PCI_REGION_TYPE_IO) ?
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200923 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
Marcel Apfelbaum0784d042014-04-10 21:55:22 +0300924 if (!pci_bridge_has_region(s->bus_dev, type))
925 continue;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300926 u64 size = 0;
927 if (qemu_cap) {
928 u32 tmp_size;
929 u64 tmp_size_64;
930 switch(type) {
931 case PCI_REGION_TYPE_IO:
932 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO) |
933 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO + 4) << 32);
934 if (tmp_size_64 != (u64)-1) {
935 size = tmp_size_64;
936 }
937 break;
938 case PCI_REGION_TYPE_MEM:
939 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_MEM);
940 if (tmp_size != (u32)-1) {
941 size = tmp_size;
942 }
943 break;
944 case PCI_REGION_TYPE_PREFMEM:
945 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_32);
946 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64) |
947 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64 + 4) << 32);
948 if (tmp_size != (u32)-1 && tmp_size_64 == (u64)-1) {
949 size = tmp_size;
950 } else if (tmp_size == (u32)-1 && tmp_size_64 != (u64)-1) {
951 size = tmp_size_64;
952 } else if (tmp_size != (u32)-1 && tmp_size_64 != (u64)-1) {
953 dprintf(1, "PCI: resource reserve cap PREF32 and PREF64"
954 " conflict\n");
955 }
956 break;
957 default:
958 break;
959 }
960 }
Alexey Korolev37c111f2012-04-26 16:51:05 +1200961 if (pci_region_align(&s->r[type]) > align)
962 align = pci_region_align(&s->r[type]);
963 u64 sum = pci_region_sum(&s->r[type]);
Gerd Hoffmann96a8d132022-09-09 10:17:15 +0200964 int is64 = pci_bios_bridge_region_is64(&s->r[type],
965 s->bus_dev, type);
Igor Mammedovb06d9562021-11-29 06:48:12 -0500966 int resource_optional = 0;
967 if (hotplug_support == HOTPLUG_PCIE)
968 resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
Gerd Hoffmann96a8d132022-09-09 10:17:15 +0200969 if (hotplug_support && pci_use_64bit && is64 && (type == PCI_REGION_TYPE_PREFMEM))
970 align = (u64)1 << (CPUPhysBits - 11);
971 if (align > sum && hotplug_support && !resource_optional)
Marcel Apfelbaumc6e298e2014-04-10 21:55:21 +0300972 sum = align; /* reserve min size for hot-plug */
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300973 if (size > sum) {
974 dprintf(1, "PCI: QEMU resource reserve cap: "
975 "size %08llx type %s\n",
976 size, region_type_name[type]);
977 if (type != PCI_REGION_TYPE_IO) {
978 size = ALIGN(size, align);
979 }
980 } else {
981 size = ALIGN(sum, align);
982 }
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200983 // entry->bar is -1 if the entry represents a bridge region
984 struct pci_region_entry *entry = pci_region_create_entry(
Alexey Korolevac0cd582012-04-19 17:48:54 +1200985 parent, s->bus_dev, -1, size, align, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200986 if (!entry)
987 return -1;
Alexey Korolev030288f2012-04-19 17:44:55 +1200988 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
Alexey Korolevf3c2b062012-04-18 17:26:43 +1200989 entry->dev->secondary_bus, size,
990 region_type_name[entry->type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200991 }
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400992 }
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200993 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400994}
995
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400996
997/****************************************************************
998 * BAR assignment
999 ****************************************************************/
1000
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -04001001// Setup region bases (given the regions' size and alignment)
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001002static int pci_bios_init_root_regions_io(struct pci_bus *bus)
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001003{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001004 /*
1005 * QEMU I/O address space usage:
1006 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
1007 * 1000 - 9fff free
1008 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
1009 * b000 - bfff power management (PORT_ACPI_PM_BASE)
1010 * [ qemu 1.4+ implements pci config registers
1011 * properly so guests can place the registers
1012 * where they want, on older versions its fixed ]
1013 * c000 - ffff free, traditionally used for pci io
1014 */
1015 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
1016 u64 sum = pci_region_sum(r_io);
1017 if (sum < 0x4000) {
1018 /* traditional region is big enougth, use it */
1019 r_io->base = 0xc000;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +02001020 } else if (sum < pci_io_low_end - 0x1000) {
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001021 /* use the larger region at 0x1000 */
1022 r_io->base = 0x1000;
1023 } else {
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +02001024 /* not enouth io address space -> error out */
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001025 return -1;
1026 }
1027 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
1028 return 0;
1029}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001030
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001031static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
1032{
Alexey Korolev37c111f2012-04-26 16:51:05 +12001033 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
1034 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
1035
1036 if (pci_region_align(r_start) < pci_region_align(r_end)) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -04001037 // Swap regions to improve alignment.
Alexey Korolev37c111f2012-04-26 16:51:05 +12001038 r_end = r_start;
1039 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001040 }
Alexey Korolev37c111f2012-04-26 16:51:05 +12001041 u64 sum = pci_region_sum(r_end);
1042 u64 align = pci_region_align(r_end);
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +02001043 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
Alexey Korolev37c111f2012-04-26 16:51:05 +12001044 sum = pci_region_sum(r_start);
1045 align = pci_region_align(r_start);
1046 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
1047
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +02001048 if ((r_start->base < pcimem_start) ||
1049 (r_start->base > pcimem_end))
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -04001050 // Memory range requested is larger than available.
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001051 return -1;
1052 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001053}
1054
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001055#define PCI_IO_SHIFT 8
1056#define PCI_MEMORY_SHIFT 16
1057#define PCI_PREF_MEMORY_SHIFT 16
1058
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001059static void
Alexey Korolev35a770f2012-04-19 17:47:19 +12001060pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001061{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001062 if (entry->bar >= 0) {
Kevin O'Connor7b673002016-02-03 03:03:15 -05001063 dprintf(1, "PCI: map device bdf=%pP"
Alexey Korolev030288f2012-04-19 17:44:55 +12001064 " bar %d, addr %08llx, size %08llx [%s]\n",
Kevin O'Connor7b673002016-02-03 03:03:15 -05001065 entry->dev,
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001066 entry->bar, addr, entry->size, region_type_name[entry->type]);
1067
Alexey Korolev030288f2012-04-19 17:44:55 +12001068 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
Alexey Korolev3a297162012-04-18 17:22:29 +12001069 return;
1070 }
1071
Kevin O'Connor7b673002016-02-03 03:03:15 -05001072 u16 bdf = entry->dev->bdf;
Alexey Korolev030288f2012-04-19 17:44:55 +12001073 u64 limit = addr + entry->size - 1;
Alexey Korolev3a297162012-04-18 17:22:29 +12001074 if (entry->type == PCI_REGION_TYPE_IO) {
1075 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
1076 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
1077 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
1078 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
1079 }
1080 if (entry->type == PCI_REGION_TYPE_MEM) {
1081 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
1082 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
1083 }
1084 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
1085 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
1086 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
Alexey Korolev030288f2012-04-19 17:44:55 +12001087 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
1088 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001089 }
1090}
1091
Alexey Korolev35a770f2012-04-19 17:47:19 +12001092static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
1093{
Kevin O'Connor030a58a2013-06-13 21:24:14 -04001094 struct hlist_node *n;
Kevin O'Connora88c1972013-06-08 21:51:46 -04001095 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -04001096 hlist_for_each_entry_safe(entry, n, &r->list, node) {
Alexey Korolev35a770f2012-04-19 17:47:19 +12001097 u64 addr = r->base;
1098 r->base += entry->size;
1099 if (entry->bar == -1)
1100 // Update bus base address if entry is a bridge region
1101 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
1102 pci_region_map_one_entry(entry, addr);
Kevin O'Connora88c1972013-06-08 21:51:46 -04001103 hlist_del(&entry->node);
Alexey Korolev35a770f2012-04-19 17:47:19 +12001104 free(entry);
Alexey Korolev35a770f2012-04-19 17:47:19 +12001105 }
1106}
1107
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001108static void pci_bios_map_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001109{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001110 if (pci_bios_init_root_regions_io(busses))
1111 panic("PCI: out of I/O address space\n");
1112
Gerd Hoffmannc72370e2013-11-26 12:51:30 +01001113 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
Gerd Hoffmann96a8d132022-09-09 10:17:15 +02001114 if (pci_use_64bit || pci_bios_init_root_regions_mem(busses)) {
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001115 struct pci_region r64_mem, r64_pref;
Kevin O'Connora88c1972013-06-08 21:51:46 -04001116 r64_mem.list.first = NULL;
1117 r64_pref.list.first = NULL;
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001118 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
1119 &r64_mem);
1120 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
1121 &r64_pref);
1122
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001123 if (pci_bios_init_root_regions_mem(busses))
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001124 panic("PCI: out of 32bit address space\n");
1125
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001126 u64 sum_mem = pci_region_sum(&r64_mem);
1127 u64 sum_pref = pci_region_sum(&r64_pref);
1128 u64 align_mem = pci_region_align(&r64_mem);
1129 u64 align_pref = pci_region_align(&r64_pref);
1130
Gerd Hoffmann0f474d02013-11-26 12:48:20 +01001131 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
1132 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
1133 r64_mem.base = 0x100000000LL + RamSizeOver4G;
Gerd Hoffmannbcfed7e2022-09-09 10:16:31 +02001134 if (CPUPhysBits) {
1135 u64 top = 1LL << CPUPhysBits;
1136 u64 size = (ALIGN(sum_mem, (1LL<<30)) +
1137 ALIGN(sum_pref, (1LL<<30)));
Gerd Hoffmann96a8d132022-09-09 10:17:15 +02001138 if (pci_use_64bit)
1139 size = ALIGN(size, (1LL<<(CPUPhysBits-3)));
Gerd Hoffmannbcfed7e2022-09-09 10:16:31 +02001140 if (r64_mem.base < top - size) {
1141 r64_mem.base = top - size;
1142 }
1143 }
Gerd Hoffmannf21c0062013-11-26 11:08:17 +01001144 r64_mem.base = ALIGN(r64_mem.base, align_mem);
1145 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
1146 r64_pref.base = r64_mem.base + sum_mem;
1147 r64_pref.base = ALIGN(r64_pref.base, align_pref);
1148 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001149 pcimem64_start = r64_mem.base;
1150 pcimem64_end = r64_pref.base + sum_pref;
Gerd Hoffmannf21c0062013-11-26 11:08:17 +01001151 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
Gerd Hoffmannc72370e2013-11-26 12:51:30 +01001152 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001153
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001154 pci_region_map_entries(busses, &r64_mem);
1155 pci_region_map_entries(busses, &r64_pref);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001156 } else {
1157 // no bars mapped high -> drop 64bit window (see dsdt)
1158 pcimem64_start = 0;
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001159 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -04001160 // Map regions on each device.
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001161 int bus;
1162 for (bus = 0; bus<=MaxPCIBus; bus++) {
1163 int type;
Alexey Korolev35a770f2012-04-19 17:47:19 +12001164 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
1165 pci_region_map_entries(busses, &busses[bus].r[type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001166 }
1167}
1168
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001169
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001170/****************************************************************
1171 * Main setup code
1172 ****************************************************************/
Isaku Yamahataf4416662010-06-22 17:57:52 +09001173
Kevin O'Connor0525d292008-07-04 06:18:30 -04001174void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -04001175pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -04001176{
Kevin O'Connora2a86e22013-02-13 19:35:12 -05001177 if (!CONFIG_QEMU)
Kevin O'Connor0525d292008-07-04 06:18:30 -04001178 return;
1179
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -04001180 dprintf(3, "pci setup\n");
1181
Gerd Hoffmann96a8d132022-09-09 10:17:15 +02001182 if (CPUPhysBits >= 36 && CPULongMode && RamSizeOver4G)
1183 pci_use_64bit = 1;
1184
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001185 dprintf(1, "=== PCI bus & bridge init ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +02001186 if (pci_probe_host() != 0) {
1187 return;
1188 }
Isaku Yamahataf4416662010-06-22 17:57:52 +09001189 pci_bios_init_bus();
1190
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001191 dprintf(1, "=== PCI device probing ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +02001192 pci_probe_devices();
Kevin O'Connor37956dd2011-06-21 22:22:58 -04001193
Kevin O'Connorb1c35f22012-11-26 11:05:32 -05001194 pcimem_start = RamSize;
1195 pci_bios_init_platform();
1196
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001197 dprintf(1, "=== PCI new allocation pass #1 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001198 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connor28a20e12011-10-15 11:07:30 -04001199 if (!busses) {
1200 warn_noalloc();
1201 return;
1202 }
1203 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001204 if (pci_bios_check_devices(busses))
1205 return;
1206
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001207 dprintf(1, "=== PCI new allocation pass #2 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001208 pci_bios_map_devices(busses);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001209
Kevin O'Connor3f2288f2011-10-15 12:02:14 -04001210 pci_bios_init_devices();
Gerd Hoffmann8e301472011-08-09 17:22:42 +02001211
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001212 free(busses);
Alex Williamson7adfd712013-03-20 10:58:47 -06001213
1214 pci_enable_default_vga();
Kevin O'Connor0525d292008-07-04 06:18:30 -04001215}