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Kevin O'Connor59f02832009-10-12 10:09:15 -04001// Code for handling OHCI USB controllers.
2//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4//
5// This file may be distributed under the terms of the GNU LGPLv3 license.
6
7#include "util.h" // dprintf
8#include "pci.h" // pci_bdf_to_bus
9#include "config.h" // CONFIG_*
Kevin O'Connor1c46a542009-10-17 23:53:32 -040010#include "usb-ohci.h" // struct ohci_hcca
11#include "pci_regs.h" // PCI_BASE_ADDRESS_0
Kevin O'Connor59f02832009-10-12 10:09:15 -040012#include "usb.h" // struct usb_s
13#include "farptr.h" // GET_FLATPTR
Kevin O'Connor59f02832009-10-12 10:09:15 -040014
Kevin O'Connor1c46a542009-10-17 23:53:32 -040015#define FIT (1 << 31)
16
17static int
18start_ohci(struct usb_s *cntl, struct ohci_hcca *hcca)
Kevin O'Connor59f02832009-10-12 10:09:15 -040019{
Kevin O'Connor1c46a542009-10-17 23:53:32 -040020 u32 oldfminterval = readl(&cntl->ohci.regs->fminterval);
21 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
Kevin O'Connor59f02832009-10-12 10:09:15 -040022
Kevin O'Connor1c46a542009-10-17 23:53:32 -040023 // XXX - check if already running?
Kevin O'Connor59f02832009-10-12 10:09:15 -040024
Kevin O'Connor1c46a542009-10-17 23:53:32 -040025 // Do reset
26 writel(&cntl->ohci.regs->control, OHCI_USB_RESET | oldrwc);
27 readl(&cntl->ohci.regs->control); // flush writes
28 mdelay(50);
Kevin O'Connor59f02832009-10-12 10:09:15 -040029
Kevin O'Connor1c46a542009-10-17 23:53:32 -040030 // Do software init (min 10us, max 2ms)
31 u64 end = calc_future_tsc_usec(10);
32 writel(&cntl->ohci.regs->cmdstatus, OHCI_HCR);
33 for (;;) {
34 u32 status = readl(&cntl->ohci.regs->cmdstatus);
35 if (! status & OHCI_HCR)
36 break;
Kevin O'Connor89eb6242009-10-22 22:30:37 -040037 if (check_time(end)) {
Kevin O'Connor1c46a542009-10-17 23:53:32 -040038 dprintf(1, "Timeout on ohci software reset\n");
39 return -1;
40 }
Kevin O'Connor59f02832009-10-12 10:09:15 -040041 }
42
Kevin O'Connor1c46a542009-10-17 23:53:32 -040043 // Init memory
44 writel(&cntl->ohci.regs->ed_controlhead, (u32)cntl->ohci.control_ed);
45 writel(&cntl->ohci.regs->ed_bulkhead, 0);
46 writel(&cntl->ohci.regs->hcca, (u32)hcca);
47
48 // Init fminterval
49 u32 fi = oldfminterval & 0x3fff;
50 writel(&cntl->ohci.regs->fminterval
51 , (((oldfminterval & FIT) ^ FIT)
52 | fi | (((6 * (fi - 210)) / 7) << 16)));
53 writel(&cntl->ohci.regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
54 readl(&cntl->ohci.regs->control); // flush writes
55
56 // XXX - verify that fminterval was setup correctly.
57
58 // Go into operational state
59 writel(&cntl->ohci.regs->control
60 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
61 | OHCI_USB_OPER | oldrwc));
62 readl(&cntl->ohci.regs->control); // flush writes
63
64 return 0;
Kevin O'Connor59f02832009-10-12 10:09:15 -040065}
66
67static void
Kevin O'Connor1c46a542009-10-17 23:53:32 -040068stop_ohci(struct usb_s *cntl)
Kevin O'Connor59f02832009-10-12 10:09:15 -040069{
Kevin O'Connor1c46a542009-10-17 23:53:32 -040070 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
71 writel(&cntl->ohci.regs->control, oldrwc);
72 readl(&cntl->ohci.regs->control); // flush writes
Kevin O'Connor59f02832009-10-12 10:09:15 -040073}
74
75// Find any devices connected to the root hub.
76static int
77check_ohci_ports(struct usb_s *cntl)
78{
Kevin O'Connor1c46a542009-10-17 23:53:32 -040079 // Turn on power for all devices on roothub.
80 u32 rha = readl(&cntl->ohci.regs->roothub_a);
81 rha &= ~(RH_A_PSM | RH_A_OCPM);
82 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPSC);
83 writel(&cntl->ohci.regs->roothub_b, RH_B_PPCM);
84 mdelay((rha >> 24) * 2);
85
86 // Count and reset connected devices
87 int ports = rha & RH_A_NDP;
88 int totalcount = 0;
89 int i;
90 for (i=0; i<ports; i++)
91 if (readl(&cntl->ohci.regs->roothub_portstatus[i]) & RH_PS_CCS) {
92 writel(&cntl->ohci.regs->roothub_portstatus[i], RH_PS_PRS);
93 totalcount++;
94 }
95 if (!totalcount)
96 // No devices connected
97 goto shutdown;
98
99 mdelay(60); // XXX - should poll instead of using timer.
100
101 totalcount = 0;
102 for (i=0; i<ports; i++) {
103 u32 sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
104 if ((sts & (RH_PS_CCS|RH_PS_PES)) == (RH_PS_CCS|RH_PS_PES)) {
105 int count = configure_usb_device(cntl, !!(sts & RH_PS_LSDA));
106 if (! count)
107 // Shutdown port
108 writel(&cntl->ohci.regs->roothub_portstatus[i]
109 , RH_PS_CCS|RH_PS_LSDA);
110 totalcount += count;
111 }
112 }
113 if (!totalcount)
114 goto shutdown;
115
116 return totalcount;
117
118shutdown:
119 // Turn off power to all ports
120 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPS);
Kevin O'Connor59f02832009-10-12 10:09:15 -0400121 return 0;
122}
123
124int
125ohci_init(struct usb_s *cntl)
126{
127 if (! CONFIG_USB_OHCI)
128 return 0;
129
130 cntl->type = USB_TYPE_OHCI;
131 u32 baseaddr = pci_config_readl(cntl->bdf, PCI_BASE_ADDRESS_0);
132 cntl->ohci.regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
133
134 dprintf(3, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
135 , pci_bdf_to_bus(cntl->bdf), pci_bdf_to_dev(cntl->bdf)
136 , pci_bdf_to_fn(cntl->bdf), cntl->ohci.regs);
137
138 // Enable bus mastering and memory access.
139 pci_config_maskw(cntl->bdf, PCI_COMMAND
140 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
141
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400142 // XXX - check for and disable SMM control?
Kevin O'Connor59f02832009-10-12 10:09:15 -0400143
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400144 // Disable interrupts
145 writel(&cntl->ohci.regs->intrdisable, ~0);
146 writel(&cntl->ohci.regs->intrstatus, ~0);
147
148 // Allocate memory
149 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
150 struct ohci_ed *control_ed = malloc_high(sizeof(*control_ed));
151 if (!hcca || !control_ed) {
152 dprintf(1, "No ram for ohci init\n");
Kevin O'Connor59f02832009-10-12 10:09:15 -0400153 return 0;
154 }
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400155 memset(hcca, 0, sizeof(*hcca));
156 memset(control_ed, 0, sizeof(*control_ed));
157 control_ed->hwINFO = ED_SKIP;
158 cntl->ohci.control_ed = control_ed;
Kevin O'Connor59f02832009-10-12 10:09:15 -0400159
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400160 int ret = start_ohci(cntl, hcca);
161 if (ret)
162 goto err;
163
164 int count = check_ohci_ports(cntl);
165 if (! count)
166 goto err;
167 return count;
168
169err:
170 stop_ohci(cntl);
171 free(hcca);
172 free(control_ed);
Kevin O'Connor59f02832009-10-12 10:09:15 -0400173 return 0;
174}
175
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400176static int
177wait_ed(struct ohci_ed *ed)
178{
179 // XXX - 500ms just a guess
180 u64 end = calc_future_tsc(500);
181 for (;;) {
182 if (ed->hwHeadP == ed->hwTailP)
183 return 0;
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400184 if (check_time(end)) {
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400185 dprintf(1, "Timeout on wait_ed %p\n", ed);
186 return -1;
187 }
188 cpu_relax();
189 }
190}
191
Kevin O'Connor59f02832009-10-12 10:09:15 -0400192int
193ohci_control(u32 endp, int dir, const void *cmd, int cmdsize
194 , void *data, int datasize)
195{
196 if (! CONFIG_USB_OHCI)
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400197 return -1;
Kevin O'Connor59f02832009-10-12 10:09:15 -0400198
199 dprintf(5, "ohci_control %x\n", endp);
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400200 struct usb_s *cntl = endp2cntl(endp);
201 int maxpacket = endp2maxsize(endp);
202 int lowspeed = endp2speed(endp);
203 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
204
205 // Setup transfer descriptors
206 struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
207 tds[0].hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
208 tds[0].hwCBP = (u32)cmd;
209 tds[0].hwNextTD = (u32)&tds[1];
210 tds[0].hwBE = (u32)cmd + cmdsize - 1;
211 tds[1].hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
212 tds[1].hwCBP = datasize ? (u32)data : 0;
213 tds[1].hwNextTD = (u32)&tds[2];
214 tds[1].hwBE = (u32)data + datasize - 1;
215 tds[2].hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
216 tds[2].hwCBP = 0;
217 tds[2].hwNextTD = (u32)&tds[3];
218 tds[2].hwBE = 0;
219
220 // Transfer data
221 struct ohci_ed *ed = cntl->ohci.control_ed;
222 ed->hwINFO = ED_SKIP;
223 barrier();
224 ed->hwHeadP = (u32)&tds[0];
225 ed->hwTailP = (u32)&tds[3];
226 barrier();
227 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
228 writel(&cntl->ohci.regs->cmdstatus, OHCI_CLF);
229
230 int ret = wait_ed(ed);
231 ed->hwINFO = ED_SKIP;
232 udelay(1); // XXX - in case controller still accessing tds
233 free(tds);
234 return ret;
Kevin O'Connor59f02832009-10-12 10:09:15 -0400235}
236
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400237struct ohci_pipe {
238 struct ohci_ed ed;
239 struct usb_pipe pipe;
240 void *data;
241 int count;
242 struct ohci_td *tds;
243};
244
Kevin O'Connor59f02832009-10-12 10:09:15 -0400245struct usb_pipe *
246ohci_alloc_intr_pipe(u32 endp, int period)
247{
248 if (! CONFIG_USB_OHCI)
249 return NULL;
250
251 dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, period);
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400252 struct usb_s *cntl = endp2cntl(endp);
253 int maxpacket = endp2maxsize(endp);
254 int lowspeed = endp2speed(endp);
255 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
256 // XXX - just grab 20 for now.
257 int count = 20;
258 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
259 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
260 void *data = malloc_low(maxpacket * count);
261 if (!pipe || !tds || !data)
262 goto err;
263
264 struct ohci_ed *ed = &pipe->ed;
265 ed->hwHeadP = (u32)&tds[0];
266 ed->hwTailP = (u32)&tds[count-1];
267 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
268 ed->hwNextED = 0;
269
270 int i;
271 for (i=0; i<count-1; i++) {
272 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
273 tds[i].hwCBP = (u32)data + maxpacket * i;
274 tds[i].hwNextTD = (u32)&tds[i+1];
275 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
276 }
277
278 // XXX - need schedule - just add to primary list for now.
279 barrier();
280 struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
281 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
282 hcca->int_table[i] = (u32)ed;
283
284 pipe->data = data;
285 pipe->count = count;
286 pipe->tds = tds;
287 pipe->pipe.endp = endp;
288 return &pipe->pipe;
289
290err:
291 free(pipe);
292 free(tds);
293 free(data);
Kevin O'Connor59f02832009-10-12 10:09:15 -0400294 return NULL;
295}
296
297int
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400298ohci_poll_intr(struct usb_pipe *pipe, void *data)
Kevin O'Connor59f02832009-10-12 10:09:15 -0400299{
300 ASSERT16();
301 if (! CONFIG_USB_OHCI)
302 return -1;
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400303
304 struct ohci_pipe *p = container_of(pipe, struct ohci_pipe, pipe);
305 struct ohci_td *tds = GET_FLATPTR(p->tds);
306 struct ohci_td *head = (void*)GET_FLATPTR(p->ed.hwHeadP);
307 struct ohci_td *tail = (void*)GET_FLATPTR(p->ed.hwTailP);
308 int count = GET_FLATPTR(p->count);
309 int pos = (tail - tds + 1) % count;
310 struct ohci_td *next = &tds[pos];
311 if (head == next)
312 // No intrs found.
313 return -1;
314 // XXX - check for errors.
315
316 // Copy data.
317 u32 endp = GET_FLATPTR(p->pipe.endp);
318 int maxpacket = endp2maxsize(endp);
319 void *pipedata = GET_FLATPTR(p->data);
320 void *intrdata = pipedata + maxpacket * pos;
321 memcpy_far(GET_SEG(SS), data
322 , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
323 , maxpacket);
324
325 // Reenable this td.
326 SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
327 intrdata = pipedata + maxpacket * (tail-tds);
328 SET_FLATPTR(tail->hwCBP, (u32)intrdata);
329 SET_FLATPTR(tail->hwNextTD, (u32)next);
330 SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
331
332 SET_FLATPTR(p->ed.hwTailP, (u32)next);
333
334 return 0;
Kevin O'Connor59f02832009-10-12 10:09:15 -0400335}