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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
Kevin O'Connor9a79b912014-01-15 11:08:22 -05008#include "byteorder.h" // le64_to_cpu
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04009#include "config.h" // CONFIG_*
10#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
Kevin O'Connor4ade5232013-09-18 21:41:48 -040011#include "hw/ata.h" // PORT_ATA1_CMD_BASE
Kevin O'Connor5d369d82013-09-02 20:48:46 -040012#include "hw/pci.h" // pci_config_readl
13#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
14#include "hw/pci_regs.h" // PCI_COMMAND
Kevin O'Connora88c1972013-06-08 21:51:46 -040015#include "list.h" // struct hlist_node
Kevin O'Connor9dea5902013-09-14 20:23:54 -040016#include "malloc.h" // free
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040017#include "memmap.h" // add_e820
18#include "output.h" // dprintf
19#include "paravirt.h" // RamSize
Kevin O'Connor9a79b912014-01-15 11:08:22 -050020#include "romfile.h" // romfile_loadint
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040021#include "string.h" // memset
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040022#include "util.h" // pci_setup
Kevin O'Connor4ade5232013-09-18 21:41:48 -040023#include "x86.h" // outb
Isaku Yamahata72a590e2012-11-28 10:17:33 +010024
Gerd Hoffmann67a3c7c2013-11-26 13:12:04 +010025#define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
26#define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
27#define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090028
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020029static const char *region_type_name[] = {
30 [ PCI_REGION_TYPE_IO ] = "io",
31 [ PCI_REGION_TYPE_MEM ] = "mem",
32 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
33};
34
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020035u64 pcimem_start = BUILD_PCIMEM_START;
36u64 pcimem_end = BUILD_PCIMEM_END;
37u64 pcimem64_start = BUILD_PCIMEM64_START;
38u64 pcimem64_end = BUILD_PCIMEM64_END;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +020039u64 pci_io_low_end = 0xa000;
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020040
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120041struct pci_region_entry {
42 struct pci_device *dev;
43 int bar;
Alexey Korolev030288f2012-04-19 17:44:55 +120044 u64 size;
45 u64 align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120046 int is64;
47 enum pci_region_type type;
Kevin O'Connora88c1972013-06-08 21:51:46 -040048 struct hlist_node node;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120049};
50
Alexey Korolev35a770f2012-04-19 17:47:19 +120051struct pci_region {
Alexey Korolev35a770f2012-04-19 17:47:19 +120052 /* pci region assignments */
53 u64 base;
Kevin O'Connora88c1972013-06-08 21:51:46 -040054 struct hlist_head list;
Alexey Korolev35a770f2012-04-19 17:47:19 +120055};
56
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040057struct pci_bus {
Alexey Korolev35a770f2012-04-19 17:47:19 +120058 struct pci_region r[PCI_REGION_TYPE_COUNT];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -040059 struct pci_device *bus_dev;
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040060};
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020061
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040062static u32 pci_bar(struct pci_device *pci, int region_num)
Isaku Yamahataa65821d2010-06-22 17:57:50 +090063{
64 if (region_num != PCI_ROM_SLOT) {
65 return PCI_BASE_ADDRESS_0 + region_num * 4;
66 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090067
68#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040069 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
Isaku Yamahata5d0de152010-06-22 17:57:51 +090070 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090071}
72
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040073static void
Alexey Korolev030288f2012-04-19 17:44:55 +120074pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
Kevin O'Connor0525d292008-07-04 06:18:30 -040075{
Alexey Korolev030288f2012-04-19 17:44:55 +120076 u32 ofs = pci_bar(pci, bar);
77 pci_config_writel(pci->bdf, ofs, addr);
78 if (is64)
79 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090080}
81
Kevin O'Connor5bab7e62011-10-01 11:33:31 -040082
83/****************************************************************
84 * Misc. device init
85 ****************************************************************/
86
87/* host irqs corresponding to PCI irqs A-D */
88const u8 pci_irqs[4] = {
89 10, 10, 11, 11
90};
91
Alex Williamsondbb7a662013-02-21 09:12:23 -070092static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
93{
94 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
95
96 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
97}
98
99static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
100 dummy_pci_slot_get_irq;
Alex Williamsonb9490402013-02-15 14:11:41 -0700101
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400102// Return the global irq number corresponding to a host bus device irq pin.
Alex Williamsonb9490402013-02-15 14:11:41 -0700103static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400104{
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200105 int slot_addend = 0;
106
107 while (pci->parent != NULL) {
108 slot_addend += pci_bdf_to_dev(pci->bdf);
109 pci = pci->parent;
110 }
111 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400112 return pci_irqs[(pin - 1 + slot_addend) & 3];
Kevin O'Connor0525d292008-07-04 06:18:30 -0400113}
114
Alex Williamsonb9490402013-02-15 14:11:41 -0700115static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
116{
117 int irq, slot, pin_addend = 0;
118
119 while (pci->parent != NULL) {
120 pin_addend += pci_bdf_to_dev(pci->bdf);
121 pci = pci->parent;
122 }
123 slot = pci_bdf_to_dev(pci->bdf);
124
125 switch (slot) {
126 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
127 with a different starting index - see q35-acpi-dsdt.dsl */
128 case 0 ... 24:
129 irq = pci_irqs[(pin - 1 + pin_addend + slot) & 3];
130 break;
131 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
132 case 25 ... 31:
133 irq = pci_irqs[(pin - 1 + pin_addend) & 3];
134 break;
135 }
136
137 return irq;
138}
139
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400140/* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500141static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400142{
143 int i, irq;
144 u8 elcr[2];
145
146 elcr[0] = 0x00;
147 elcr[1] = 0x00;
148 for (i = 0; i < 4; i++) {
149 irq = pci_irqs[i];
150 /* set to trigger level */
151 elcr[irq >> 3] |= (1 << (irq & 7));
152 /* activate irq remapping in PIIX */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400153 pci_config_writeb(pci->bdf, 0x60 + i, irq);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400154 }
155 outb(elcr[0], 0x4d0);
156 outb(elcr[1], 0x4d1);
157 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
158}
159
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100160/* ICH9 LPC PCI to ISA bridge */
161/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500162static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100163{
164 u16 bdf = dev->bdf;
165 int i, irq;
166 u8 elcr[2];
167
168 elcr[0] = 0x00;
169 elcr[1] = 0x00;
170
171 for (i = 0; i < 4; i++) {
172 irq = pci_irqs[i];
173 /* set to trigger level */
174 elcr[irq >> 3] |= (1 << (irq & 7));
175
176 /* activate irq remapping in LPC */
177
178 /* PIRQ[A-D] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700179 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100180 /* PIRQ[E-H] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700181 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100182 }
183 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
184 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
185 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
186
187 /* pm io base */
188 pci_config_writel(bdf, ICH9_LPC_PMBASE,
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200189 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100190
191 /* acpi enable, SCI: IRQ9 000b = irq9*/
192 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
193
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200194 acpi_pm1a_cnt = acpi_pm_base + 0x04;
195 pmtimer_setup(acpi_pm_base + 0x08);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100196}
197
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500198static void storage_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400199{
200 /* IDE: we map it as in ISA mode */
Alexey Korolev030288f2012-04-19 17:44:55 +1200201 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
202 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
203 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
204 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400205}
206
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400207/* PIIX3/PIIX4 IDE */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500208static void piix_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400209{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400210 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400211 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
212 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400213}
214
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500215static void pic_ibm_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400216{
217 /* PIC, IBM, MPIC & MPIC2 */
Alexey Korolev030288f2012-04-19 17:44:55 +1200218 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400219}
220
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500221static void apple_macio_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400222{
223 /* macio bridge */
Alexey Korolev030288f2012-04-19 17:44:55 +1200224 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400225}
226
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200227static void piix4_pm_config_setup(u16 bdf)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400228{
229 // acpi sci is hardwired to 9
230 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
231
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200232 pci_config_writel(bdf, 0x40, acpi_pm_base | 1);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400233 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200234 pci_config_writel(bdf, 0x90, (acpi_pm_base + 0x100) | 1);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400235 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200236}
237
238static int PiixPmBDF = -1;
239
240/* PIIX4 Power Management device (for ACPI) */
241static void piix4_pm_setup(struct pci_device *pci, void *arg)
242{
243 PiixPmBDF = pci->bdf;
244 piix4_pm_config_setup(pci->bdf);
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200245
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200246 acpi_pm1a_cnt = acpi_pm_base + 0x04;
247 pmtimer_setup(acpi_pm_base + 0x08);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400248}
249
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100250/* ICH9 SMBUS */
251/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500252static void ich9_smbus_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100253{
254 u16 bdf = dev->bdf;
255 /* map smbus into io space */
256 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200257 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100258
259 /* enable SMBus */
260 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
261}
262
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400263static const struct pci_device_id pci_device_tbl[] = {
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500264 /* PIIX3/PIIX4 PCI to ISA bridge */
265 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500266 piix_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500267 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500268 piix_isa_bridge_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100269 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500270 mch_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500271
272 /* STORAGE IDE */
273 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500274 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500275 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500276 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500277 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500278 storage_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500279
280 /* PIC, IBM, MIPC & MPIC2 */
281 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500282 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500283 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500284 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500285
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400286 /* PIIX4 Power Management device (for ACPI) */
287 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500288 piix4_pm_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100289 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500290 ich9_smbus_setup),
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400291
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500292 /* 0xff00 */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500293 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
294 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500295
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400296 PCI_DEVICE_END,
297};
298
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200299void pci_resume(void)
300{
301 if (!CONFIG_QEMU) {
302 return;
303 }
304
305 if (PiixPmBDF >= 0) {
306 piix4_pm_config_setup(PiixPmBDF);
307 }
308}
309
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400310static void pci_bios_init_device(struct pci_device *pci)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400311{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400312 u16 bdf = pci->bdf;
Kevin O'Connor99e37c42011-10-01 10:47:21 -0400313 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
314 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400315 , pci->vendor, pci->device);
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400316
Kevin O'Connor0525d292008-07-04 06:18:30 -0400317 /* map the interrupt */
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400318 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
319 if (pin != 0)
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200320 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
Kevin O'Connor0525d292008-07-04 06:18:30 -0400321
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400322 pci_init_device(pci_device_tbl, pci, NULL);
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500323
324 /* enable memory mappings */
Isaku Yamahatad146ab82012-11-28 10:17:32 +0100325 pci_config_maskw(bdf, PCI_COMMAND, 0,
326 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400327}
328
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400329static void pci_bios_init_devices(void)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900330{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400331 struct pci_device *pci;
332 foreachpci(pci) {
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400333 pci_bios_init_device(pci);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900334 }
335}
336
Alex Williamson7adfd712013-03-20 10:58:47 -0600337static void pci_enable_default_vga(void)
338{
339 struct pci_device *pci;
340
341 foreachpci(pci) {
342 if (is_pci_vga(pci)) {
343 dprintf(1, "PCI: Using %02x:%02x.%x for primary VGA\n",
344 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
345 pci_bdf_to_fn(pci->bdf));
346 return;
347 }
348 }
349
350 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
351 if (!pci) {
352 dprintf(1, "PCI: No VGA devices found\n");
353 return;
354 }
355
356 dprintf(1, "PCI: Enabling %02x:%02x.%x for primary VGA\n",
357 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
358 pci_bdf_to_fn(pci->bdf));
359
360 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
361 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
362
363 while (pci->parent) {
364 pci = pci->parent;
365
366 dprintf(1, "PCI: Setting VGA enable on bridge %02x:%02x.%x\n",
367 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
368 pci_bdf_to_fn(pci->bdf));
369
370 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
371 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
372 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
373 }
374}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400375
376/****************************************************************
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500377 * Platform device initialization
378 ****************************************************************/
379
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500380static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500381{
382 if (RamSize <= 0x80000000)
383 pcimem_start = 0x80000000;
384 else if (RamSize <= 0xc0000000)
385 pcimem_start = 0xc0000000;
Alex Williamsonb9490402013-02-15 14:11:41 -0700386
387 pci_slot_get_irq = piix_pci_slot_get_irq;
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500388}
389
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500390static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100391{
392 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
393 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
394
395 /* setup mmconfig */
396 u16 bdf = dev->bdf;
397 u32 upper = addr >> 32;
398 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
399 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
400 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
401 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
402 add_e820(addr, size, E820_RESERVED);
403
404 /* setup pci i/o window (above mmconfig) */
405 pcimem_start = addr + size;
Alex Williamsonb9490402013-02-15 14:11:41 -0700406
407 pci_slot_get_irq = mch_pci_slot_get_irq;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200408
409 /* setup io address space */
410 if (acpi_pm_base < 0x1000)
411 pci_io_low_end = 0x10000;
412 else
413 pci_io_low_end = acpi_pm_base;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100414}
415
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500416static const struct pci_device_id pci_platform_tbl[] = {
417 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500418 i440fx_mem_addr_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100419 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500420 mch_mem_addr_setup),
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500421 PCI_DEVICE_END
422};
423
424static void pci_bios_init_platform(void)
425{
426 struct pci_device *pci;
427 foreachpci(pci) {
428 pci_init_device(pci_platform_tbl, pci, NULL);
429 }
430}
431
432
433/****************************************************************
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400434 * Bus initialization
435 ****************************************************************/
436
Isaku Yamahataf4416662010-06-22 17:57:52 +0900437static void
438pci_bios_init_bus_rec(int bus, u8 *pci_bus)
439{
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400440 int bdf;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900441 u16 class;
442
443 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
444
445 /* prevent accidental access to unintended devices */
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400446 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900447 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
448 if (class == PCI_CLASS_BRIDGE_PCI) {
449 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
450 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
451 }
452 }
453
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400454 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900455 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
456 if (class != PCI_CLASS_BRIDGE_PCI) {
457 continue;
458 }
459 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
460
461 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
462 if (pribus != bus) {
463 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
464 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
465 } else {
466 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
467 }
468
469 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
470 (*pci_bus)++;
471 if (*pci_bus != secbus) {
472 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
473 secbus, *pci_bus);
474 secbus = *pci_bus;
475 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
476 } else {
477 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
478 }
479
480 /* set to max for access to all subordinate buses.
481 later set it to accurate value */
482 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
483 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
484
485 pci_bios_init_bus_rec(secbus, pci_bus);
486
487 if (subbus != *pci_bus) {
488 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
489 subbus, *pci_bus);
490 subbus = *pci_bus;
491 } else {
492 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
493 }
494 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
495 }
496}
497
498static void
499pci_bios_init_bus(void)
500{
501 u8 pci_bus = 0;
502 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200503}
504
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400505
506/****************************************************************
507 * Bus sizing
508 ****************************************************************/
509
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400510static void
Alexey Korolev030288f2012-04-19 17:44:55 +1200511pci_bios_get_bar(struct pci_device *pci, int bar,
512 int *ptype, u64 *psize, int *pis64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200513{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400514 u32 ofs = pci_bar(pci, bar);
515 u16 bdf = pci->bdf;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200516 u32 old = pci_config_readl(bdf, ofs);
Alexey Korolev030288f2012-04-19 17:44:55 +1200517 int is64 = 0, type = PCI_REGION_TYPE_MEM;
518 u64 mask;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200519
520 if (bar == PCI_ROM_SLOT) {
521 mask = PCI_ROM_ADDRESS_MASK;
522 pci_config_writel(bdf, ofs, mask);
523 } else {
Alexey Korolev030288f2012-04-19 17:44:55 +1200524 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200525 mask = PCI_BASE_ADDRESS_IO_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200526 type = PCI_REGION_TYPE_IO;
527 } else {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200528 mask = PCI_BASE_ADDRESS_MEM_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200529 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
530 type = PCI_REGION_TYPE_PREFMEM;
531 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
532 == PCI_BASE_ADDRESS_MEM_TYPE_64);
533 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200534 pci_config_writel(bdf, ofs, ~0);
535 }
Alexey Korolev030288f2012-04-19 17:44:55 +1200536 u64 val = pci_config_readl(bdf, ofs);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200537 pci_config_writel(bdf, ofs, old);
Alexey Korolev030288f2012-04-19 17:44:55 +1200538 if (is64) {
539 u32 hold = pci_config_readl(bdf, ofs + 4);
540 pci_config_writel(bdf, ofs + 4, ~0);
541 u32 high = pci_config_readl(bdf, ofs + 4);
542 pci_config_writel(bdf, ofs + 4, hold);
543 val |= ((u64)high << 32);
544 mask |= ((u64)0xffffffff << 32);
545 *psize = (~(val & mask)) + 1;
546 } else {
547 *psize = ((~(val & mask)) + 1) & 0xffffffff;
548 }
549 *ptype = type;
550 *pis64 = is64;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200551}
552
Alexey Korolevac0cd582012-04-19 17:48:54 +1200553static int pci_bios_bridge_region_is64(struct pci_region *r,
554 struct pci_device *pci, int type)
555{
556 if (type != PCI_REGION_TYPE_PREFMEM)
557 return 0;
558 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
559 if (!pmem) {
560 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
561 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
562 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
563 }
564 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
565 return 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400566 struct pci_region_entry *entry;
567 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolevac0cd582012-04-19 17:48:54 +1200568 if (!entry->is64)
569 return 0;
Alexey Korolevac0cd582012-04-19 17:48:54 +1200570 }
571 return 1;
572}
573
Alexey Korolev37c111f2012-04-26 16:51:05 +1200574static u64 pci_region_align(struct pci_region *r)
575{
Kevin O'Connora88c1972013-06-08 21:51:46 -0400576 struct pci_region_entry *entry;
577 hlist_for_each_entry(entry, &r->list, node) {
578 // The first entry in the sorted list has the largest alignment
579 return entry->align;
580 }
581 return 1;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200582}
583
584static u64 pci_region_sum(struct pci_region *r)
585{
Alexey Korolev37c111f2012-04-26 16:51:05 +1200586 u64 sum = 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400587 struct pci_region_entry *entry;
588 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolev37c111f2012-04-26 16:51:05 +1200589 sum += entry->size;
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400590 }
591 return sum;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200592}
593
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200594static void pci_region_migrate_64bit_entries(struct pci_region *from,
595 struct pci_region *to)
596{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400597 struct hlist_node *n, **last = &to->list.first;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400598 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400599 hlist_for_each_entry_safe(entry, n, &from->list, node) {
Kevin O'Connora88c1972013-06-08 21:51:46 -0400600 if (!entry->is64)
Kevin O'Connord630d142012-04-26 22:20:56 -0400601 continue;
Gerd Hoffmanna247e672013-11-26 12:57:19 +0100602 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
603 continue;
Kevin O'Connord630d142012-04-26 22:20:56 -0400604 // Move from source list to destination list.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400605 hlist_del(&entry->node);
606 hlist_add(&entry->node, last);
Gerd Hoffmann95c5afc2013-11-26 11:21:23 +0100607 last = &entry->node.next;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200608 }
609}
610
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200611static struct pci_region_entry *
612pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
Alexey Korolev030288f2012-04-19 17:44:55 +1200613 int bar, u64 size, u64 align, int type, int is64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200614{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200615 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
616 if (!entry) {
617 warn_noalloc();
618 return NULL;
619 }
620 memset(entry, 0, sizeof(*entry));
621 entry->dev = dev;
622 entry->bar = bar;
623 entry->size = size;
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400624 entry->align = align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200625 entry->is64 = is64;
626 entry->type = type;
627 // Insert into list in sorted order.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400628 struct hlist_node **pprev;
629 struct pci_region_entry *pos;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400630 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400631 if (pos->align < align || (pos->align == align && pos->size < size))
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200632 break;
633 }
Kevin O'Connora88c1972013-06-08 21:51:46 -0400634 hlist_add(&entry->node, pprev);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200635 return entry;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200636}
637
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200638static int pci_bios_check_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200639{
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400640 dprintf(1, "PCI: check devices\n");
641
642 // Calculate resources needed for regular (non-bus) devices.
643 struct pci_device *pci;
644 foreachpci(pci) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200645 if (pci->class == PCI_CLASS_BRIDGE_PCI)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400646 busses[pci->secondary_bus].bus_dev = pci;
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200647
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400648 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
649 int i;
650 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200651 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
652 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
653 continue;
Alexey Korolev030288f2012-04-19 17:44:55 +1200654 int type, is64;
655 u64 size;
656 pci_bios_get_bar(pci, i, &type, &size, &is64);
657 if (size == 0)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400658 continue;
659
Alexey Korolev5fa24b52012-04-18 17:31:58 +1200660 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
661 size = PCI_DEVICE_MEM_MIN;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200662 struct pci_region_entry *entry = pci_region_create_entry(
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400663 bus, pci, i, size, size, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200664 if (!entry)
665 return -1;
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400666
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200667 if (is64)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400668 i++;
669 }
670 }
671
672 // Propagate required bus resources to parent busses.
673 int secondary_bus;
674 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
675 struct pci_bus *s = &busses[secondary_bus];
676 if (!s->bus_dev)
677 continue;
678 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400679 int type;
Marcel Apfelbaumc6e298e2014-04-10 21:55:21 +0300680 u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200681 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Alexey Korolev030288f2012-04-19 17:44:55 +1200682 u64 align = (type == PCI_REGION_TYPE_IO) ?
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200683 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
Marcel Apfelbaum0784d042014-04-10 21:55:22 +0300684 if (!pci_bridge_has_region(s->bus_dev, type))
685 continue;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200686 if (pci_region_align(&s->r[type]) > align)
687 align = pci_region_align(&s->r[type]);
688 u64 sum = pci_region_sum(&s->r[type]);
Marcel Apfelbaumc6e298e2014-04-10 21:55:21 +0300689 if (!sum && shpc_cap)
690 sum = align; /* reserve min size for hot-plug */
Alexey Korolev37c111f2012-04-26 16:51:05 +1200691 u64 size = ALIGN(sum, align);
Alexey Korolevac0cd582012-04-19 17:48:54 +1200692 int is64 = pci_bios_bridge_region_is64(&s->r[type],
693 s->bus_dev, type);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200694 // entry->bar is -1 if the entry represents a bridge region
695 struct pci_region_entry *entry = pci_region_create_entry(
Alexey Korolevac0cd582012-04-19 17:48:54 +1200696 parent, s->bus_dev, -1, size, align, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200697 if (!entry)
698 return -1;
Alexey Korolev030288f2012-04-19 17:44:55 +1200699 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
Alexey Korolevf3c2b062012-04-18 17:26:43 +1200700 entry->dev->secondary_bus, size,
701 region_type_name[entry->type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200702 }
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400703 }
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200704 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400705}
706
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400707
708/****************************************************************
709 * BAR assignment
710 ****************************************************************/
711
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400712// Setup region bases (given the regions' size and alignment)
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100713static int pci_bios_init_root_regions_io(struct pci_bus *bus)
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400714{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100715 /*
716 * QEMU I/O address space usage:
717 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
718 * 1000 - 9fff free
719 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
720 * b000 - bfff power management (PORT_ACPI_PM_BASE)
721 * [ qemu 1.4+ implements pci config registers
722 * properly so guests can place the registers
723 * where they want, on older versions its fixed ]
724 * c000 - ffff free, traditionally used for pci io
725 */
726 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
727 u64 sum = pci_region_sum(r_io);
728 if (sum < 0x4000) {
729 /* traditional region is big enougth, use it */
730 r_io->base = 0xc000;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200731 } else if (sum < pci_io_low_end - 0x1000) {
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100732 /* use the larger region at 0x1000 */
733 r_io->base = 0x1000;
734 } else {
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200735 /* not enouth io address space -> error out */
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100736 return -1;
737 }
738 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
739 return 0;
740}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400741
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100742static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
743{
Alexey Korolev37c111f2012-04-26 16:51:05 +1200744 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
745 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
746
747 if (pci_region_align(r_start) < pci_region_align(r_end)) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400748 // Swap regions to improve alignment.
Alexey Korolev37c111f2012-04-26 16:51:05 +1200749 r_end = r_start;
750 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400751 }
Alexey Korolev37c111f2012-04-26 16:51:05 +1200752 u64 sum = pci_region_sum(r_end);
753 u64 align = pci_region_align(r_end);
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +0200754 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
Alexey Korolev37c111f2012-04-26 16:51:05 +1200755 sum = pci_region_sum(r_start);
756 align = pci_region_align(r_start);
757 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
758
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +0200759 if ((r_start->base < pcimem_start) ||
760 (r_start->base > pcimem_end))
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400761 // Memory range requested is larger than available.
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200762 return -1;
763 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400764}
765
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400766#define PCI_IO_SHIFT 8
767#define PCI_MEMORY_SHIFT 16
768#define PCI_PREF_MEMORY_SHIFT 16
769
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200770static void
Alexey Korolev35a770f2012-04-19 17:47:19 +1200771pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200772{
773 u16 bdf = entry->dev->bdf;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200774 if (entry->bar >= 0) {
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200775 dprintf(1, "PCI: map device bdf=%02x:%02x.%x"
Alexey Korolev030288f2012-04-19 17:44:55 +1200776 " bar %d, addr %08llx, size %08llx [%s]\n",
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200777 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf),
778 entry->bar, addr, entry->size, region_type_name[entry->type]);
779
Alexey Korolev030288f2012-04-19 17:44:55 +1200780 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
Alexey Korolev3a297162012-04-18 17:22:29 +1200781 return;
782 }
783
Alexey Korolev030288f2012-04-19 17:44:55 +1200784 u64 limit = addr + entry->size - 1;
Alexey Korolev3a297162012-04-18 17:22:29 +1200785 if (entry->type == PCI_REGION_TYPE_IO) {
786 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
787 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
788 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
789 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
790 }
791 if (entry->type == PCI_REGION_TYPE_MEM) {
792 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
793 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
794 }
795 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
796 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
797 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
Alexey Korolev030288f2012-04-19 17:44:55 +1200798 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
799 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200800 }
801}
802
Alexey Korolev35a770f2012-04-19 17:47:19 +1200803static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
804{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400805 struct hlist_node *n;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400806 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400807 hlist_for_each_entry_safe(entry, n, &r->list, node) {
Alexey Korolev35a770f2012-04-19 17:47:19 +1200808 u64 addr = r->base;
809 r->base += entry->size;
810 if (entry->bar == -1)
811 // Update bus base address if entry is a bridge region
812 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
813 pci_region_map_one_entry(entry, addr);
Kevin O'Connora88c1972013-06-08 21:51:46 -0400814 hlist_del(&entry->node);
Alexey Korolev35a770f2012-04-19 17:47:19 +1200815 free(entry);
Alexey Korolev35a770f2012-04-19 17:47:19 +1200816 }
817}
818
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400819static void pci_bios_map_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200820{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100821 if (pci_bios_init_root_regions_io(busses))
822 panic("PCI: out of I/O address space\n");
823
Gerd Hoffmannc72370e2013-11-26 12:51:30 +0100824 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100825 if (pci_bios_init_root_regions_mem(busses)) {
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200826 struct pci_region r64_mem, r64_pref;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400827 r64_mem.list.first = NULL;
828 r64_pref.list.first = NULL;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200829 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
830 &r64_mem);
831 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
832 &r64_pref);
833
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100834 if (pci_bios_init_root_regions_mem(busses))
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200835 panic("PCI: out of 32bit address space\n");
836
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200837 u64 sum_mem = pci_region_sum(&r64_mem);
838 u64 sum_pref = pci_region_sum(&r64_pref);
839 u64 align_mem = pci_region_align(&r64_mem);
840 u64 align_pref = pci_region_align(&r64_pref);
841
Gerd Hoffmann0f474d02013-11-26 12:48:20 +0100842 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
843 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
844 r64_mem.base = 0x100000000LL + RamSizeOver4G;
Gerd Hoffmannf21c0062013-11-26 11:08:17 +0100845 r64_mem.base = ALIGN(r64_mem.base, align_mem);
846 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
847 r64_pref.base = r64_mem.base + sum_mem;
848 r64_pref.base = ALIGN(r64_pref.base, align_pref);
849 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200850 pcimem64_start = r64_mem.base;
851 pcimem64_end = r64_pref.base + sum_pref;
Gerd Hoffmannf21c0062013-11-26 11:08:17 +0100852 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
Gerd Hoffmannc72370e2013-11-26 12:51:30 +0100853 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200854
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200855 pci_region_map_entries(busses, &r64_mem);
856 pci_region_map_entries(busses, &r64_pref);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200857 } else {
858 // no bars mapped high -> drop 64bit window (see dsdt)
859 pcimem64_start = 0;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200860 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400861 // Map regions on each device.
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200862 int bus;
863 for (bus = 0; bus<=MaxPCIBus; bus++) {
864 int type;
Alexey Korolev35a770f2012-04-19 17:47:19 +1200865 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
866 pci_region_map_entries(busses, &busses[bus].r[type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200867 }
868}
869
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200870
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400871/****************************************************************
872 * Main setup code
873 ****************************************************************/
Isaku Yamahataf4416662010-06-22 17:57:52 +0900874
Kevin O'Connor0525d292008-07-04 06:18:30 -0400875void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400876pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400877{
Kevin O'Connora2a86e22013-02-13 19:35:12 -0500878 if (!CONFIG_QEMU)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400879 return;
880
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400881 dprintf(3, "pci setup\n");
882
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200883 dprintf(1, "=== PCI bus & bridge init ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200884 if (pci_probe_host() != 0) {
885 return;
886 }
Isaku Yamahataf4416662010-06-22 17:57:52 +0900887 pci_bios_init_bus();
888
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200889 dprintf(1, "=== PCI device probing ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200890 pci_probe_devices();
Kevin O'Connor37956dd2011-06-21 22:22:58 -0400891
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500892 pcimem_start = RamSize;
893 pci_bios_init_platform();
894
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200895 dprintf(1, "=== PCI new allocation pass #1 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400896 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connor28a20e12011-10-15 11:07:30 -0400897 if (!busses) {
898 warn_noalloc();
899 return;
900 }
901 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200902 if (pci_bios_check_devices(busses))
903 return;
904
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200905 dprintf(1, "=== PCI new allocation pass #2 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400906 pci_bios_map_devices(busses);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200907
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400908 pci_bios_init_devices();
Gerd Hoffmann8e301472011-08-09 17:22:42 +0200909
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200910 free(busses);
Alex Williamson7adfd712013-03-20 10:58:47 -0600911
912 pci_enable_default_vga();
Kevin O'Connor0525d292008-07-04 06:18:30 -0400913}