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Nils31eabf92012-01-14 12:11:41 -05001// Geode GX2/LX VGA functions
2//
3// Copyright (C) 2009 Chris Kindt
4//
5// Writen for Google Summer of Code 2009 for the coreboot project
6//
7// This file may be distributed under the terms of the GNU LGPLv3 license.
8
9#ifndef GEODEVGA_H
10#define GEODEVGA_H
11
12#define VRC_INDEX 0xAC1C // Index register
13#define VRC_DATA 0xAC1E // Data register
14#define VR_UNLOCK 0xFC53 // Virtual register unlock code
15
Nils31eabf92012-01-14 12:11:41 -050016// Graphics-specific registers:
17#define OEM_BAR0 0x50
18#define OEM_BAR1 0x54
19#define OEM_BAR2 0x58
20#define OEM_BAR3 0x5C
21
Nils31eabf92012-01-14 12:11:41 -050022#define DC_LOCK_LOCK 0x00000000
23#define DC_LOCK_UNLOCK 0x00004758
24
25/* LX MSRs */
26#define MSR_GLIU0 (1 << 28)
Nils24ddd862012-01-14 12:15:14 -050027#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* LX */
28#define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) /* GX2 */
Kevin O'Connor028f3482014-04-11 12:08:33 -040029#define GLIU0_P2D_RO (MSR_GLIU0 + 0x29)
Nils31eabf92012-01-14 12:11:41 -050030#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
31#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
32#define DC_SPARE 0x80000011
Nils24ddd862012-01-14 12:15:14 -050033#define VP_MSR_CONFIG_GX2 0xc0002001 /* GX2 */
34#define VP_MSR_CONFIG_LX 0x48002001 /* LX */
Christian Gmeinerfad37fd2012-10-01 14:02:48 +020035#define VP_MSR_PADSEL 0x48002011
36
37#define VP_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF
38#define VP_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F
Nils31eabf92012-01-14 12:11:41 -050039
Christian Gmeinerf6930c52012-10-01 14:02:45 +020040/* VP_MSR_CONFIG bits */
41#define VP_MSR_CONFIG_FMT_CRT (0)
42#define VP_MSR_CONFIG_FMT_FP (1 << 3)
43#define VP_MSR_CONFIG_FPC (1 << 15)
44#define VP_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
45
46
Nils31eabf92012-01-14 12:11:41 -050047/* DC REG OFFSET */
48#define DC_UNLOCK 0x0
49#define DC_GENERAL_CFG 0x4
50#define DC_DISPLAY_CFG 0x8
Nils31eabf92012-01-14 12:11:41 -050051#define DC_FB_ST_OFFSET 0x10
52#define DC_CB_ST_OFFSET 0x14
53#define DC_CURS_ST_OFFSET 0x18
54#define DC_GLIU0_MEM_OFFSET 0x84
55
56/* VP REG OFFSET */
57#define VP_VCFG 0x0
58#define VP_DCFG 0x8
59#define VP_MISC 0x50
60
Christian Gmeiner55063762012-10-01 14:02:44 +020061/* FP REG OFFSET */
62#define FP_PT1 0x00
63#define FP_PT2 0x08
64#define FP_PM 0x10
65
Nils31eabf92012-01-14 12:11:41 -050066
67/* DC bits */
Christian Gmeiner1337eb32013-02-14 10:34:37 +010068#define DC_GENERAL_CFG_VGAE (1 << 7)
Christian Gmeiner286e0132012-10-01 14:02:42 +020069#define DC_DISPLAY_CFG_GDEN (1 << 3)
70#define DC_DISPLAY_CFG_TRUP (1 << 6)
Nils31eabf92012-01-14 12:11:41 -050071
72/* VP bits */
Christian Gmeiner286e0132012-10-01 14:02:42 +020073#define VP_DCFG_CRT_EN (1 << 0)
74#define VP_DCFG_HSYNC_EN (1 << 1)
75#define VP_DCFG_VSYNC_EN (1 << 2)
76#define VP_DCFG_DAC_BL_EN (1 << 3)
77#define VP_DCFG_CRT_SKEW (1 << 16)
78#define VP_DCFG_BYP_BOTH (1 << 0)
Nils31eabf92012-01-14 12:11:41 -050079
Christian Gmeiner55063762012-10-01 14:02:44 +020080/* FP bits */
81#define FP_PM_P (1 << 24) /* panel power ctl */
82#define FP_PT2_SCRC (1 << 27) /* panel shift clock retrace activity ctl */
83
Nilse8b184f2012-01-14 12:13:34 -050084/* Mask */
Nils31eabf92012-01-14 12:11:41 -050085#define DC_CFG_MSK 0xf000a6
86
Kevin O'Connord83c87b2013-01-21 01:14:12 -050087int geodevga_setup();
Nils31eabf92012-01-14 12:11:41 -050088
89#endif