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Isaku Yamahataecbe3fd2012-11-28 10:17:36 +01001/*
2 * Bochs/QEMU ACPI DSDT ASL definition
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
9 *
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19/*
20 * Copyright (c) 2010 Isaku Yamahata
21 * yamahata at valinux co jp
22 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
23 */
24
25DefinitionBlock (
26 "q35-acpi-dsdt.aml",// Output Filename
27 "DSDT", // Signature
28 0x01, // DSDT Compliance Revision
29 "BXPC", // OEMID
30 "BXDSDT", // TABLE ID
31 0x2 // OEM Revision
32 )
33{
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010034
Gerd Hoffmannbeaedaa2012-11-28 10:17:39 +010035#include "acpi-dsdt-dbug.dsl"
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +010036
37 Scope (\_SB)
38 {
39 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
40 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
41 Field (PCSB, AnyAcc, NoLock, WriteAsZeros)
42 {
43 PCIB, 8,
44 }
45 }
46
47 /* Zero => PIC mode, One => APIC Mode */
48 Name (\PICF, Zero)
49 Method (\_PIC, 1, NotSerialized)
50 {
51 Store (Arg0, \PICF)
52 }
53
54 /* PCI Bus definition */
55 Scope(\_SB) {
56
57 Device(PCI0) {
58 Name (_HID, EisaId ("PNP0A08"))
59 Name (_CID, EisaId ("PNP0A03"))
60 Name (_ADR, 0x00)
61 Name (_UID, 1)
62
63 // _OSC: based on sample of ACPI3.0b spec
64 Name(SUPP,0) // PCI _OSC Support Field value
65 Name(CTRL,0) // PCI _OSC Control Field value
66 Method(_OSC,4)
67 {
68 // Create DWORD-addressable fields from the Capabilities Buffer
69 CreateDWordField(Arg3,0,CDW1)
70
71 // Check for proper UUID
72 If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
73 {
74 // Create DWORD-addressable fields from the Capabilities Buffer
75 CreateDWordField(Arg3,4,CDW2)
76 CreateDWordField(Arg3,8,CDW3)
77
78 // Save Capabilities DWORD2 & 3
79 Store(CDW2,SUPP)
80 Store(CDW3,CTRL)
81
82 // Always allow native PME, AER (no dependencies)
83 // Never allow SHPC (no SHPC controller in this system)
84 And(CTRL,0x1D,CTRL)
85
86#if 0 // For now, nothing to do
87 If(Not(And(CDW1,1))) // Query flag clear?
88 { // Disable GPEs for features granted native control.
89 If(And(CTRL,0x01)) // Hot plug control granted?
90 {
91 Store(0,HPCE) // clear the hot plug SCI enable bit
92 Store(1,HPCS) // clear the hot plug SCI status bit
93 }
94 If(And(CTRL,0x04)) // PME control granted?
95 {
96 Store(0,PMCE) // clear the PME SCI enable bit
97 Store(1,PMCS) // clear the PME SCI status bit
98 }
99 If(And(CTRL,0x10)) // OS restoring PCI Express cap structure?
100 {
101 // Set status to not restore PCI Express cap structure
102 // upon resume from S3
103 Store(1,S3CR)
104 }
105
106 }
107#endif
108 If(LNotEqual(Arg1,One))
109 { // Unknown revision
110 Or(CDW1,0x08,CDW1)
111 }
112 If(LNotEqual(CDW3,CTRL))
113 { // Capabilities bits were masked
114 Or(CDW1,0x10,CDW1)
115 }
116 // Update DWORD3 in the buffer
117 Store(CTRL,CDW3)
118 } Else {
119 Or(CDW1,4,CDW1) // Unrecognized UUID
120 }
121 Return(Arg3)
122 }
123
124#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
125 Package() { nr##ffff, 0, lnk0, 0 }, \
126 Package() { nr##ffff, 1, lnk1, 0 }, \
127 Package() { nr##ffff, 2, lnk2, 0 }, \
128 Package() { nr##ffff, 3, lnk3, 0 }
129
130#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
131#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
132#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
133#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
134
135#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
136#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
137#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
138#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
139
140#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
Jan Kiszka2114f502012-11-28 10:17:37 +0100141 Package() { nr##ffff, 0, gsi0, 0 }, \
142 Package() { nr##ffff, 1, gsi1, 0 }, \
143 Package() { nr##ffff, 2, gsi2, 0 }, \
144 Package() { nr##ffff, 3, gsi3, 0 }
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100145
146#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
147#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
148#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
149#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
150
151#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
152#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
153#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
154#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
155
156 NAME(PRTP, package()
157 {
158 prt_slot_lnkE(0x0000),
159 prt_slot_lnkF(0x0001),
160 prt_slot_lnkG(0x0002),
161 prt_slot_lnkH(0x0003),
162 prt_slot_lnkE(0x0004),
163 prt_slot_lnkF(0x0005),
164 prt_slot_lnkG(0x0006),
165 prt_slot_lnkH(0x0007),
166 prt_slot_lnkE(0x0008),
167 prt_slot_lnkF(0x0009),
168 prt_slot_lnkG(0x000a),
169 prt_slot_lnkH(0x000b),
170 prt_slot_lnkE(0x000c),
171 prt_slot_lnkF(0x000d),
172 prt_slot_lnkG(0x000e),
173 prt_slot_lnkH(0x000f),
174 prt_slot_lnkE(0x0010),
175 prt_slot_lnkF(0x0011),
176 prt_slot_lnkG(0x0012),
177 prt_slot_lnkH(0x0013),
178 prt_slot_lnkE(0x0014),
179 prt_slot_lnkF(0x0015),
180 prt_slot_lnkG(0x0016),
181 prt_slot_lnkH(0x0017),
182 prt_slot_lnkE(0x0018),
183
184 /* INTA -> PIRQA for slot 25 - 31
185 see the default value of D<N>IR */
186 prt_slot_lnkA(0x0019),
187 prt_slot_lnkA(0x001a),
188 prt_slot_lnkA(0x001b),
189 prt_slot_lnkA(0x001c),
190 prt_slot_lnkA(0x001d),
191
192 /* PCIe->PCI bridge. use PIRQ[E-H] */
193 prt_slot_lnkE(0x001e),
194
195 prt_slot_lnkA(0x001f)
196 })
197
198 NAME(PRTA, package()
199 {
200 prt_slot_gsiE(0x0000),
201 prt_slot_gsiF(0x0001),
202 prt_slot_gsiG(0x0002),
203 prt_slot_gsiH(0x0003),
204 prt_slot_gsiE(0x0004),
205 prt_slot_gsiF(0x0005),
206 prt_slot_gsiG(0x0006),
207 prt_slot_gsiH(0x0007),
208 prt_slot_gsiE(0x0008),
209 prt_slot_gsiF(0x0009),
210 prt_slot_gsiG(0x000a),
211 prt_slot_gsiH(0x000b),
212 prt_slot_gsiE(0x000c),
213 prt_slot_gsiF(0x000d),
214 prt_slot_gsiG(0x000e),
215 prt_slot_gsiH(0x000f),
216 prt_slot_gsiE(0x0010),
217 prt_slot_gsiF(0x0011),
218 prt_slot_gsiG(0x0012),
219 prt_slot_gsiH(0x0013),
220 prt_slot_gsiE(0x0014),
221 prt_slot_gsiF(0x0015),
222 prt_slot_gsiG(0x0016),
223 prt_slot_gsiH(0x0017),
224 prt_slot_gsiE(0x0018),
225
226 /* INTA -> PIRQA for slot 25 - 31, but 30
227 see the default value of D<N>IR */
228 prt_slot_gsiA(0x0019),
229 prt_slot_gsiA(0x001a),
230 prt_slot_gsiA(0x001b),
231 prt_slot_gsiA(0x001c),
232 prt_slot_gsiA(0x001d),
233
234 /* PCIe->PCI bridge. use PIRQ[E-H] */
235 prt_slot_gsiE(0x001e),
236
237 prt_slot_gsiA(0x001f)
238 })
239
240 Method(_PRT, 0, NotSerialized)
241 {
242 /* PCI IRQ routing table, example from ACPI 2.0a specification,
243 section 6.2.8.1 */
244 /* Note: we provide the same info as the PCI routing
245 table of the Bochs BIOS */
246 If (LEqual (\PICF, Zero))
247 {
248 Return (PRTP)
249 }
250 Else
251 {
252 Return (PRTA)
253 }
254 }
255
256 Name (CRES, ResourceTemplate ()
257 {
258 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
259 0x0000, // Address Space Granularity
260 0x0000, // Address Range Minimum
261 0x00FF, // Address Range Maximum
262 0x0000, // Address Translation Offset
263 0x0100, // Address Length
264 ,, )
265 IO (Decode16,
266 0x0CF8, // Address Range Minimum
267 0x0CF8, // Address Range Maximum
268 0x01, // Address Alignment
269 0x08, // Address Length
270 )
271 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
272 0x0000, // Address Space Granularity
273 0x0000, // Address Range Minimum
274 0x0CF7, // Address Range Maximum
275 0x0000, // Address Translation Offset
276 0x0CF8, // Address Length
277 ,, , TypeStatic)
278 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
279 0x0000, // Address Space Granularity
280 0x0D00, // Address Range Minimum
281 0xFFFF, // Address Range Maximum
282 0x0000, // Address Translation Offset
283 0xF300, // Address Length
284 ,, , TypeStatic)
285 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
286 0x00000000, // Address Space Granularity
287 0x000A0000, // Address Range Minimum
288 0x000BFFFF, // Address Range Maximum
289 0x00000000, // Address Translation Offset
290 0x00020000, // Address Length
291 ,, , AddressRangeMemory, TypeStatic)
292 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
293 0x00000000, // Address Space Granularity
294 0xC0000000, // Address Range Minimum
295 0xFEBFFFFF, // Address Range Maximum
296 0x00000000, // Address Translation Offset
297 0x3EC00000, // Address Length
298 ,, PW32, AddressRangeMemory, TypeStatic)
299 })
300 Name (CR64, ResourceTemplate ()
301 {
302 QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
303 0x00000000, // Address Space Granularity
304 0x8000000000, // Address Range Minimum
305 0xFFFFFFFFFF, // Address Range Maximum
306 0x00000000, // Address Translation Offset
307 0x8000000000, // Address Length
308 ,, PW64, AddressRangeMemory, TypeStatic)
309 })
310 Method (_CRS, 0)
311 {
312 /* see see acpi.h, struct bfld */
313 External (BDAT, OpRegionObj)
314 Field(BDAT, QWordAcc, NoLock, Preserve) {
315 P0S, 64,
316 P0E, 64,
317 P0L, 64,
318 P1S, 64,
319 P1E, 64,
320 P1L, 64,
321 }
322 Field(BDAT, DWordAcc, NoLock, Preserve) {
323 P0SL, 32,
324 P0SH, 32,
325 P0EL, 32,
326 P0EH, 32,
327 P0LL, 32,
328 P0LH, 32,
329 P1SL, 32,
330 P1SH, 32,
331 P1EL, 32,
332 P1EH, 32,
333 P1LL, 32,
334 P1LH, 32,
335 }
336
337 /* fixup 32bit pci io window */
338 CreateDWordField (CRES,\_SB.PCI0.PW32._MIN, PS32)
339 CreateDWordField (CRES,\_SB.PCI0.PW32._MAX, PE32)
340 CreateDWordField (CRES,\_SB.PCI0.PW32._LEN, PL32)
341 Store (P0SL, PS32)
342 Store (P0EL, PE32)
343 Store (P0LL, PL32)
344
345 If (LAnd(LEqual(P1SL, 0x00), LEqual(P1SH, 0x00))) {
346 Return (CRES)
347 } Else {
348 /* fixup 64bit pci io window */
349 CreateQWordField (CR64,\_SB.PCI0.PW64._MIN, PS64)
350 CreateQWordField (CR64,\_SB.PCI0.PW64._MAX, PE64)
351 CreateQWordField (CR64,\_SB.PCI0.PW64._LEN, PL64)
352 Store (P1S, PS64)
353 Store (P1E, PE64)
354 Store (P1L, PL64)
355 /* add window and return result */
356 ConcatenateResTemplate (CRES, CR64, Local0)
357 Return (Local0)
358 }
359 }
360 }
361 }
362
Gerd Hoffmann7464aea2012-11-28 10:17:41 +0100363#include "acpi-dsdt-hpet.dsl"
364
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100365 Scope(\_SB.PCI0) {
366 Device (VGA) {
367 Name (_ADR, 0x00020000)
368 Method (_S1D, 0, NotSerialized)
369 {
370 Return (0x00)
371 }
372 Method (_S2D, 0, NotSerialized)
373 {
374 Return (0x00)
375 }
376 Method (_S3D, 0, NotSerialized)
377 {
378 Return (0x00)
379 }
380 }
381
382
383 /* PCI D31:f0 LPC ISA bridge */
384 Device (LPC) {
385 /* PCI D31:f0 */
386 Name (_ADR, 0x001f0000)
387
388 /* ICH9 PCI to ISA irq remapping */
389 OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
390 Field (PIRQ, ByteAcc, NoLock, Preserve)
391 {
392 PRQA, 8,
393 PRQB, 8,
394 PRQC, 8,
395 PRQD, 8,
396
397 Offset (0x08),
398 PRQE, 8,
399 PRQF, 8,
400 PRQG, 8,
401 PRQH, 8
402 }
403
404 OperationRegion (LPCD, PCI_Config, 0x80, 0x2)
405 Field (LPCD, AnyAcc, NoLock, Preserve)
406 {
407 COMA, 3,
408 , 1,
409 COMB, 3,
410
411 Offset(0x01),
412 LPTD, 2,
413 , 2,
414 FDCD, 2
415 }
416 OperationRegion (LPCE, PCI_Config, 0x82, 0x2)
417 Field (LPCE, AnyAcc, NoLock, Preserve)
418 {
419 CAEN, 1,
420 CBEN, 1,
421 LPEN, 1,
422 FDEN, 1
423 }
424
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100425 /* Real-time clock */
426 Device (RTC)
427 {
428 Name (_HID, EisaId ("PNP0B00"))
429 Name (_CRS, ResourceTemplate ()
430 {
431 IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
432 IRQNoFlags () {8}
433 IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
434 })
435 }
436
437 /* Keyboard seems to be important for WinXP install */
438 Device (KBD)
439 {
440 Name (_HID, EisaId ("PNP0303"))
441 Method (_STA, 0, NotSerialized)
442 {
443 Return (0x0f)
444 }
445
446 Method (_CRS, 0, NotSerialized)
447 {
448 Name (TMP, ResourceTemplate ()
449 {
450 IO (Decode16,
451 0x0060, // Address Range Minimum
452 0x0060, // Address Range Maximum
453 0x01, // Address Alignment
454 0x01, // Address Length
455 )
456 IO (Decode16,
457 0x0064, // Address Range Minimum
458 0x0064, // Address Range Maximum
459 0x01, // Address Alignment
460 0x01, // Address Length
461 )
462 IRQNoFlags ()
463 {1}
464 })
465 Return (TMP)
466 }
467 }
468
469 /* PS/2 mouse */
470 Device (MOU)
471 {
472 Name (_HID, EisaId ("PNP0F13"))
473 Method (_STA, 0, NotSerialized)
474 {
475 Return (0x0f)
476 }
477
478 Method (_CRS, 0, NotSerialized)
479 {
480 Name (TMP, ResourceTemplate ()
481 {
482 IRQNoFlags () {12}
483 })
484 Return (TMP)
485 }
486 }
487
488 /* PS/2 floppy controller */
489 Device (FDC0)
490 {
491 Name (_HID, EisaId ("PNP0700"))
492 Method (_STA, 0, NotSerialized)
493 {
494 Store (\_SB.PCI0.LPC.FDEN, Local0)
495 If (LEqual (Local0, 0))
496 {
497 Return (0x00)
498 }
499 Else
500 {
501 Return (0x0F)
502 }
503 }
504 Method (_CRS, 0, NotSerialized)
505 {
506 Name (BUF0, ResourceTemplate ()
507 {
508 IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
509 IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
510 IRQNoFlags () {6}
511 DMA (Compatibility, NotBusMaster, Transfer8) {2}
512 })
513 Return (BUF0)
514 }
515 }
516
517 /* Parallel port */
518 Device (LPT)
519 {
520 Name (_HID, EisaId ("PNP0400"))
521 Method (_STA, 0, NotSerialized)
522 {
523 Store (\_SB.PCI0.LPC.LPEN, Local0)
524 If (LEqual (Local0, 0))
525 {
526 Return (0x00)
527 }
528 Else
529 {
530 Return (0x0F)
531 }
532 }
533 Method (_CRS, 0, NotSerialized)
534 {
535 Name (BUF0, ResourceTemplate ()
536 {
537 IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
538 IRQNoFlags () {7}
539 })
540 Return (BUF0)
541 }
542 }
543
544 /* Serial Ports */
545 Device (COM1)
546 {
547 Name (_HID, EisaId ("PNP0501"))
548 Name (_UID, 0x01)
549 Method (_STA, 0, NotSerialized)
550 {
551 Store (\_SB.PCI0.LPC.CAEN, Local0)
552 If (LEqual (Local0, 0))
553 {
554 Return (0x00)
555 }
556 Else
557 {
558 Return (0x0F)
559 }
560 }
561 Method (_CRS, 0, NotSerialized)
562 {
563 Name (BUF0, ResourceTemplate ()
564 {
565 IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
566 IRQNoFlags () {4}
567 })
568 Return (BUF0)
569 }
570 }
571
572 Device (COM2)
573 {
574 Name (_HID, EisaId ("PNP0501"))
575 Name (_UID, 0x02)
576 Method (_STA, 0, NotSerialized)
577 {
578 Store (\_SB.PCI0.LPC.CBEN, Local0)
579 If (LEqual (Local0, 0))
580 {
581 Return (0x00)
582 }
583 Else
584 {
585 Return (0x0F)
586 }
587 }
588 Method (_CRS, 0, NotSerialized)
589 {
590 Name (BUF0, ResourceTemplate ()
591 {
592 IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
593 IRQNoFlags () {3}
594 })
595 Return (BUF0)
596 }
597 }
598 }
599 }
600
601 /* PCI IRQs */
602 Scope(\_SB) {
603#define define_link(link, uid, reg) \
604 Device(link){ \
605 Name(_HID, EISAID("PNP0C0F")) \
606 Name(_UID, uid) \
607 Name(_PRS, ResourceTemplate(){ \
608 Interrupt (, Level, ActiveHigh, \
609 Shared) \
610 { 5, 10, 11 } \
611 }) \
612 Method (_STA, 0, NotSerialized) \
613 { \
614 Store (0x0B, Local0) \
615 If (And (0x80, reg, Local1)) \
616 { \
617 Store (0x09, Local0) \
618 } \
619 Return (Local0) \
620 } \
621 Method (_DIS, 0, NotSerialized) \
622 { \
623 Or (reg, 0x80, reg) \
624 } \
625 Method (_CRS, 0, NotSerialized) \
626 { \
627 Name (PRR0, ResourceTemplate () \
628 { \
629 Interrupt (, Level, ActiveHigh, \
630 Shared) \
631 {1} \
632 }) \
633 CreateDWordField (PRR0, 0x05, TMP) \
634 And (reg, 0x0F, Local0) \
635 Store (Local0, TMP) \
636 Return (PRR0) \
637 } \
638 Method (_SRS, 1, NotSerialized) \
639 { \
640 CreateDWordField (Arg0, 0x05, TMP) \
641 Store (TMP, reg) \
642 } \
643 }
644
645 define_link(LNKA, 0, \_SB.PCI0.LPC.PRQA)
646 define_link(LNKB, 1, \_SB.PCI0.LPC.PRQB)
647 define_link(LNKC, 2, \_SB.PCI0.LPC.PRQC)
648 define_link(LNKD, 3, \_SB.PCI0.LPC.PRQD)
649 define_link(LNKE, 4, \_SB.PCI0.LPC.PRQE)
650 define_link(LNKF, 5, \_SB.PCI0.LPC.PRQF)
651 define_link(LNKG, 6, \_SB.PCI0.LPC.PRQG)
652 define_link(LNKH, 7, \_SB.PCI0.LPC.PRQH)
Jan Kiszka2114f502012-11-28 10:17:37 +0100653
654#define define_gsi_link(link, uid, gsi) \
655 Device(link){ \
656 Name(_HID, EISAID("PNP0C0F")) \
657 Name(_UID, uid) \
658 Name(_PRS, ResourceTemplate() { \
659 Interrupt (, Level, ActiveHigh, \
660 Shared) \
661 { gsi } \
662 }) \
663 Method (_CRS, 0, NotSerialized) \
664 { \
665 Return (ResourceTemplate () { \
666 Interrupt (, Level, ActiveHigh, \
667 Shared) \
668 { gsi } \
669 }) \
670 } \
671 Method (_SRS, 1, NotSerialized) { } \
672 } \
673
674 define_gsi_link(GSIA, 0, 0x10)
675 define_gsi_link(GSIB, 0, 0x11)
676 define_gsi_link(GSIC, 0, 0x12)
677 define_gsi_link(GSID, 0, 0x13)
678 define_gsi_link(GSIE, 0, 0x14)
679 define_gsi_link(GSIF, 0, 0x15)
680 define_gsi_link(GSIG, 0, 0x16)
681 define_gsi_link(GSIH, 0, 0x17)
Isaku Yamahataecbe3fd2012-11-28 10:17:36 +0100682 }
683
684 /* CPU hotplug */
685 Scope(\_SB) {
686 /* Objects filled in by run-time generated SSDT */
687 External(NTFY, MethodObj)
688 External(CPON, PkgObj)
689
690 /* Methods called by run-time generated SSDT Processor objects */
691 Method (CPMA, 1, NotSerialized) {
692 // _MAT method - create an madt apic buffer
693 // Local0 = CPON flag for this cpu
694 Store(DerefOf(Index(CPON, Arg0)), Local0)
695 // Local1 = Buffer (in madt apic form) to return
696 Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
697 // Update the processor id, lapic id, and enable/disable status
698 Store(Arg0, Index(Local1, 2))
699 Store(Arg0, Index(Local1, 3))
700 Store(Local0, Index(Local1, 4))
701 Return (Local1)
702 }
703 Method (CPST, 1, NotSerialized) {
704 // _STA method - return ON status of cpu
705 // Local0 = CPON flag for this cpu
706 Store(DerefOf(Index(CPON, Arg0)), Local0)
707 If (Local0) { Return(0xF) } Else { Return(0x0) }
708 }
709 Method (CPEJ, 2, NotSerialized) {
710 // _EJ0 method - eject callback
711 Sleep(200)
712 }
713
714 /* CPU hotplug notify method */
715 OperationRegion(PRST, SystemIO, 0xaf00, 32)
716 Field (PRST, ByteAcc, NoLock, Preserve)
717 {
718 PRS, 256
719 }
720 Method(PRSC, 0) {
721 // Local5 = active cpu bitmap
722 Store (PRS, Local5)
723 // Local2 = last read byte from bitmap
724 Store (Zero, Local2)
725 // Local0 = cpuid iterator
726 Store (Zero, Local0)
727 While (LLess(Local0, SizeOf(CPON))) {
728 // Local1 = CPON flag for this cpu
729 Store(DerefOf(Index(CPON, Local0)), Local1)
730 If (And(Local0, 0x07)) {
731 // Shift down previously read bitmap byte
732 ShiftRight(Local2, 1, Local2)
733 } Else {
734 // Read next byte from cpu bitmap
735 Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
736 }
737 // Local3 = active state for this cpu
738 Store(And(Local2, 1), Local3)
739
740 If (LNotEqual(Local1, Local3)) {
741 // State change - update CPON with new state
742 Store(Local3, Index(CPON, Local0))
743 // Do CPU notify
744 If (LEqual(Local3, 1)) {
745 NTFY(Local0, 1)
746 } Else {
747 NTFY(Local0, 3)
748 }
749 }
750 Increment(Local0)
751 }
752 Return(One)
753 }
754 }
755
756 Scope (\_GPE)
757 {
758 Name(_HID, "ACPI0006")
759
760 Method(_L00) {
761 Return(0x01)
762 }
763 Method(_L01) {
764 // CPU hotplug event
765 Return(\_SB.PRSC())
766 }
767 Method(_L02) {
768 Return(0x01)
769 }
770 Method(_L03) {
771 Return(0x01)
772 }
773 Method(_L04) {
774 Return(0x01)
775 }
776 Method(_L05) {
777 Return(0x01)
778 }
779 Method(_L06) {
780 Return(0x01)
781 }
782 Method(_L07) {
783 Return(0x01)
784 }
785 Method(_L08) {
786 Return(0x01)
787 }
788 Method(_L09) {
789 Return(0x01)
790 }
791 Method(_L0A) {
792 Return(0x01)
793 }
794 Method(_L0B) {
795 Return(0x01)
796 }
797 Method(_L0C) {
798 Return(0x01)
799 }
800 Method(_L0D) {
801 Return(0x01)
802 }
803 Method(_L0E) {
804 Return(0x01)
805 }
806 Method(_L0F) {
807 Return(0x01)
808 }
809 }
810}