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Kevin O'Connor1f2c3072009-05-06 23:35:59 -04001// QEMU Cirrus CLGD 54xx VGABIOS Extension.
2//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (c) 2004 Makoto Suzuki (suzu)
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connor6f775082011-12-31 18:39:59 -05008#include "clext.h" // clext_init
9#include "vgabios.h" // VBE_VENDOR_STRING
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040010#include "biosvar.h" // GET_GLOBAL
11#include "util.h" // dprintf
Kevin O'Connor3c065362011-12-27 21:34:33 -050012#include "bregs.h" // struct bregs
Kevin O'Connored68e5b2011-12-31 04:15:12 -050013#include "stdvga.h" // VGAREG_SEQU_ADDRESS
Kevin O'Connor97cc3542012-01-14 16:59:21 -050014#include "pci.h" // pci_config_readl
15#include "pci_regs.h" // PCI_BASE_ADDRESS_0
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040016
Kevin O'Connore48a5372011-12-20 23:56:14 -050017
18/****************************************************************
19 * tables
20 ****************************************************************/
21
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040022/* VGA */
23static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
24static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
25static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
26
27/* extensions */
28static u16 cgraph_svgacolor[] VAR16 = {
29 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
30 0x0009,0x000a,0x000b,
31 0xffff
32};
33/* 640x480x8 */
34static u16 cseq_640x480x8[] VAR16 = {
35 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
36 0x580b,0x580c,0x580d,0x580e,
37 0x0412,0x0013,0x2017,
38 0x331b,0x331c,0x331d,0x331e,
39 0xffff
40};
41static u16 ccrtc_640x480x8[] VAR16 = {
42 0x2c11,
43 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
44 0x4009,0x000c,0x000d,
45 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
46 0x001a,0x221b,0x001d,
47 0xffff
48};
49/* 640x480x16 */
50static u16 cseq_640x480x16[] VAR16 = {
51 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
52 0x580b,0x580c,0x580d,0x580e,
53 0x0412,0x0013,0x2017,
54 0x331b,0x331c,0x331d,0x331e,
55 0xffff
56};
57static u16 ccrtc_640x480x16[] VAR16 = {
58 0x2c11,
59 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
60 0x4009,0x000c,0x000d,
61 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
62 0x001a,0x221b,0x001d,
63 0xffff
64};
65/* 640x480x24 */
66static u16 cseq_640x480x24[] VAR16 = {
67 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
68 0x580b,0x580c,0x580d,0x580e,
69 0x0412,0x0013,0x2017,
70 0x331b,0x331c,0x331d,0x331e,
71 0xffff
72};
73static u16 ccrtc_640x480x24[] VAR16 = {
74 0x2c11,
75 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
76 0x4009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -050077 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
78 0x001a,0x221b,0x001d,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040079 0xffff
80};
81/* 800x600x8 */
82static u16 cseq_800x600x8[] VAR16 = {
83 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
84 0x230b,0x230c,0x230d,0x230e,
85 0x0412,0x0013,0x2017,
86 0x141b,0x141c,0x141d,0x141e,
87 0xffff
88};
89static u16 ccrtc_800x600x8[] VAR16 = {
90 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
91 0x6009,0x000c,0x000d,
92 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
93 0x001a,0x221b,0x001d,
94 0xffff
95};
96/* 800x600x16 */
97static u16 cseq_800x600x16[] VAR16 = {
98 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
99 0x230b,0x230c,0x230d,0x230e,
100 0x0412,0x0013,0x2017,
101 0x141b,0x141c,0x141d,0x141e,
102 0xffff
103};
104static u16 ccrtc_800x600x16[] VAR16 = {
105 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
106 0x6009,0x000c,0x000d,
107 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
108 0x001a,0x221b,0x001d,
109 0xffff
110};
111/* 800x600x24 */
112static u16 cseq_800x600x24[] VAR16 = {
113 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
114 0x230b,0x230c,0x230d,0x230e,
115 0x0412,0x0013,0x2017,
116 0x141b,0x141c,0x141d,0x141e,
117 0xffff
118};
119static u16 ccrtc_800x600x24[] VAR16 = {
120 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
121 0x6009,0x000c,0x000d,
122 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
123 0x001a,0x321b,0x001d,
124 0xffff
125};
126/* 1024x768x8 */
127static u16 cseq_1024x768x8[] VAR16 = {
128 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
129 0x760b,0x760c,0x760d,0x760e,
130 0x0412,0x0013,0x2017,
131 0x341b,0x341c,0x341d,0x341e,
132 0xffff
133};
134static u16 ccrtc_1024x768x8[] VAR16 = {
135 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
136 0x6009,0x000c,0x000d,
137 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
138 0x001a,0x221b,0x001d,
139 0xffff
140};
141/* 1024x768x16 */
142static u16 cseq_1024x768x16[] VAR16 = {
143 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
144 0x760b,0x760c,0x760d,0x760e,
145 0x0412,0x0013,0x2017,
146 0x341b,0x341c,0x341d,0x341e,
147 0xffff
148};
149static u16 ccrtc_1024x768x16[] VAR16 = {
150 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
151 0x6009,0x000c,0x000d,
152 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
153 0x001a,0x321b,0x001d,
154 0xffff
155};
156/* 1024x768x24 */
157static u16 cseq_1024x768x24[] VAR16 = {
158 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
159 0x760b,0x760c,0x760d,0x760e,
160 0x0412,0x0013,0x2017,
161 0x341b,0x341c,0x341d,0x341e,
162 0xffff
163};
164static u16 ccrtc_1024x768x24[] VAR16 = {
165 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
166 0x6009,0x000c,0x000d,
167 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
168 0x001a,0x321b,0x001d,
169 0xffff
170};
171/* 1280x1024x8 */
172static u16 cseq_1280x1024x8[] VAR16 = {
173 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
174 0x760b,0x760c,0x760d,0x760e,
175 0x0412,0x0013,0x2017,
176 0x341b,0x341c,0x341d,0x341e,
177 0xffff
178};
179static u16 ccrtc_1280x1024x8[] VAR16 = {
180 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
181 0x6009,0x000c,0x000d,
182 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
183 0x001a,0x221b,0x001d,
184 0xffff
185};
186/* 1280x1024x16 */
187static u16 cseq_1280x1024x16[] VAR16 = {
188 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
189 0x760b,0x760c,0x760d,0x760e,
190 0x0412,0x0013,0x2017,
191 0x341b,0x341c,0x341d,0x341e,
192 0xffff
193};
194static u16 ccrtc_1280x1024x16[] VAR16 = {
195 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
196 0x6009,0x000c,0x000d,
197 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
198 0x001a,0x321b,0x001d,
199 0xffff
200};
201
202/* 1600x1200x8 */
203static u16 cseq_1600x1200x8[] VAR16 = {
204 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
205 0x760b,0x760c,0x760d,0x760e,
206 0x0412,0x0013,0x2017,
207 0x341b,0x341c,0x341d,0x341e,
208 0xffff
209};
210static u16 ccrtc_1600x1200x8[] VAR16 = {
211 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
212 0x6009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500213 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400214 0x001a,0x221b,0x001d,
215 0xffff
216};
217
Kevin O'Connor643290f2012-01-13 22:08:52 -0500218struct cirrus_mode_s {
219 u16 mode;
220 struct vgamode_s info;
221
222 u16 hidden_dac; /* 0x3c6 */
223 u16 *seq; /* 0x3c4 */
224 u16 *graph; /* 0x3ce */
225 u16 *crtc; /* 0x3d4 */
226};
227
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400228static struct cirrus_mode_s cirrus_modes[] VAR16 = {
Kevin O'Connor03776022012-01-21 11:00:11 -0500229 {0x5f,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500230 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
Kevin O'Connor03776022012-01-21 11:00:11 -0500231 {0x64,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500232 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connor03776022012-01-21 11:00:11 -0500233 {0x66,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500234 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connor03776022012-01-21 11:00:11 -0500235 {0x71,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500236 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400237
Kevin O'Connor03776022012-01-21 11:00:11 -0500238 {0x5c,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500239 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
Kevin O'Connor03776022012-01-21 11:00:11 -0500240 {0x65,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500241 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connor03776022012-01-21 11:00:11 -0500242 {0x67,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500243 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400244
Kevin O'Connor03776022012-01-21 11:00:11 -0500245 {0x60,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500246 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
Kevin O'Connor03776022012-01-21 11:00:11 -0500247 {0x74,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500248 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connor03776022012-01-21 11:00:11 -0500249 {0x68,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500250 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400251
Kevin O'Connor03776022012-01-21 11:00:11 -0500252 {0x78,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500253 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
Kevin O'Connor03776022012-01-21 11:00:11 -0500254 {0x79,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500255 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400256
Kevin O'Connor03776022012-01-21 11:00:11 -0500257 {0x6d,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500258 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
Kevin O'Connor03776022012-01-21 11:00:11 -0500259 {0x69,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500260 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connor03776022012-01-21 11:00:11 -0500261 {0x75,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500262 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400263
Kevin O'Connor03776022012-01-21 11:00:11 -0500264 {0x7b,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500265 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400266};
267
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500268static struct cirrus_mode_s mode_switchback VAR16 =
Kevin O'Connor643290f2012-01-13 22:08:52 -0500269 {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
270
271static struct {
272 u16 vesamode, mode;
273} cirrus_vesa_modelist[] VAR16 = {
274 // 640x480x8
275 { 0x101, 0x5f },
276 // 640x480x15
277 { 0x110, 0x66 },
278 // 640x480x16
279 { 0x111, 0x64 },
280 // 640x480x24
281 { 0x112, 0x71 },
282 // 800x600x8
283 { 0x103, 0x5c },
284 // 800x600x15
285 { 0x113, 0x67 },
286 // 800x600x16
287 { 0x114, 0x65 },
288 // 800x600x24
289 { 0x115, 0x78 },
290 // 1024x768x8
291 { 0x105, 0x60 },
292 // 1024x768x15
293 { 0x116, 0x68 },
294 // 1024x768x16
295 { 0x117, 0x74 },
296 // 1024x768x24
297 { 0x118, 0x79 },
298 // 1280x1024x8
299 { 0x107, 0x6d },
300 // 1280x1024x15
301 { 0x119, 0x69 },
302 // 1280x1024x16
303 { 0x11a, 0x75 },
304};
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500305
Kevin O'Connore48a5372011-12-20 23:56:14 -0500306
307/****************************************************************
308 * helper functions
309 ****************************************************************/
310
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500311int
312is_cirrus_mode(struct vgamode_s *vmode_g)
313{
314 return (vmode_g >= &cirrus_modes[0].info
315 && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
316}
317
Kevin O'Connor59f75d42012-01-27 20:52:29 -0500318void
319clext_list_modes(u16 seg, u16 *dest, u16 *last)
320{
321 int i;
322 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
323 SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
324 dest++;
325 }
326 stdvga_list_modes(seg, dest, last);
327}
328
Kevin O'Connor643290f2012-01-13 22:08:52 -0500329static u16
330cirrus_vesamode_to_mode(u16 vesamode)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400331{
Kevin O'Connor643290f2012-01-13 22:08:52 -0500332 int i;
333 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
334 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
335 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
336 return 0;
337}
338
339static struct cirrus_mode_s *
340cirrus_get_modeentry(int mode)
341{
342 int transmode = cirrus_vesamode_to_mode(mode);
343 if (transmode)
344 mode = transmode;
Kevin O'Connor4f792742009-05-16 14:55:01 -0400345 struct cirrus_mode_s *table_g = cirrus_modes;
346 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
347 u16 tmode = GET_GLOBAL(table_g->mode);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400348 if (tmode == mode)
Kevin O'Connor4f792742009-05-16 14:55:01 -0400349 return table_g;
350 table_g++;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400351 }
352 return NULL;
353}
354
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500355struct vgamode_s *
356clext_find_mode(int mode)
357{
358 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
359 if (table_g)
360 return &table_g->info;
361 return stdvga_find_mode(mode);
362}
363
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400364static void
365cirrus_switch_mode_setregs(u16 *data, u16 port)
366{
367 for (;;) {
368 u16 val = GET_GLOBAL(*data);
369 if (val == 0xffff)
370 return;
371 outw(val, port);
372 data++;
373 }
374}
375
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400376static void
377cirrus_switch_mode(struct cirrus_mode_s *table)
378{
379 // Unlock cirrus special
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500380 stdvga_sequ_write(0x06, 0x12);
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400381 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
382 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
Kevin O'Connorc990f272011-12-31 16:00:54 -0500383 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400384
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500385 stdvga_pelmask_write(0x00);
386 stdvga_pelmask_read();
387 stdvga_pelmask_read();
388 stdvga_pelmask_read();
389 stdvga_pelmask_read();
390 stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
391 stdvga_pelmask_write(0xff);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400392
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500393 u8 memmodel = GET_GLOBAL(table->info.memmodel);
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500394 u8 on = 0;
Kevin O'Connorb451f182012-01-02 02:23:17 -0500395 if (memmodel == MM_PLANAR)
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500396 on = 0x41;
Kevin O'Connorb451f182012-01-02 02:23:17 -0500397 else if (memmodel != MM_TEXT)
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500398 on = 0x01;
399 stdvga_attr_mask(0x10, 0x01, on);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400400}
401
Kevin O'Connore48a5372011-12-20 23:56:14 -0500402static u8
403cirrus_get_memsize(void)
404{
405 // get DRAM band width
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500406 u8 v = stdvga_sequ_read(0x0f);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500407 u8 x = (v >> 3) & 0x03;
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500408 if (x == 0x03 && v & 0x80)
409 // 4MB
410 return 0x40;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500411 return 0x04 << x;
412}
413
Kevin O'Connor9961f992012-01-21 11:53:44 -0500414int
415clext_get_window(struct vgamode_s *vmode_g, int window)
416{
417 return stdvga_grdc_read(window + 9);
418}
419
420int
421clext_set_window(struct vgamode_s *vmode_g, int window, int val)
422{
423 if (val >= 0x100)
424 return -1;
425 stdvga_grdc_write(window + 9, val);
426 return 0;
427}
428
Kevin O'Connor3876b532012-01-24 00:07:44 -0500429int
430clext_get_linelength(struct vgamode_s *vmode_g)
431{
432 u16 crtc_addr = stdvga_get_crtc();
433 u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
434 u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
435 return (((reg1b & 0x10) << 4) + reg13) * stdvga_bpp_factor(vmode_g) * 2;
436}
437
438int
439clext_set_linelength(struct vgamode_s *vmode_g, int val)
440{
441 u16 crtc_addr = stdvga_get_crtc();
442 int factor = stdvga_bpp_factor(vmode_g) * 2;
443 int new_line_offset = DIV_ROUND_UP(val, factor);
444 stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
445 stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
446 return 0;
447}
448
Kevin O'Connord61fc532012-01-27 20:37:45 -0500449int
450clext_get_displaystart(struct vgamode_s *vmode_g)
451{
452 u16 crtc_addr = stdvga_get_crtc();
453 u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
454 u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
455 u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
456 u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
457 int val = (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
458 | ((b4 & 0x80) << 12));
459 return val * stdvga_bpp_factor(vmode_g);
460}
461
462int
463clext_set_displaystart(struct vgamode_s *vmode_g, int val)
464{
465 u16 crtc_addr = stdvga_get_crtc();
466 val /= stdvga_bpp_factor(vmode_g);
467 stdvga_crtc_write(crtc_addr, 0x0d, val);
468 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
469 stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (val & 0x0800) >> 4);
470 stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
471 , ((val & 0x0100) >> 8) | ((val & 0x0600) >> 7));
472 return 0;
473}
474
Kevin O'Connore48a5372011-12-20 23:56:14 -0500475static void
476cirrus_enable_16k_granularity(void)
477{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500478 stdvga_grdc_mask(0x0b, 0x00, 0x20);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500479}
480
481static void
482cirrus_clear_vram(u16 param)
483{
484 cirrus_enable_16k_granularity();
Kevin O'Connor5e1694c2012-01-21 10:43:30 -0500485 u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500486 u8 i;
487 for (i=0; i<count; i++) {
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500488 stdvga_grdc_write(0x09, i);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500489 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
490 }
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500491 stdvga_grdc_write(0x09, 0x00);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500492}
493
494int
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500495clext_set_mode(struct vgamode_s *vmode_g, int flags)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400496{
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500497 if (!is_cirrus_mode(vmode_g)) {
498 cirrus_switch_mode(&mode_switchback);
499 dprintf(1, "cirrus mode switch regular\n");
500 return stdvga_set_mode(vmode_g, flags);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400501 }
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500502 struct cirrus_mode_s *table_g = container_of(
503 vmode_g, struct cirrus_mode_s, info);
504 cirrus_switch_mode(table_g);
505 if (!(flags & MF_LINEARFB))
506 cirrus_enable_16k_granularity();
507 if (!(flags & MF_NOCLEARMEM))
508 cirrus_clear_vram(0);
509 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400510}
511
512static int
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500513cirrus_check(void)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400514{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500515 stdvga_sequ_write(0x06, 0x92);
516 return stdvga_sequ_read(0x06) == 0x12;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400517}
518
Kevin O'Connore48a5372011-12-20 23:56:14 -0500519
520/****************************************************************
521 * extbios
522 ****************************************************************/
523
524static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500525clext_101280(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500526{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500527 u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500528 if (v == 0xa0)
529 // 5430
530 regs->ax = 0x0032;
531 else if (v == 0xb8)
532 // 5446
533 regs->ax = 0x0039;
534 else
535 regs->ax = 0x00ff;
536 regs->bx = 0x00;
537 return;
538}
539
540static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500541clext_101281(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500542{
543 // XXX
544 regs->ax = 0x0100;
545}
546
547static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500548clext_101282(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500549{
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500550 regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500551 regs->ah = 0xAF;
552}
553
554static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500555clext_101285(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500556{
Kevin O'Connor5e1694c2012-01-21 10:43:30 -0500557 regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500558}
559
560static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500561clext_10129a(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500562{
563 regs->ax = 0x4060;
564 regs->cx = 0x1132;
565}
566
567extern void a0h_callback(void);
568ASM16(
569 // fatal: not implemented yet
570 "a0h_callback:"
571 "cli\n"
572 "hlt\n"
573 "retf");
574
575static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500576clext_1012a0(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500577{
578 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
579 regs->ah = (table_g ? 1 : 0);
580 regs->si = 0xffff;
581 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
582}
583
584static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500585clext_1012a1(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500586{
587 regs->bx = 0x0e00; // IBM 8512/8513, color
588}
589
590static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500591clext_1012a2(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500592{
593 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
594}
595
596static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500597clext_1012ae(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500598{
599 regs->al = 0x01; // High Refresh 75Hz
600}
601
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500602static void
603clext_1012XX(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500604{
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500605 debug_stub(regs);
606}
607
608void
609clext_1012(struct bregs *regs)
610{
Kevin O'Connore48a5372011-12-20 23:56:14 -0500611 switch (regs->bl) {
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500612 case 0x80: clext_101280(regs); break;
613 case 0x81: clext_101281(regs); break;
614 case 0x82: clext_101282(regs); break;
615 case 0x85: clext_101285(regs); break;
616 case 0x9a: clext_10129a(regs); break;
617 case 0xa0: clext_1012a0(regs); break;
618 case 0xa1: clext_1012a1(regs); break;
619 case 0xa2: clext_1012a2(regs); break;
620 case 0xae: clext_1012ae(regs); break;
621 default: clext_1012XX(regs); break;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500622 }
623}
624
625
626/****************************************************************
Kevin O'Connore48a5372011-12-20 23:56:14 -0500627 * init
628 ****************************************************************/
629
Kevin O'Connor161d2012011-12-31 19:42:21 -0500630int
Kevin O'Connor6f775082011-12-31 18:39:59 -0500631clext_init(void)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400632{
Kevin O'Connor161d2012011-12-31 19:42:21 -0500633 int ret = stdvga_init();
634 if (ret)
635 return ret;
636
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400637 dprintf(1, "cirrus init\n");
638 if (! cirrus_check())
Kevin O'Connor161d2012011-12-31 19:42:21 -0500639 return -1;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400640 dprintf(1, "cirrus init 2\n");
641
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500642 u32 lfb_addr = 0;
Kevin O'Connor8cf8f8e2012-01-16 19:05:27 -0500643 int bdf = GET_GLOBAL(VgaBDF);
644 if (CONFIG_VGA_PCI && bdf >= 0)
645 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500646 & PCI_BASE_ADDRESS_MEM_MASK);
647 SET_VGA(VBE_framebuffer, lfb_addr);
Kevin O'Connor643290f2012-01-13 22:08:52 -0500648 u16 totalmem = cirrus_get_memsize();
649 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
650 SET_VGA(VBE_win_granularity, 16);
651
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400652 // memory setup
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500653 stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400654 // set vga mode
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500655 stdvga_sequ_write(0x07, 0x00);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400656 // reset bitblt
Kevin O'Connoradd3bec2012-01-14 22:18:02 -0500657 stdvga_grdc_write(0x31, 0x04);
658 stdvga_grdc_write(0x31, 0x00);
Kevin O'Connor161d2012011-12-31 19:42:21 -0500659
660 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400661}