blob: 61540766464385982e443e8e2af70646409696a9 [file] [log] [blame]
Kevin O'Connorc0c7df62009-05-17 18:11:33 -04001// VGA io port access
2//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2001-2008 the LGPL VGABios developers Team
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
8#include "ioport.h" // outb
Kevin O'Connorc0c7df62009-05-17 18:11:33 -04009#include "farptr.h" // SET_FARVAR
Kevin O'Connora0ecb052009-05-18 23:34:00 -040010#include "biosvar.h" // GET_BDA
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040011#include "vgatables.h" // VGAREG_*
12
Kevin O'Connor414d0732009-05-31 22:42:04 -040013// TODO
14// * replace direct in/out calls with wrapper functions
15
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040016
17/****************************************************************
18 * Attribute control
19 ****************************************************************/
20
21void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050022vgahw_screen_disable(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -040023{
24 inb(VGAREG_ACTL_RESET);
25 outb(0x00, VGAREG_ACTL_ADDRESS);
26}
27
28void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050029vgahw_screen_enable(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -040030{
31 inb(VGAREG_ACTL_RESET);
32 outb(0x20, VGAREG_ACTL_ADDRESS);
33}
34
35void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040036vgahw_set_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040037{
38 inb(VGAREG_ACTL_RESET);
39 outb(0x00, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040040 u8 v1 = color & 0x0f;
41 if (v1 & 0x08)
42 v1 += 0x08;
43 outb(v1, VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040044
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040045 u8 v2 = color & 0x10;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040046 int i;
47 for (i = 1; i < 4; i++) {
48 outb(i, VGAREG_ACTL_ADDRESS);
49
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040050 u8 cur = inb(VGAREG_ACTL_READ_DATA);
51 cur &= 0xef;
52 cur |= v2;
53 outb(cur, VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040054 }
55 outb(0x20, VGAREG_ACTL_ADDRESS);
56}
57
58void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040059vgahw_set_overscan_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040060{
61 inb(VGAREG_ACTL_RESET);
62 outb(0x11, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040063 outb(color, VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040064 outb(0x20, VGAREG_ACTL_ADDRESS);
65}
66
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040067u8
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050068vgahw_get_overscan_border_color(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040069{
70 inb(VGAREG_ACTL_RESET);
71 outb(0x11, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040072 u8 v = inb(VGAREG_ACTL_READ_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040073 inb(VGAREG_ACTL_RESET);
74 outb(0x20, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040075 return v;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040076}
77
78void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040079vgahw_set_palette(u8 palid)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040080{
81 inb(VGAREG_ACTL_RESET);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040082 palid &= 0x01;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040083 int i;
84 for (i = 1; i < 4; i++) {
85 outb(i, VGAREG_ACTL_ADDRESS);
86
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040087 u8 v = inb(VGAREG_ACTL_READ_DATA);
88 v &= 0xfe;
89 v |= palid;
90 outb(v, VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040091 }
92 outb(0x20, VGAREG_ACTL_ADDRESS);
93}
94
95void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040096vgahw_set_single_palette_reg(u8 reg, u8 val)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040097{
98 inb(VGAREG_ACTL_RESET);
99 outb(reg, VGAREG_ACTL_ADDRESS);
100 outb(val, VGAREG_ACTL_WRITE_DATA);
101 outb(0x20, VGAREG_ACTL_ADDRESS);
102}
103
104u8
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400105vgahw_get_single_palette_reg(u8 reg)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400106{
107 inb(VGAREG_ACTL_RESET);
108 outb(reg, VGAREG_ACTL_ADDRESS);
109 u8 v = inb(VGAREG_ACTL_READ_DATA);
110 inb(VGAREG_ACTL_RESET);
111 outb(0x20, VGAREG_ACTL_ADDRESS);
112 return v;
113}
114
115void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400116vgahw_set_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400117{
118 inb(VGAREG_ACTL_RESET);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400119 int i;
120 for (i = 0; i < 0x10; i++) {
121 outb(i, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400122 u8 val = GET_FARVAR(seg, *data_far);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400123 outb(val, VGAREG_ACTL_WRITE_DATA);
124 data_far++;
125 }
126 outb(0x11, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400127 outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400128 outb(0x20, VGAREG_ACTL_ADDRESS);
129}
130
131void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400132vgahw_get_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400133{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400134 int i;
135 for (i = 0; i < 0x10; i++) {
136 inb(VGAREG_ACTL_RESET);
137 outb(i, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400138 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400139 data_far++;
140 }
141 inb(VGAREG_ACTL_RESET);
142 outb(0x11, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400143 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400144 inb(VGAREG_ACTL_RESET);
145 outb(0x20, VGAREG_ACTL_ADDRESS);
146}
147
148void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400149vgahw_toggle_intensity(u8 flag)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400150{
151 inb(VGAREG_ACTL_RESET);
152 outb(0x10, VGAREG_ACTL_ADDRESS);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400153 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400154 outb(val, VGAREG_ACTL_WRITE_DATA);
155 outb(0x20, VGAREG_ACTL_ADDRESS);
156}
157
158void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400159vgahw_select_video_dac_color_page(u8 flag, u8 data)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400160{
161 inb(VGAREG_ACTL_RESET);
162 outb(0x10, VGAREG_ACTL_ADDRESS);
163 u8 val = inb(VGAREG_ACTL_READ_DATA);
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400164 if (!(flag & 0x01)) {
165 // select paging mode
166 val = (val & 0x7f) | (data << 7);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400167 outb(val, VGAREG_ACTL_WRITE_DATA);
168 outb(0x20, VGAREG_ACTL_ADDRESS);
169 return;
170 }
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400171 // select page
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400172 inb(VGAREG_ACTL_RESET);
173 outb(0x14, VGAREG_ACTL_ADDRESS);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400174 if (!(val & 0x80))
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400175 data <<= 2;
176 data &= 0x0f;
177 outb(data, VGAREG_ACTL_WRITE_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400178 outb(0x20, VGAREG_ACTL_ADDRESS);
179}
180
181void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400182vgahw_read_video_dac_state(u8 *pmode, u8 *curpage)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400183{
184 inb(VGAREG_ACTL_RESET);
185 outb(0x10, VGAREG_ACTL_ADDRESS);
186 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
187
188 inb(VGAREG_ACTL_RESET);
189 outb(0x14, VGAREG_ACTL_ADDRESS);
190 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
191 if (!(val1 & 0x01))
192 val2 >>= 2;
193
194 inb(VGAREG_ACTL_RESET);
195 outb(0x20, VGAREG_ACTL_ADDRESS);
196
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400197 *pmode = val1;
198 *curpage = val2;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400199}
200
201
202/****************************************************************
203 * DAC control
204 ****************************************************************/
205
206void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400207vgahw_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400208{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400209 outb(start, VGAREG_DAC_WRITE_ADDRESS);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400210 while (count) {
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400211 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400212 data_far++;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400213 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400214 data_far++;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400215 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400216 data_far++;
217 count--;
218 }
219}
220
221void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400222vgahw_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400223{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400224 outb(start, VGAREG_DAC_READ_ADDRESS);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400225 while (count) {
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400226 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400227 data_far++;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400228 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400229 data_far++;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400230 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400231 data_far++;
232 count--;
233 }
234}
235
236void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400237vgahw_set_pel_mask(u8 val)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400238{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400239 outb(val, VGAREG_PEL_MASK);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400240}
241
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400242u8
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500243vgahw_get_pel_mask(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400244{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400245 return inb(VGAREG_PEL_MASK);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400246}
247
Kevin O'Connorca668642009-05-21 23:06:08 -0400248void
249vgahw_save_dac_state(u16 seg, struct saveDACcolors *info)
250{
251 /* XXX: check this */
252 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
253 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
254 SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
255 vgahw_get_dac_regs(seg, info->dac, 0, 256);
256 SET_FARVAR(seg, info->color_select, 0);
257}
258
259void
260vgahw_restore_dac_state(u16 seg, struct saveDACcolors *info)
261{
262 outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
263 vgahw_set_dac_regs(seg, info->dac, 0, 256);
264 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
265}
266
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400267
268/****************************************************************
269 * Memory control
270 ****************************************************************/
271
272void
Kevin O'Connor414d0732009-05-31 22:42:04 -0400273vgahw_sequ_write(u8 index, u8 value)
274{
275 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
276}
277
278void
279vgahw_grdc_write(u8 index, u8 value)
280{
281 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
282}
283
284void
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400285vgahw_set_text_block_specifier(u8 spec)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400286{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400287 outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400288}
289
290void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500291get_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400292{
293 outw(0x0100, VGAREG_SEQU_ADDRESS);
294 outw(0x0402, VGAREG_SEQU_ADDRESS);
295 outw(0x0704, VGAREG_SEQU_ADDRESS);
296 outw(0x0300, VGAREG_SEQU_ADDRESS);
297 outw(0x0204, VGAREG_GRDC_ADDRESS);
298 outw(0x0005, VGAREG_GRDC_ADDRESS);
299 outw(0x0406, VGAREG_GRDC_ADDRESS);
300}
301
302void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500303release_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400304{
305 outw(0x0100, VGAREG_SEQU_ADDRESS);
306 outw(0x0302, VGAREG_SEQU_ADDRESS);
307 outw(0x0304, VGAREG_SEQU_ADDRESS);
308 outw(0x0300, VGAREG_SEQU_ADDRESS);
309 u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
310 outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
311 outw(0x0004, VGAREG_GRDC_ADDRESS);
312 outw(0x1005, VGAREG_GRDC_ADDRESS);
313}
314
315
316/****************************************************************
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400317 * CRTC registers
318 ****************************************************************/
319
320static u16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500321get_crtc(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400322{
323 return GET_BDA(crtc_address);
324}
325
326void
327vgahw_set_cursor_shape(u8 start, u8 end)
328{
329 u16 crtc_addr = get_crtc();
330 outb(0x0a, crtc_addr);
331 outb(start, crtc_addr + 1);
332 outb(0x0b, crtc_addr);
333 outb(end, crtc_addr + 1);
334}
335
336void
337vgahw_set_active_page(u16 address)
338{
339 u16 crtc_addr = get_crtc();
340 outb(0x0c, crtc_addr);
341 outb((address & 0xff00) >> 8, crtc_addr + 1);
342 outb(0x0d, crtc_addr);
343 outb(address & 0x00ff, crtc_addr + 1);
344}
345
346void
347vgahw_set_cursor_pos(u16 address)
348{
349 u16 crtc_addr = get_crtc();
350 outb(0x0e, crtc_addr);
351 outb((address & 0xff00) >> 8, crtc_addr + 1);
352 outb(0x0f, crtc_addr);
353 outb(address & 0x00ff, crtc_addr + 1);
354}
355
356void
357vgahw_set_scan_lines(u8 lines)
358{
359 u16 crtc_addr = get_crtc();
360 outb(0x09, crtc_addr);
361 u8 crtc_r9 = inb(crtc_addr + 1);
362 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
363 outb(crtc_r9, crtc_addr + 1);
364}
365
366// Get vertical display end
367u16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500368vgahw_get_vde(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400369{
370 u16 crtc_addr = get_crtc();
371 outb(0x12, crtc_addr);
372 u16 vde = inb(crtc_addr + 1);
373 outb(0x07, crtc_addr);
374 u8 ovl = inb(crtc_addr + 1);
375 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
376 return vde;
377}
378
379
380/****************************************************************
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400381 * Save/Restore/Set state
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400382 ****************************************************************/
383
384void
Kevin O'Connorca668642009-05-21 23:06:08 -0400385vgahw_save_state(u16 seg, struct saveVideoHardware *info)
386{
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400387 u16 crtc_addr = get_crtc();
Kevin O'Connorca668642009-05-21 23:06:08 -0400388 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
389 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
390 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
391 inb(VGAREG_ACTL_RESET);
392 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
393 SET_FARVAR(seg, info->actl_index, ar_index);
394 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
395
396 u16 i;
397 for (i=0; i<4; i++) {
398 outb(i+1, VGAREG_SEQU_ADDRESS);
399 SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
400 }
401 outb(0, VGAREG_SEQU_ADDRESS);
402 SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
403
404 for (i=0; i<25; i++) {
405 outb(i, crtc_addr);
406 SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
407 }
408
409 for (i=0; i<20; i++) {
410 inb(VGAREG_ACTL_RESET);
411 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
412 SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
413 }
414 inb(VGAREG_ACTL_RESET);
415
416 for (i=0; i<9; i++) {
417 outb(i, VGAREG_GRDC_ADDRESS);
418 SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
419 }
420
421 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
422
423 /* XXX: read plane latches */
424 for (i=0; i<4; i++)
425 SET_FARVAR(seg, info->plane_latch[i], 0);
426}
427
428void
429vgahw_restore_state(u16 seg, struct saveVideoHardware *info)
430{
431 // Reset Attribute Ctl flip-flop
432 inb(VGAREG_ACTL_RESET);
433
434 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
435
436 u16 i;
437 for (i=0; i<4; i++) {
438 outb(i+1, VGAREG_SEQU_ADDRESS);
439 outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
440 }
441 outb(0, VGAREG_SEQU_ADDRESS);
442 outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
443
444 // Disable CRTC write protection
445 outw(0x0011, crtc_addr);
446 // Set CRTC regs
447 for (i=0; i<25; i++)
448 if (i != 0x11) {
449 outb(i, crtc_addr);
450 outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
451 }
452 // select crtc base address
453 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
454 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
455 v |= 0x01;
456 outb(v, VGAREG_WRITE_MISC_OUTPUT);
457
458 // enable write protection if needed
459 outb(0x11, crtc_addr);
460 outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
461
462 // Set Attribute Ctl
463 u16 ar_index = GET_FARVAR(seg, info->actl_index);
464 inb(VGAREG_ACTL_RESET);
465 for (i=0; i<20; i++) {
466 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
467 outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
468 }
469 outb(ar_index, VGAREG_ACTL_ADDRESS);
470 inb(VGAREG_ACTL_RESET);
471
472 for (i=0; i<9; i++) {
473 outb(i, VGAREG_GRDC_ADDRESS);
474 outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
475 }
476
477 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
478 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
479 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
480 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
481}
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400482
483void
Kevin O'Connor87233e92011-12-23 21:40:34 -0500484vgahw_set_mode(struct vgamode_s *vmode_g)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400485{
486 // Reset Attribute Ctl flip-flop
487 inb(VGAREG_ACTL_RESET);
488
489 // Set Attribute Ctl
Kevin O'Connor87233e92011-12-23 21:40:34 -0500490 u8 *regs = GET_GLOBAL(vmode_g->actl_regs);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400491 u16 i;
492 for (i = 0; i <= 0x13; i++) {
493 outb(i, VGAREG_ACTL_ADDRESS);
Kevin O'Connor87233e92011-12-23 21:40:34 -0500494 outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400495 }
496 outb(0x14, VGAREG_ACTL_ADDRESS);
497 outb(0x00, VGAREG_ACTL_WRITE_DATA);
498
499 // Set Sequencer Ctl
500 outb(0, VGAREG_SEQU_ADDRESS);
501 outb(0x03, VGAREG_SEQU_DATA);
Kevin O'Connor87233e92011-12-23 21:40:34 -0500502 regs = GET_GLOBAL(vmode_g->sequ_regs);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400503 for (i = 1; i <= 4; i++) {
504 outb(i, VGAREG_SEQU_ADDRESS);
Kevin O'Connor87233e92011-12-23 21:40:34 -0500505 outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400506 }
507
508 // Set Grafx Ctl
Kevin O'Connor87233e92011-12-23 21:40:34 -0500509 regs = GET_GLOBAL(vmode_g->grdc_regs);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400510 for (i = 0; i <= 8; i++) {
511 outb(i, VGAREG_GRDC_ADDRESS);
Kevin O'Connor87233e92011-12-23 21:40:34 -0500512 outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400513 }
514
515 // Set CRTC address VGA or MDA
Kevin O'Connor87233e92011-12-23 21:40:34 -0500516 u8 miscreg = GET_GLOBAL(vmode_g->miscreg);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400517 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
518 if (!(miscreg & 1))
519 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
520
521 // Disable CRTC write protection
522 outw(0x0011, crtc_addr);
523 // Set CRTC regs
Kevin O'Connor87233e92011-12-23 21:40:34 -0500524 regs = GET_GLOBAL(vmode_g->crtc_regs);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400525 for (i = 0; i <= 0x18; i++) {
526 outb(i, crtc_addr);
Kevin O'Connor87233e92011-12-23 21:40:34 -0500527 outb(GET_GLOBAL(regs[i]), crtc_addr + 1);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400528 }
529
530 // Set the misc register
531 outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
532
533 // Enable video
534 outb(0x20, VGAREG_ACTL_ADDRESS);
535 inb(VGAREG_ACTL_RESET);
536}
537
538
539/****************************************************************
540 * Misc
541 ****************************************************************/
542
543void
544vgahw_enable_video_addressing(u8 disable)
545{
546 u8 v = (disable & 1) ? 0x00 : 0x02;
547 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
548 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
549}
550
551void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500552vgahw_init(void)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400553{
554 // switch to color mode and enable CPU access 480 lines
555 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
556 // more than 64k 3C4/04
557 outb(0x04, VGAREG_SEQU_ADDRESS);
558 outb(0x02, VGAREG_SEQU_DATA);
559}