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Kevin O'Connor4ade5232013-09-18 21:41:48 -04001// Internal timer and Intel 8253 Programmable Interrupt Timer (PIT) support.
Kevin O'Connorc6e8c072013-07-20 10:51:58 -04002//
3// Copyright (C) 2008-2013 Kevin O'Connor <kevin@koconnor.net>
4//
5// This file may be distributed under the terms of the GNU LGPLv3 license.
6
Kevin O'Connorc6e8c072013-07-20 10:51:58 -04007#include "biosvar.h" // GET_LOW
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04008#include "config.h" // CONFIG_*
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04009#include "output.h" // dprintf
Kevin O'Connor3df600b2013-09-14 19:28:55 -040010#include "stacks.h" // yield
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040011#include "util.h" // timer_setup
Kevin O'Connorb9c6a962013-09-14 13:01:30 -040012#include "x86.h" // cpuid
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040013
Kevin O'Connor4ade5232013-09-18 21:41:48 -040014#define PORT_PIT_COUNTER0 0x0040
15#define PORT_PIT_COUNTER1 0x0041
16#define PORT_PIT_COUNTER2 0x0042
17#define PORT_PIT_MODE 0x0043
Kevin O'Connor09ae7f12014-11-03 09:48:21 -050018#define PORT_PS2_CTRLB 0x0061
Kevin O'Connor4ade5232013-09-18 21:41:48 -040019
Kevin O'Connor9fcd1992013-09-15 01:50:00 -040020// Bits for PORT_PIT_MODE
21#define PM_SEL_TIMER0 (0<<6)
22#define PM_SEL_TIMER1 (1<<6)
23#define PM_SEL_TIMER2 (2<<6)
24#define PM_SEL_READBACK (3<<6)
25#define PM_ACCESS_LATCH (0<<4)
26#define PM_ACCESS_LOBYTE (1<<4)
27#define PM_ACCESS_HIBYTE (2<<4)
28#define PM_ACCESS_WORD (3<<4)
29#define PM_MODE0 (0<<1)
30#define PM_MODE1 (1<<1)
31#define PM_MODE2 (2<<1)
32#define PM_MODE3 (3<<1)
33#define PM_MODE4 (4<<1)
34#define PM_MODE5 (5<<1)
35#define PM_CNT_BINARY (0<<0)
36#define PM_CNT_BCD (1<<0)
37#define PM_READ_COUNTER0 (1<<1)
38#define PM_READ_COUNTER1 (1<<2)
39#define PM_READ_COUNTER2 (1<<3)
40#define PM_READ_STATUSVALUE (0<<4)
41#define PM_READ_VALUE (1<<4)
42#define PM_READ_STATUS (2<<4)
43
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040044// Bits for PORT_PS2_CTRLB
45#define PPCB_T2GATE (1<<0)
46#define PPCB_SPKR (1<<1)
47#define PPCB_T2OUT (1<<5)
48
Kevin O'Connorb7ab1782013-07-20 13:06:35 -040049#define PMTIMER_HZ 3579545 // Underlying Hz of the PM Timer
50#define PMTIMER_TO_PIT 3 // Ratio of pmtimer rate to pit rate
Kevin O'Connorb7ab1782013-07-20 13:06:35 -040051
Kevin O'Connor4ec872a2015-07-23 08:36:01 -040052u32 TimerKHz VARFSEG = DIV_ROUND_UP(PMTIMER_HZ, 1000 * PMTIMER_TO_PIT);
53u16 TimerPort VARFSEG = PORT_PIT_COUNTER0;
Kevin O'Connor23c14a12013-07-20 17:06:51 -040054u8 ShiftTSC VARFSEG;
55
Kevin O'Connor99997542013-07-20 18:39:37 -040056
57/****************************************************************
Kevin O'Connor9fcd1992013-09-15 01:50:00 -040058 * Internal timer setup
Kevin O'Connor99997542013-07-20 18:39:37 -040059 ****************************************************************/
60
61#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
62
63// Calibrate the CPU time-stamp-counter
64static void
65tsctimer_setup(void)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040066{
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040067 // Setup "timer2"
68 u8 orig = inb(PORT_PS2_CTRLB);
69 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
70 /* binary, mode 0, LSB/MSB, Ch 2 */
71 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
72 /* LSB of ticks */
73 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
74 /* MSB of ticks */
75 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
76
77 u64 start = rdtscll();
78 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
79 ;
80 u64 end = rdtscll();
81
82 // Restore PORT_PS2_CTRLB
83 outb(orig, PORT_PS2_CTRLB);
84
85 // Store calibrated cpu khz.
86 u64 diff = end - start;
87 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
88 , (u32)start, (u32)end, (u32)diff);
Kevin O'Connor23c14a12013-07-20 17:06:51 -040089 u64 t = DIV_ROUND_UP(diff * PMTIMER_HZ, CALIBRATE_COUNT);
90 while (t >= (1<<24)) {
91 ShiftTSC++;
92 t = (t + 1) >> 1;
93 }
94 TimerKHz = DIV_ROUND_UP((u32)t, 1000 * PMTIMER_TO_PIT);
Kevin O'Connor4ec872a2015-07-23 08:36:01 -040095 TimerPort = 0;
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040096
Kevin O'Connor23c14a12013-07-20 17:06:51 -040097 dprintf(1, "CPU Mhz=%u\n", (TimerKHz << ShiftTSC) / 1000);
Kevin O'Connorc6e8c072013-07-20 10:51:58 -040098}
99
Kevin O'Connor99997542013-07-20 18:39:37 -0400100// Setup internal timers.
101void
102timer_setup(void)
103{
Gerd Hoffmann67cbfed2020-03-10 11:22:45 +0100104 if (!CONFIG_TSC_TIMER)
Kevin O'Connor99997542013-07-20 18:39:37 -0400105 return;
Gerd Hoffmann67cbfed2020-03-10 11:22:45 +0100106 if (TimerPort != PORT_PIT_COUNTER0)
107 return; // have timer already
Kevin O'Connor99997542013-07-20 18:39:37 -0400108
Kevin O'Connor4ec872a2015-07-23 08:36:01 -0400109 // Check if CPU has a timestamp counter
Kevin O'Connor99997542013-07-20 18:39:37 -0400110 u32 eax, ebx, ecx, edx, cpuid_features = 0;
111 cpuid(0, &eax, &ebx, &ecx, &edx);
112 if (eax > 0)
113 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
Kevin O'Connor4ec872a2015-07-23 08:36:01 -0400114 if (cpuid_features & CPUID_TSC)
115 tsctimer_setup();
Kevin O'Connor99997542013-07-20 18:39:37 -0400116}
117
118void
Gerd Hoffmann67cbfed2020-03-10 11:22:45 +0100119tsctimer_setfreq(u32 khz, const char *src)
120{
121 if (!CONFIG_TSC_TIMER)
122 return;
123 if (TimerPort != PORT_PIT_COUNTER0)
124 return; // have timer already
125
126 TimerKHz = khz;
127 ShiftTSC = 0;
128 while (TimerKHz >= 6000) {
129 ShiftTSC++;
130 TimerKHz = (TimerKHz + 1) >> 1;
131 }
132 TimerPort = 0;
133
134 dprintf(1, "CPU Mhz=%u (%s)\n", (TimerKHz << ShiftTSC) / 1000, src);
135}
136
137void
Kevin O'Connor99997542013-07-20 18:39:37 -0400138pmtimer_setup(u16 ioport)
139{
140 if (!CONFIG_PMTIMER)
141 return;
Gerd Hoffmann67cbfed2020-03-10 11:22:45 +0100142 if (TimerPort != PORT_PIT_COUNTER0)
143 return; // have timer already
144
Kevin O'Connor99997542013-07-20 18:39:37 -0400145 dprintf(1, "Using pmtimer, ioport 0x%x\n", ioport);
Kevin O'Connoreac11942013-07-20 19:09:07 -0400146 TimerPort = ioport;
Kevin O'Connor99997542013-07-20 18:39:37 -0400147 TimerKHz = DIV_ROUND_UP(PMTIMER_HZ, 1000);
148}
149
150
151/****************************************************************
152 * Internal timer reading
153 ****************************************************************/
154
Kevin O'Connoreac11942013-07-20 19:09:07 -0400155u32 TimerLast VARLOW;
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400156
Kevin O'Connoreac11942013-07-20 19:09:07 -0400157// Add extra high bits to timers that have less than 32bits of precision.
Kevin O'Connor23c14a12013-07-20 17:06:51 -0400158static u32
Kevin O'Connoreac11942013-07-20 19:09:07 -0400159timer_adjust_bits(u32 value, u32 validbits)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400160{
Kevin O'Connoreac11942013-07-20 19:09:07 -0400161 u32 last = GET_LOW(TimerLast);
162 value = (last & ~validbits) | (value & validbits);
163 if (value < last)
164 value += validbits + 1;
165 SET_LOW(TimerLast, value);
166 return value;
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400167}
168
Kevin O'Connoreac11942013-07-20 19:09:07 -0400169// Sample the current timer value.
Kevin O'Connor23c14a12013-07-20 17:06:51 -0400170static u32
Kevin O'Connor018bdd72013-07-20 18:22:57 -0400171timer_read(void)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400172{
Kevin O'Connoreac11942013-07-20 19:09:07 -0400173 u16 port = GET_GLOBAL(TimerPort);
Kevin O'Connor4ec872a2015-07-23 08:36:01 -0400174 if (CONFIG_TSC_TIMER && !port)
Kevin O'Connoreac11942013-07-20 19:09:07 -0400175 // Read from CPU TSC
176 return rdtscll() >> GET_GLOBAL(ShiftTSC);
177 if (CONFIG_PMTIMER && port != PORT_PIT_COUNTER0)
178 // Read from PMTIMER
179 return timer_adjust_bits(inl(port), 0xffffff);
180 // Read from PIT.
181 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
182 u16 v = inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8);
183 return timer_adjust_bits(v, 0xffff);
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400184}
185
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400186// Return the TSC value that is 'msecs' time in the future.
Kevin O'Connor23c14a12013-07-20 17:06:51 -0400187u32
Kevin O'Connor018bdd72013-07-20 18:22:57 -0400188timer_calc(u32 msecs)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400189{
Kevin O'Connor018bdd72013-07-20 18:22:57 -0400190 return timer_read() + (GET_GLOBAL(TimerKHz) * msecs);
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400191}
Kevin O'Connor23c14a12013-07-20 17:06:51 -0400192u32
Kevin O'Connor018bdd72013-07-20 18:22:57 -0400193timer_calc_usec(u32 usecs)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400194{
Kevin O'Connor488e1c32017-11-02 11:21:14 -0400195 u32 cur = timer_read(), khz = GET_GLOBAL(TimerKHz);
196 if (usecs > 500000)
197 return cur + DIV_ROUND_UP(usecs, 1000) * khz;
198 return cur + DIV_ROUND_UP(usecs * khz, 1000);
199}
200static u32
201timer_calc_nsec(u32 nsecs)
202{
203 u32 cur = timer_read(), khz = GET_GLOBAL(TimerKHz);
204 if (nsecs > 500000)
205 return cur + DIV_ROUND_UP(nsecs, 1000000) * khz;
206 return cur + DIV_ROUND_UP(nsecs * khz, 1000000);
207}
208
209// Check if the current time is past a previously calculated end time.
210int
211timer_check(u32 end)
212{
213 return (s32)(timer_read() - end) > 0;
214}
215
216static void
217timer_delay(u32 end)
218{
219 while (!timer_check(end))
220 cpu_relax();
221}
222
223static void
224timer_sleep(u32 end)
225{
226 while (!timer_check(end))
227 yield();
228}
229
230void ndelay(u32 count) {
231 timer_delay(timer_calc_nsec(count));
232}
233void udelay(u32 count) {
234 timer_delay(timer_calc_usec(count));
235}
236void mdelay(u32 count) {
237 timer_delay(timer_calc(count));
238}
239
240void nsleep(u32 count) {
241 timer_sleep(timer_calc_nsec(count));
242}
243void usleep(u32 count) {
244 timer_sleep(timer_calc_usec(count));
245}
246void msleep(u32 count) {
247 timer_sleep(timer_calc(count));
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400248}
249
250
251/****************************************************************
Kevin O'Connor9fcd1992013-09-15 01:50:00 -0400252 * PIT setup
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400253 ****************************************************************/
254
Kevin O'Connoreac11942013-07-20 19:09:07 -0400255#define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
256
Kevin O'Connor69013372013-07-20 12:08:48 -0400257// Return the number of milliseconds in 'ticks' number of timer irqs.
258u32
259ticks_to_ms(u32 ticks)
260{
Kevin O'Connorb7ab1782013-07-20 13:06:35 -0400261 u32 t = PIT_TICK_INTERVAL * 1000 * PMTIMER_TO_PIT * ticks;
262 return DIV_ROUND_UP(t, PMTIMER_HZ);
Kevin O'Connor69013372013-07-20 12:08:48 -0400263}
264
265// Return the number of timer irqs in 'ms' number of milliseconds.
266u32
267ticks_from_ms(u32 ms)
268{
Kevin O'Connorb7ab1782013-07-20 13:06:35 -0400269 u32 t = DIV_ROUND_UP((u64)ms * PMTIMER_HZ, PIT_TICK_INTERVAL);
270 return DIV_ROUND_UP(t, 1000 * PMTIMER_TO_PIT);
Kevin O'Connor69013372013-07-20 12:08:48 -0400271}
272
Kevin O'Connor9fcd1992013-09-15 01:50:00 -0400273void
274pit_setup(void)
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400275{
Kevin O'Connorbd5f6c72015-08-10 16:14:48 -0400276 if (!CONFIG_HARDWARE_IRQ)
277 return;
Kevin O'Connor9fcd1992013-09-15 01:50:00 -0400278 // timer0: binary count, 16bit count, mode 2
279 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
280 // maximum count of 0000H = 18.2Hz
281 outb(0x0, PORT_PIT_COUNTER0);
282 outb(0x0, PORT_PIT_COUNTER0);
Kevin O'Connorc6e8c072013-07-20 10:51:58 -0400283}