blob: 886deca0f315f1ad1d47bab2cb2b46d08b8f19cd [file] [log] [blame]
Kevin O'Connor3471fdb2012-01-14 19:02:43 -05001// Standard VGA driver code
Kevin O'Connorc0c7df62009-05-17 18:11:33 -04002//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2001-2008 the LGPL VGABios developers Team
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connorc990f272011-12-31 16:00:54 -05008#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor4ade5232013-09-18 21:41:48 -04009#include "farptr.h" // SET_FARVAR
10#include "stdvga.h" // stdvga_setup
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040011#include "string.h" // memset_far
Kevin O'Connor4ade5232013-09-18 21:41:48 -040012#include "vgabios.h" // struct vgamode_s
Kevin O'Connorc682ffe2016-08-05 11:48:20 -040013#include "vgautil.h" // stdvga_attr_write
Kevin O'Connor4ade5232013-09-18 21:41:48 -040014#include "x86.h" // outb
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040015
16
17/****************************************************************
18 * Attribute control
19 ****************************************************************/
20
Kevin O'Connora0ecb052009-05-18 23:34:00 -040021void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050022stdvga_set_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040023{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040024 u8 v1 = color & 0x0f;
25 if (v1 & 0x08)
26 v1 += 0x08;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050027 stdvga_attr_write(0x00, v1);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040028
29 int i;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050030 for (i = 1; i < 4; i++)
31 stdvga_attr_mask(i, 0x10, color & 0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040032}
33
34void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050035stdvga_set_overscan_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040036{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050037 stdvga_attr_write(0x11, color);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040038}
39
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040040u8
Kevin O'Connor88ca7412011-12-31 04:24:20 -050041stdvga_get_overscan_border_color(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040042{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050043 return stdvga_attr_read(0x11);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040044}
45
46void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050047stdvga_set_palette(u8 palid)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040048{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040049 int i;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050050 for (i = 1; i < 4; i++)
51 stdvga_attr_mask(i, 0x01, palid & 0x01);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040052}
53
54void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050055stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040056{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040057 int i;
58 for (i = 0; i < 0x10; i++) {
Kevin O'Connor86d2e002012-01-14 22:17:07 -050059 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040060 data_far++;
61 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -050062 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040063}
64
65void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050066stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040067{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040068 int i;
69 for (i = 0; i < 0x10; i++) {
Kevin O'Connor86d2e002012-01-14 22:17:07 -050070 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040071 data_far++;
72 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -050073 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040074}
75
76void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050077stdvga_toggle_intensity(u8 flag)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040078{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050079 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040080}
81
82void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050083stdvga_select_video_dac_color_page(u8 flag, u8 data)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040084{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040085 if (!(flag & 0x01)) {
86 // select paging mode
Kevin O'Connor86d2e002012-01-14 22:17:07 -050087 stdvga_attr_mask(0x10, 0x80, data << 7);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040088 return;
89 }
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040090 // select page
Kevin O'Connor86d2e002012-01-14 22:17:07 -050091 u8 val = stdvga_attr_read(0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040092 if (!(val & 0x80))
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040093 data <<= 2;
94 data &= 0x0f;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050095 stdvga_attr_write(0x14, data);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040096}
97
98void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050099stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400100{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500101 u8 val1 = stdvga_attr_read(0x10) >> 7;
102 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400103 if (!(val1 & 0x01))
104 val2 >>= 2;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400105 *pmode = val1;
106 *curpage = val2;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400107}
108
109
110/****************************************************************
111 * DAC control
112 ****************************************************************/
113
114void
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500115stdvga_perform_gray_scale_summing(u16 start, u16 count)
116{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500117 stdvga_attrindex_write(0x00);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500118 int i;
119 for (i = start; i < start+count; i++) {
120 u8 rgb[3];
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500121 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500122
123 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
124 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
125 if (intensity > 0x3f)
126 intensity = 0x3f;
Kevin O'Connor9cba2b32013-03-09 13:00:40 -0500127 rgb[0] = rgb[1] = rgb[2] = intensity;
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500128
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500129 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500130 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500131 stdvga_attrindex_write(0x20);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500132}
133
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400134
135/****************************************************************
136 * Memory control
137 ****************************************************************/
138
139void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500140stdvga_set_text_block_specifier(u8 spec)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400141{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500142 stdvga_sequ_write(0x03, spec);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400143}
144
Kevin O'Connor160d34a2012-01-16 18:48:26 -0500145// Enable reads and writes to the given "plane" when in planar4 mode.
146void
147stdvga_planar4_plane(int plane)
148{
149 if (plane < 0) {
150 // Return to default mode (read plane0, write all planes)
151 stdvga_sequ_write(0x02, 0x0f);
152 stdvga_grdc_write(0x04, 0);
153 } else {
154 stdvga_sequ_write(0x02, 1<<plane);
155 stdvga_grdc_write(0x04, plane);
156 }
157}
158
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500159
160/****************************************************************
161 * Font loading
162 ****************************************************************/
163
164static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500165get_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400166{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500167 stdvga_sequ_write(0x00, 0x01);
168 stdvga_sequ_write(0x02, 0x04);
169 stdvga_sequ_write(0x04, 0x07);
170 stdvga_sequ_write(0x00, 0x03);
171 stdvga_grdc_write(0x04, 0x02);
172 stdvga_grdc_write(0x05, 0x00);
173 stdvga_grdc_write(0x06, 0x04);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400174}
175
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500176static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500177release_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400178{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500179 stdvga_sequ_write(0x00, 0x01);
180 stdvga_sequ_write(0x02, 0x03);
181 stdvga_sequ_write(0x04, 0x03);
182 stdvga_sequ_write(0x00, 0x03);
183 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
184 stdvga_grdc_write(0x06, v);
185 stdvga_grdc_write(0x04, 0x00);
186 stdvga_grdc_write(0x05, 0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400187}
188
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500189void
190stdvga_load_font(u16 seg, void *src_far, u16 count
191 , u16 start, u8 destflags, u8 fontsize)
192{
193 get_font_access();
194 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
195 void *dest_far = (void*)(blockaddr + start*32);
196 u16 i;
197 for (i = 0; i < count; i++)
198 memcpy_far(SEG_GRAPH, dest_far + i*32
199 , seg, src_far + i*fontsize, fontsize);
200 release_font_access();
201}
202
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400203
204/****************************************************************
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400205 * CRTC registers
206 ****************************************************************/
207
Kevin O'Connorc990f272011-12-31 16:00:54 -0500208u16
209stdvga_get_crtc(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400210{
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500211 if (stdvga_misc_read() & 1)
Kevin O'Connorc990f272011-12-31 16:00:54 -0500212 return VGAREG_VGA_CRTC_ADDRESS;
213 return VGAREG_MDA_CRTC_ADDRESS;
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400214}
215
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400216// Ratio between system visible framebuffer ram and the actual videoram used.
Kevin O'Connor3876b532012-01-24 00:07:44 -0500217int
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400218stdvga_vram_ratio(struct vgamode_s *vmode_g)
Kevin O'Connor3876b532012-01-24 00:07:44 -0500219{
220 switch (GET_GLOBAL(vmode_g->memmodel)) {
221 case MM_TEXT:
222 return 2;
223 case MM_CGA:
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400224 return 4 / GET_GLOBAL(vmode_g->depth);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500225 case MM_PLANAR:
Kevin O'Connor3876b532012-01-24 00:07:44 -0500226 return 4;
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400227 default:
228 return 1;
Kevin O'Connor3876b532012-01-24 00:07:44 -0500229 }
230}
231
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400232void
Kevin O'Connorc9aecfc2014-10-22 20:57:37 -0400233stdvga_set_cursor_shape(u16 cursor_type)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400234{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500235 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connorc9aecfc2014-10-22 20:57:37 -0400236 stdvga_crtc_write(crtc_addr, 0x0a, cursor_type >> 8);
237 stdvga_crtc_write(crtc_addr, 0x0b, cursor_type);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400238}
239
240void
Kevin O'Connor16920072012-01-27 22:59:46 -0500241stdvga_set_cursor_pos(int address)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400242{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500243 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor16920072012-01-27 22:59:46 -0500244 address /= 2; // Assume we're in text mode.
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500245 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
246 stdvga_crtc_write(crtc_addr, 0x0f, address);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400247}
248
249void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500250stdvga_set_scan_lines(u8 lines)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400251{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500252 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400253}
254
255// Get vertical display end
256u16
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500257stdvga_get_vde(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400258{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500259 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500260 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
261 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400262 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
263 return vde;
264}
265
Kevin O'Connor9961f992012-01-21 11:53:44 -0500266int
267stdvga_get_window(struct vgamode_s *vmode_g, int window)
268{
269 return -1;
270}
271
272int
273stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
274{
275 return -1;
276}
277
Kevin O'Connor3876b532012-01-24 00:07:44 -0500278int
279stdvga_get_linelength(struct vgamode_s *vmode_g)
280{
281 u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400282 return val * 8 / stdvga_vram_ratio(vmode_g);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500283}
284
285int
286stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
287{
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400288 val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
289 stdvga_crtc_write(stdvga_get_crtc(), 0x13, val);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500290 return 0;
291}
292
Kevin O'Connord61fc532012-01-27 20:37:45 -0500293int
294stdvga_get_displaystart(struct vgamode_s *vmode_g)
295{
296 u16 crtc_addr = stdvga_get_crtc();
297 int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
298 | stdvga_crtc_read(crtc_addr, 0x0d));
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400299 return addr * 4 / stdvga_vram_ratio(vmode_g);
Kevin O'Connord61fc532012-01-27 20:37:45 -0500300}
301
302int
303stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
304{
305 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400306 val = val * stdvga_vram_ratio(vmode_g) / 4;
Kevin O'Connord61fc532012-01-27 20:37:45 -0500307 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
308 stdvga_crtc_write(crtc_addr, 0x0d, val);
309 return 0;
310}
311
Kevin O'Connore737b172012-02-04 11:08:39 -0500312int
313stdvga_get_dacformat(struct vgamode_s *vmode_g)
314{
315 return -1;
316}
317
318int
319stdvga_set_dacformat(struct vgamode_s *vmode_g, int val)
320{
321 return -1;
322}
323
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400324
325/****************************************************************
Kevin O'Connorf98bbf02012-01-27 23:09:02 -0500326 * Save/Restore state
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400327 ****************************************************************/
328
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500329struct saveVideoHardware {
330 u8 sequ_index;
331 u8 crtc_index;
332 u8 grdc_index;
333 u8 actl_index;
334 u8 feature;
335 u8 sequ_regs[4];
336 u8 sequ0;
337 u8 crtc_regs[25];
338 u8 actl_regs[20];
339 u8 grdc_regs[9];
340 u16 crtc_addr;
341 u8 plane_latch[4];
Kevin O'Connorf5ec1e02014-02-05 18:49:44 -0500342} PACKED;
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500343
344static void
345stdvga_save_hw_state(u16 seg, struct saveVideoHardware *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400346{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500347 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connorca668642009-05-21 23:06:08 -0400348 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
349 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
350 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500351 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
Kevin O'Connorca668642009-05-21 23:06:08 -0400352 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
353
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500354 int i;
355 for (i=0; i<4; i++)
356 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
357 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
Kevin O'Connorca668642009-05-21 23:06:08 -0400358
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500359 for (i=0; i<25; i++)
360 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400361
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500362 for (i=0; i<20; i++)
363 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400364
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500365 for (i=0; i<9; i++)
366 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400367
368 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
369
370 /* XXX: read plane latches */
371 for (i=0; i<4; i++)
372 SET_FARVAR(seg, info->plane_latch[i], 0);
373}
374
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500375static void
376stdvga_restore_hw_state(u16 seg, struct saveVideoHardware *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400377{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500378 int i;
379 for (i=0; i<4; i++)
380 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
381 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
Kevin O'Connorca668642009-05-21 23:06:08 -0400382
383 // Disable CRTC write protection
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500384 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
385 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
Kevin O'Connorca668642009-05-21 23:06:08 -0400386 // Set CRTC regs
387 for (i=0; i<25; i++)
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500388 if (i != 0x11)
389 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400390 // select crtc base address
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500391 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
Kevin O'Connorca668642009-05-21 23:06:08 -0400392
393 // enable write protection if needed
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500394 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400395
396 // Set Attribute Ctl
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500397 for (i=0; i<20; i++)
398 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
399 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
Kevin O'Connorca668642009-05-21 23:06:08 -0400400
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500401 for (i=0; i<9; i++)
402 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400403
404 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
405 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
406 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
407 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
408}
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400409
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500410struct saveDACcolors {
411 u8 rwmode;
412 u8 peladdr;
413 u8 pelmask;
414 u8 dac[768];
415 u8 color_select;
Kevin O'Connorf5ec1e02014-02-05 18:49:44 -0500416} PACKED;
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500417
418static void
419stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
420{
421 /* XXX: check this */
422 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
423 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
424 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
425 stdvga_dac_read(seg, info->dac, 0, 256);
426 SET_FARVAR(seg, info->color_select, 0);
427}
428
429static void
430stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
431{
432 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
433 stdvga_dac_write(seg, info->dac, 0, 256);
434 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
435}
436
437int
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500438stdvga_save_restore(int cmd, u16 seg, void *data)
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500439{
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500440 void *pos = data;
441 if (cmd & SR_HARDWARE) {
442 if (cmd & SR_SAVE)
443 stdvga_save_hw_state(seg, pos);
444 if (cmd & SR_RESTORE)
445 stdvga_restore_hw_state(seg, pos);
446 pos += sizeof(struct saveVideoHardware);
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500447 }
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500448 pos += bda_save_restore(cmd, seg, pos);
449 if (cmd & SR_DAC) {
450 if (cmd & SR_SAVE)
451 stdvga_save_dac_state(seg, pos);
452 if (cmd & SR_RESTORE)
453 stdvga_restore_dac_state(seg, pos);
454 pos += sizeof(struct saveDACcolors);
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500455 }
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500456 return pos - data;
Kevin O'Connor9f857fc2012-02-04 11:59:02 -0500457}
458
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400459
460/****************************************************************
461 * Misc
462 ****************************************************************/
463
464void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500465stdvga_enable_video_addressing(u8 disable)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400466{
467 u8 v = (disable & 1) ? 0x00 : 0x02;
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500468 stdvga_misc_mask(0x02, v);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400469}
470
Kevin O'Connor161d2012011-12-31 19:42:21 -0500471int
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500472stdvga_setup(void)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400473{
474 // switch to color mode and enable CPU access 480 lines
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500475 stdvga_misc_write(0xc3);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400476 // more than 64k 3C4/04
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500477 stdvga_sequ_write(0x04, 0x02);
Kevin O'Connor161d2012011-12-31 19:42:21 -0500478
479 return 0;
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400480}