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Kevin O'Connor190cc622010-03-09 19:43:52 -05001#ifndef __USB_EHCI_H
2#define __USB_EHCI_H
3
4// usb-ehci.c
Kevin O'Connor8ff8e012011-07-09 14:11:21 -04005int ehci_init(struct pci_device *pci, int busid, struct pci_device *comppci);
Kevin O'Connor54bf2072012-03-09 07:52:33 -05006struct usbdevice_s;
7struct usb_endpoint_descriptor;
Kevin O'Connorc3d96c22012-03-10 09:03:25 -05008struct usb_pipe *ehci_alloc_pipe(struct usbdevice_s *usbdev
9 , struct usb_endpoint_descriptor *epdesc);
Kevin O'Connor190cc622010-03-09 19:43:52 -050010struct usb_pipe;
Kevin O'Connor190cc622010-03-09 19:43:52 -050011int ehci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
12 , void *data, int datasize);
Kevin O'Connor190cc622010-03-09 19:43:52 -050013int ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize);
Kevin O'Connor190cc622010-03-09 19:43:52 -050014int ehci_poll_intr(struct usb_pipe *p, void *data);
15
16
17/****************************************************************
18 * ehci structs and flags
19 ****************************************************************/
20
21struct ehci_caps {
22 u8 caplength;
23 u8 reserved_01;
24 u16 hciversion;
25 u32 hcsparams;
26 u32 hccparams;
27 u64 portroute;
28} PACKED;
29
30#define HCC_64BIT_ADDR 1
31
32#define HCS_N_PORTS_MASK 0xf
33
34struct ehci_regs {
35 u32 usbcmd;
36 u32 usbsts;
37 u32 usbintr;
38 u32 frindex;
39 u32 ctrldssegment;
40 u32 periodiclistbase;
41 u32 asynclistbase;
42 u32 reserved[9];
43 u32 configflag;
44 u32 portsc[0];
45} PACKED;
46
47#define CMD_PARK (1<<11)
48#define CMD_PARK_CNT(c) (((c)>>8)&3)
49#define CMD_LRESET (1<<7)
50#define CMD_IAAD (1<<6)
51#define CMD_ASE (1<<5)
52#define CMD_PSE (1<<4)
53#define CMD_HCRESET (1<<1)
54#define CMD_RUN (1<<0)
55
56#define STS_ASS (1<<15)
57#define STS_PSS (1<<14)
58#define STS_RECL (1<<13)
59#define STS_HALT (1<<12)
60#define STS_IAA (1<<5)
61#define STS_FATAL (1<<4)
62#define STS_FLR (1<<3)
63#define STS_PCD (1<<2)
64#define STS_ERR (1<<1)
65#define STS_INT (1<<0)
66
67#define FLAG_CF (1<<0)
68
69#define PORT_WKOC_E (1<<22)
70#define PORT_WKDISC_E (1<<21)
71#define PORT_WKCONN_E (1<<20)
72#define PORT_TEST_PKT (0x4<<16)
73#define PORT_LED_OFF (0<<14)
74#define PORT_LED_AMBER (1<<14)
75#define PORT_LED_GREEN (2<<14)
76#define PORT_LED_MASK (3<<14)
77#define PORT_OWNER (1<<13)
78#define PORT_POWER (1<<12)
79#define PORT_LINESTATUS_MASK (3<<10)
80#define PORT_LINESTATUS_KSTATE (1<<10)
81#define PORT_RESET (1<<8)
82#define PORT_SUSPEND (1<<7)
83#define PORT_RESUME (1<<6)
84#define PORT_OCC (1<<5)
85#define PORT_OC (1<<4)
86#define PORT_PEC (1<<3)
87#define PORT_PE (1<<2)
88#define PORT_CSC (1<<1)
89#define PORT_CONNECT (1<<0)
90#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
91
92
Sven Schnellea3fa66c2012-06-12 09:20:23 +020093#define EHCI_QH_ALIGN 128 // Can't span a 4K boundary, so increase from 32
Kevin O'Connor190cc622010-03-09 19:43:52 -050094
95struct ehci_qh {
96 u32 next;
97 u32 info1;
98 u32 info2;
99 u32 current;
100
101 u32 qtd_next;
102 u32 alt_next;
103 u32 token;
104 u32 buf[5];
Sven Schnellea3fa66c2012-06-12 09:20:23 +0200105 u32 buf_hi[5];
Kevin O'Connor190cc622010-03-09 19:43:52 -0500106} PACKED;
107
108#define QH_CONTROL (1 << 27)
109#define QH_MAXPACKET_SHIFT 16
110#define QH_MAXPACKET_MASK (0x7ff << QH_MAXPACKET_SHIFT)
111#define QH_HEAD (1 << 15)
112#define QH_TOGGLECONTROL (1 << 14)
113#define QH_SPEED_SHIFT 12
114#define QH_SPEED_MASK (0x3 << QH_SPEED_SHIFT)
115#define QH_EP_SHIFT 8
116#define QH_EP_MASK (0xf << QH_EP_SHIFT)
117#define QH_DEVADDR_SHIFT 0
118#define QH_DEVADDR_MASK (0x7f << QH_DEVADDR_SHIFT)
119
120#define QH_SMASK_SHIFT 0
121#define QH_SMASK_MASK (0xff << QH_SMASK_SHIFT)
122#define QH_CMASK_SHIFT 8
123#define QH_CMASK_MASK (0xff << QH_CMASK_SHIFT)
124#define QH_HUBADDR_SHIFT 16
125#define QH_HUBADDR_MASK (0x7f << QH_HUBADDR_SHIFT)
126#define QH_HUBPORT_SHIFT 23
127#define QH_HUBPORT_MASK (0x7f << QH_HUBPORT_SHIFT)
128#define QH_MULT_SHIFT 30
129#define QH_MULT_MASK (0x3 << QH_MULT_SHIFT)
130
131#define EHCI_PTR_BITS 0x001F
132#define EHCI_PTR_TERM 0x0001
133#define EHCI_PTR_QH 0x0002
134
135
Sven Schnellea3fa66c2012-06-12 09:20:23 +0200136#define EHCI_QTD_ALIGN 64 // Can't span a 4K boundary, so increase from 32
Kevin O'Connor190cc622010-03-09 19:43:52 -0500137
138struct ehci_qtd {
139 u32 qtd_next;
140 u32 alt_next;
141 u32 token;
142 u32 buf[5];
Sven Schnellea3fa66c2012-06-12 09:20:23 +0200143 u32 buf_hi[5];
144 /* keep struct size a multiple of 64 bytes, as we're allocating
145 arrays. Without this padding, the second qtd could have the
146 wrong alignment. */
147} PACKED __aligned(EHCI_QTD_ALIGN);
Kevin O'Connor190cc622010-03-09 19:43:52 -0500148
149#define QTD_TOGGLE (1 << 31)
150#define QTD_LENGTH_SHIFT 16
151#define QTD_LENGTH_MASK (0x7fff << QTD_LENGTH_SHIFT)
152#define QTD_CERR_SHIFT 10
153#define QTD_CERR_MASK (0x3 << QTD_CERR_SHIFT)
154#define QTD_IOC (1 << 15)
155#define QTD_PID_OUT (0x0 << 8)
156#define QTD_PID_IN (0x1 << 8)
157#define QTD_PID_SETUP (0x2 << 8)
158#define QTD_STS_ACTIVE (1 << 7)
159#define QTD_STS_HALT (1 << 6)
160#define QTD_STS_DBE (1 << 5)
161#define QTD_STS_BABBLE (1 << 4)
162#define QTD_STS_XACT (1 << 3)
163#define QTD_STS_MMF (1 << 2)
164#define QTD_STS_STS (1 << 1)
165#define QTD_STS_PING (1 << 0)
166
167#define ehci_explen(len) (((len) << QTD_LENGTH_SHIFT) & QTD_LENGTH_MASK)
168
169#define ehci_maxerr(err) (((err) << QTD_CERR_SHIFT) & QTD_CERR_MASK)
170
171
172struct ehci_framelist {
173 u32 links[1024];
174} PACKED;
175
176#endif // usb-ehci.h