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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
Kevin O'Connor9a79b912014-01-15 11:08:22 -05008#include "byteorder.h" // le64_to_cpu
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04009#include "config.h" // CONFIG_*
10#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
Paolo Bonzini40d03122014-05-15 13:22:26 +020011#include "dev-piix.h" // PIIX_*
Kevin O'Connorc167e542015-09-29 09:40:46 -040012#include "e820map.h" // e820_add
Kevin O'Connor4ade5232013-09-18 21:41:48 -040013#include "hw/ata.h" // PORT_ATA1_CMD_BASE
Kevin O'Connor5d369d82013-09-02 20:48:46 -040014#include "hw/pci.h" // pci_config_readl
Kevin O'Connor4d8510c2016-02-03 01:28:20 -050015#include "hw/pcidevice.h" // pci_probe_devices
Kevin O'Connor5d369d82013-09-02 20:48:46 -040016#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
17#include "hw/pci_regs.h" // PCI_COMMAND
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +030018#include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE
Kevin O'Connora88c1972013-06-08 21:51:46 -040019#include "list.h" // struct hlist_node
Kevin O'Connor9dea5902013-09-14 20:23:54 -040020#include "malloc.h" // free
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040021#include "output.h" // dprintf
22#include "paravirt.h" // RamSize
Kevin O'Connor9a79b912014-01-15 11:08:22 -050023#include "romfile.h" // romfile_loadint
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040024#include "string.h" // memset
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040025#include "util.h" // pci_setup
Kevin O'Connor4ade5232013-09-18 21:41:48 -040026#include "x86.h" // outb
Isaku Yamahata72a590e2012-11-28 10:17:33 +010027
Gerd Hoffmann67a3c7c2013-11-26 13:12:04 +010028#define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
29#define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
30#define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090031
Kevin O'Connor62ff9d52016-02-03 00:47:27 -050032#define PCI_ROM_SLOT 6
33#define PCI_NUM_REGIONS 7
34#define PCI_BRIDGE_NUM_REGIONS 2
35
36enum pci_region_type {
37 PCI_REGION_TYPE_IO,
38 PCI_REGION_TYPE_MEM,
39 PCI_REGION_TYPE_PREFMEM,
40 PCI_REGION_TYPE_COUNT,
41};
42
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020043static const char *region_type_name[] = {
44 [ PCI_REGION_TYPE_IO ] = "io",
45 [ PCI_REGION_TYPE_MEM ] = "mem",
46 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
47};
48
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020049u64 pcimem_start = BUILD_PCIMEM_START;
50u64 pcimem_end = BUILD_PCIMEM_END;
51u64 pcimem64_start = BUILD_PCIMEM64_START;
52u64 pcimem64_end = BUILD_PCIMEM64_END;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +020053u64 pci_io_low_end = 0xa000;
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020054
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120055struct pci_region_entry {
56 struct pci_device *dev;
57 int bar;
Alexey Korolev030288f2012-04-19 17:44:55 +120058 u64 size;
59 u64 align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120060 int is64;
61 enum pci_region_type type;
Kevin O'Connora88c1972013-06-08 21:51:46 -040062 struct hlist_node node;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120063};
64
Alexey Korolev35a770f2012-04-19 17:47:19 +120065struct pci_region {
Alexey Korolev35a770f2012-04-19 17:47:19 +120066 /* pci region assignments */
67 u64 base;
Kevin O'Connora88c1972013-06-08 21:51:46 -040068 struct hlist_head list;
Alexey Korolev35a770f2012-04-19 17:47:19 +120069};
70
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040071struct pci_bus {
Alexey Korolev35a770f2012-04-19 17:47:19 +120072 struct pci_region r[PCI_REGION_TYPE_COUNT];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -040073 struct pci_device *bus_dev;
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040074};
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020075
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040076static u32 pci_bar(struct pci_device *pci, int region_num)
Isaku Yamahataa65821d2010-06-22 17:57:50 +090077{
78 if (region_num != PCI_ROM_SLOT) {
79 return PCI_BASE_ADDRESS_0 + region_num * 4;
80 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090081
82#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040083 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
Isaku Yamahata5d0de152010-06-22 17:57:51 +090084 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090085}
86
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040087static void
Alexey Korolev030288f2012-04-19 17:44:55 +120088pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
Kevin O'Connor0525d292008-07-04 06:18:30 -040089{
Alexey Korolev030288f2012-04-19 17:44:55 +120090 u32 ofs = pci_bar(pci, bar);
91 pci_config_writel(pci->bdf, ofs, addr);
92 if (is64)
93 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090094}
95
Kevin O'Connor5bab7e62011-10-01 11:33:31 -040096
97/****************************************************************
98 * Misc. device init
99 ****************************************************************/
100
101/* host irqs corresponding to PCI irqs A-D */
102const u8 pci_irqs[4] = {
103 10, 10, 11, 11
104};
105
Alex Williamsondbb7a662013-02-21 09:12:23 -0700106static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
107{
108 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
109
110 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
111}
112
113static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
114 dummy_pci_slot_get_irq;
Alex Williamsonb9490402013-02-15 14:11:41 -0700115
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400116// Return the global irq number corresponding to a host bus device irq pin.
Alex Williamsonb9490402013-02-15 14:11:41 -0700117static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400118{
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200119 int slot_addend = 0;
120
121 while (pci->parent != NULL) {
122 slot_addend += pci_bdf_to_dev(pci->bdf);
123 pci = pci->parent;
124 }
125 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400126 return pci_irqs[(pin - 1 + slot_addend) & 3];
Kevin O'Connor0525d292008-07-04 06:18:30 -0400127}
128
Alex Williamsonb9490402013-02-15 14:11:41 -0700129static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
130{
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500131 int pin_addend = 0;
Alex Williamsonb9490402013-02-15 14:11:41 -0700132 while (pci->parent != NULL) {
133 pin_addend += pci_bdf_to_dev(pci->bdf);
134 pci = pci->parent;
135 }
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500136 u8 slot = pci_bdf_to_dev(pci->bdf);
137 if (slot <= 24)
138 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
139 with a different starting index - see q35-acpi-dsdt.dsl */
140 return pci_irqs[(pin - 1 + pin_addend + slot) & 3];
Alex Williamsonb9490402013-02-15 14:11:41 -0700141 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
Kevin O'Connor9f505f72014-11-12 18:00:30 -0500142 return pci_irqs[(pin - 1 + pin_addend) & 3];
Alex Williamsonb9490402013-02-15 14:11:41 -0700143}
144
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400145/* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500146static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400147{
148 int i, irq;
149 u8 elcr[2];
150
151 elcr[0] = 0x00;
152 elcr[1] = 0x00;
153 for (i = 0; i < 4; i++) {
154 irq = pci_irqs[i];
155 /* set to trigger level */
156 elcr[irq >> 3] |= (1 << (irq & 7));
157 /* activate irq remapping in PIIX */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400158 pci_config_writeb(pci->bdf, 0x60 + i, irq);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400159 }
Paolo Bonzini40d03122014-05-15 13:22:26 +0200160 outb(elcr[0], PIIX_PORT_ELCR1);
161 outb(elcr[1], PIIX_PORT_ELCR2);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400162 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
163}
164
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200165static void mch_isa_lpc_setup(u16 bdf)
166{
167 /* pm io base */
168 pci_config_writel(bdf, ICH9_LPC_PMBASE,
169 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
170
171 /* acpi enable, SCI: IRQ9 000b = irq9*/
172 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
173
174 /* set root complex register block BAR */
175 pci_config_writel(bdf, ICH9_LPC_RCBA,
176 ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
177}
178
179static int ICH9LpcBDF = -1;
180
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100181/* ICH9 LPC PCI to ISA bridge */
182/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500183static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100184{
185 u16 bdf = dev->bdf;
186 int i, irq;
187 u8 elcr[2];
188
189 elcr[0] = 0x00;
190 elcr[1] = 0x00;
191
192 for (i = 0; i < 4; i++) {
193 irq = pci_irqs[i];
194 /* set to trigger level */
195 elcr[irq >> 3] |= (1 << (irq & 7));
196
197 /* activate irq remapping in LPC */
198
199 /* PIRQ[A-D] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700200 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100201 /* PIRQ[E-H] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700202 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100203 }
204 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
205 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
206 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
207
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200208 ICH9LpcBDF = bdf;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100209
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200210 mch_isa_lpc_setup(bdf);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100211
Kevin O'Connorc167e542015-09-29 09:40:46 -0400212 e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
Paulo Alcantara7f50afc2015-07-09 21:04:01 -0300213
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200214 acpi_pm1a_cnt = acpi_pm_base + 0x04;
215 pmtimer_setup(acpi_pm_base + 0x08);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100216}
217
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500218static void storage_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400219{
220 /* IDE: we map it as in ISA mode */
Alexey Korolev030288f2012-04-19 17:44:55 +1200221 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
222 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
223 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
224 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400225}
226
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400227/* PIIX3/PIIX4 IDE */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500228static void piix_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400229{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400230 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400231 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
232 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400233}
234
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500235static void pic_ibm_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400236{
237 /* PIC, IBM, MPIC & MPIC2 */
Alexey Korolev030288f2012-04-19 17:44:55 +1200238 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400239}
240
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500241static void apple_macio_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400242{
243 /* macio bridge */
Alexey Korolev030288f2012-04-19 17:44:55 +1200244 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400245}
246
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200247static void piix4_pm_config_setup(u16 bdf)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400248{
249 // acpi sci is hardwired to 9
250 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
251
Paolo Bonzini40d03122014-05-15 13:22:26 +0200252 pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
253 pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
254 pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
255 pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200256}
257
258static int PiixPmBDF = -1;
259
260/* PIIX4 Power Management device (for ACPI) */
261static void piix4_pm_setup(struct pci_device *pci, void *arg)
262{
263 PiixPmBDF = pci->bdf;
264 piix4_pm_config_setup(pci->bdf);
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200265
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200266 acpi_pm1a_cnt = acpi_pm_base + 0x04;
267 pmtimer_setup(acpi_pm_base + 0x08);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400268}
269
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200270static void ich9_smbus_enable(u16 bdf)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100271{
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100272 /* map smbus into io space */
273 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
Gerd Hoffmanna217de92014-05-13 14:01:22 +0200274 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100275
276 /* enable SMBus */
277 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
278}
279
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200280static int ICH9SmbusBDF = -1;
281
282/* ICH9 SMBUS */
283/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
284static void ich9_smbus_setup(struct pci_device *dev, void *arg)
285{
286 ICH9SmbusBDF = dev->bdf;
287
288 ich9_smbus_enable(dev->bdf);
289}
290
Alex Williamson04259c52016-05-17 14:44:32 -0600291static void intel_igd_setup(struct pci_device *dev, void *arg)
292{
293 struct romfile_s *opregion = romfile_find("etc/igd-opregion");
294 u64 bdsm_size = le64_to_cpu(romfile_loadint("etc/igd-bdsm-size", 0));
295 void *addr;
296 u16 bdf = dev->bdf;
297
298 /* Apply OpRegion to any Intel VGA device, more than one is undefined */
299 if (opregion && opregion->size) {
300 addr = memalign_high(PAGE_SIZE, opregion->size);
301 if (!addr) {
302 warn_noalloc();
303 return;
304 }
305
306 if (opregion->copy(opregion, addr, opregion->size) < 0) {
307 free(addr);
308 return;
309 }
310
311 pci_config_writel(bdf, 0xFC, cpu_to_le32((u32)addr));
312
313 dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev "
314 "%02x:%02x.%x\n", (u32)addr, opregion->size >> 10,
315 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
316 }
317
318 /* Apply BDSM only to Intel VGA at 00:02.0 */
319 if (bdsm_size && (bdf == pci_to_bdf(0, 2, 0))) {
320 addr = memalign_tmphigh(1024 * 1024, bdsm_size);
321 if (!addr) {
322 warn_noalloc();
323 return;
324 }
325
326 e820_add((u32)addr, bdsm_size, E820_RESERVED);
327
328 pci_config_writel(bdf, 0x5C, cpu_to_le32((u32)addr));
329
330 dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %lldMB, dev "
331 "00:02.0\n", (u32)addr, bdsm_size >> 20);
332 }
333}
334
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400335static const struct pci_device_id pci_device_tbl[] = {
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500336 /* PIIX3/PIIX4 PCI to ISA bridge */
337 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500338 piix_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500339 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500340 piix_isa_bridge_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100341 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500342 mch_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500343
344 /* STORAGE IDE */
345 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500346 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500347 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500348 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500349 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500350 storage_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500351
Cao jine518c0f2016-01-30 15:50:38 +0800352 /* PIC, IBM, MPIC & MPIC2 */
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500353 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500354 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500355 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500356 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500357
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400358 /* PIIX4 Power Management device (for ACPI) */
359 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500360 piix4_pm_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100361 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500362 ich9_smbus_setup),
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400363
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500364 /* 0xff00 */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500365 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
366 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500367
Alex Williamson04259c52016-05-17 14:44:32 -0600368 /* Intel IGD OpRegion setup */
369 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
370 intel_igd_setup),
371
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400372 PCI_DEVICE_END,
373};
374
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200375static int MCHMmcfgBDF = -1;
376static void mch_mmconfig_setup(u16 bdf);
377
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200378void pci_resume(void)
379{
380 if (!CONFIG_QEMU) {
381 return;
382 }
383
384 if (PiixPmBDF >= 0) {
385 piix4_pm_config_setup(PiixPmBDF);
386 }
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200387
388 if (ICH9LpcBDF >= 0) {
389 mch_isa_lpc_setup(ICH9LpcBDF);
390 }
391
392 if (ICH9SmbusBDF >= 0) {
393 ich9_smbus_enable(ICH9SmbusBDF);
394 }
395
396 if(MCHMmcfgBDF >= 0) {
397 mch_mmconfig_setup(MCHMmcfgBDF);
398 }
Marcel Apfelbaum40d020f2014-01-15 14:20:06 +0200399}
400
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400401static void pci_bios_init_device(struct pci_device *pci)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400402{
Kevin O'Connor7b673002016-02-03 03:03:15 -0500403 dprintf(1, "PCI: init bdf=%pP id=%04x:%04x\n"
404 , pci, pci->vendor, pci->device);
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400405
Kevin O'Connor0525d292008-07-04 06:18:30 -0400406 /* map the interrupt */
Kevin O'Connor7b673002016-02-03 03:03:15 -0500407 u16 bdf = pci->bdf;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400408 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
409 if (pin != 0)
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200410 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
Kevin O'Connor0525d292008-07-04 06:18:30 -0400411
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400412 pci_init_device(pci_device_tbl, pci, NULL);
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500413
414 /* enable memory mappings */
Isaku Yamahatad146ab82012-11-28 10:17:32 +0100415 pci_config_maskw(bdf, PCI_COMMAND, 0,
416 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
Chen Fan32ec3ee2015-01-28 16:05:13 +0800417 /* enable SERR# for forwarding */
418 if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
419 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
420 PCI_BRIDGE_CTL_SERR);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400421}
422
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400423static void pci_bios_init_devices(void)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900424{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400425 struct pci_device *pci;
426 foreachpci(pci) {
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400427 pci_bios_init_device(pci);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900428 }
429}
430
Alex Williamson7adfd712013-03-20 10:58:47 -0600431static void pci_enable_default_vga(void)
432{
433 struct pci_device *pci;
434
435 foreachpci(pci) {
436 if (is_pci_vga(pci)) {
Kevin O'Connor7b673002016-02-03 03:03:15 -0500437 dprintf(1, "PCI: Using %pP for primary VGA\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600438 return;
439 }
440 }
441
442 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
443 if (!pci) {
444 dprintf(1, "PCI: No VGA devices found\n");
445 return;
446 }
447
Kevin O'Connor7b673002016-02-03 03:03:15 -0500448 dprintf(1, "PCI: Enabling %pP for primary VGA\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600449
450 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
451 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
452
453 while (pci->parent) {
454 pci = pci->parent;
455
Kevin O'Connor7b673002016-02-03 03:03:15 -0500456 dprintf(1, "PCI: Setting VGA enable on bridge %pP\n", pci);
Alex Williamson7adfd712013-03-20 10:58:47 -0600457
458 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
459 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
460 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
461 }
462}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400463
464/****************************************************************
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500465 * Platform device initialization
466 ****************************************************************/
467
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500468static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500469{
470 if (RamSize <= 0x80000000)
471 pcimem_start = 0x80000000;
472 else if (RamSize <= 0xc0000000)
473 pcimem_start = 0xc0000000;
Alex Williamsonb9490402013-02-15 14:11:41 -0700474
475 pci_slot_get_irq = piix_pci_slot_get_irq;
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500476}
477
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200478static void mch_mmconfig_setup(u16 bdf)
479{
480 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
481 u32 upper = addr >> 32;
482 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
483 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
484 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
485 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
486}
487
Kevin O'Connor9a79b912014-01-15 11:08:22 -0500488static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100489{
490 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
491 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
492
493 /* setup mmconfig */
Marcel Apfelbaumdce99e02016-03-01 16:06:45 +0200494 MCHMmcfgBDF = dev->bdf;
495 mch_mmconfig_setup(dev->bdf);
Kevin O'Connorc167e542015-09-29 09:40:46 -0400496 e820_add(addr, size, E820_RESERVED);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100497
498 /* setup pci i/o window (above mmconfig) */
499 pcimem_start = addr + size;
Alex Williamsonb9490402013-02-15 14:11:41 -0700500
501 pci_slot_get_irq = mch_pci_slot_get_irq;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200502
503 /* setup io address space */
504 if (acpi_pm_base < 0x1000)
505 pci_io_low_end = 0x10000;
506 else
507 pci_io_low_end = acpi_pm_base;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100508}
509
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500510static const struct pci_device_id pci_platform_tbl[] = {
511 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500512 i440fx_mem_addr_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100513 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500514 mch_mem_addr_setup),
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500515 PCI_DEVICE_END
516};
517
518static void pci_bios_init_platform(void)
519{
520 struct pci_device *pci;
521 foreachpci(pci) {
522 pci_init_device(pci_platform_tbl, pci, NULL);
523 }
524}
525
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300526static u8 pci_find_resource_reserve_capability(u16 bdf)
527{
528 if (pci_config_readw(bdf, PCI_VENDOR_ID) == PCI_VENDOR_ID_REDHAT &&
529 pci_config_readw(bdf, PCI_DEVICE_ID) ==
530 PCI_DEVICE_ID_REDHAT_ROOT_PORT) {
531 u8 cap = 0;
532 do {
533 cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap);
534 } while (cap &&
535 pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) !=
536 REDHAT_CAP_RESOURCE_RESERVE);
537 if (cap) {
538 u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS);
539 if (cap_len < RES_RESERVE_CAP_SIZE) {
540 dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n",
541 cap_len);
Jing Liu2c455cc2018-08-24 16:52:59 +0800542 return 0;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300543 }
Jing Liu478bc3e2018-08-24 16:53:00 +0800544 } else {
545 dprintf(1, "PCI: QEMU resource reserve cap not found\n");
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300546 }
547 return cap;
548 } else {
Jing Liu478bc3e2018-08-24 16:53:00 +0800549 dprintf(1, "PCI: QEMU resource reserve cap VID or DID doesn't match.\n");
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300550 return 0;
551 }
552}
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500553
554/****************************************************************
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400555 * Bus initialization
556 ****************************************************************/
557
Isaku Yamahataf4416662010-06-22 17:57:52 +0900558static void
559pci_bios_init_bus_rec(int bus, u8 *pci_bus)
560{
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400561 int bdf;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900562 u16 class;
563
564 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
565
566 /* prevent accidental access to unintended devices */
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400567 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900568 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
569 if (class == PCI_CLASS_BRIDGE_PCI) {
570 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
571 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
572 }
573 }
574
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400575 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900576 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
577 if (class != PCI_CLASS_BRIDGE_PCI) {
578 continue;
579 }
580 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
581
582 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
583 if (pribus != bus) {
584 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
585 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
586 } else {
587 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
588 }
589
590 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
591 (*pci_bus)++;
592 if (*pci_bus != secbus) {
593 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
594 secbus, *pci_bus);
595 secbus = *pci_bus;
596 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
597 } else {
598 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
599 }
600
601 /* set to max for access to all subordinate buses.
602 later set it to accurate value */
603 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
604 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
605
606 pci_bios_init_bus_rec(secbus, pci_bus);
607
608 if (subbus != *pci_bus) {
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300609 u8 res_bus = *pci_bus;
610 u8 cap = pci_find_resource_reserve_capability(bdf);
611
612 if (cap) {
613 u32 tmp_res_bus = pci_config_readl(bdf,
614 cap + RES_RESERVE_BUS_RES);
615 if (tmp_res_bus != (u32)-1) {
616 res_bus = tmp_res_bus & 0xFF;
617 if ((u8)(res_bus + secbus) < secbus ||
618 (u8)(res_bus + secbus) < res_bus) {
619 dprintf(1, "PCI: bus_reserve value %d is invalid\n",
620 res_bus);
621 res_bus = 0;
622 }
Marcel Apfelbaum14d91c32018-01-11 22:15:12 +0200623 if (secbus + res_bus > *pci_bus) {
624 dprintf(1, "PCI: QEMU resource reserve cap: bus = %u\n",
625 res_bus);
626 res_bus = secbus + res_bus;
627 }
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300628 }
629 }
Isaku Yamahataf4416662010-06-22 17:57:52 +0900630 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300631 subbus, res_bus);
632 subbus = res_bus;
633 *pci_bus = res_bus;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900634 } else {
635 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
636 }
637 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
638 }
639}
640
641static void
642pci_bios_init_bus(void)
643{
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200644 u8 extraroots = romfile_loadint("etc/extra-pci-roots", 0);
Isaku Yamahataf4416662010-06-22 17:57:52 +0900645 u8 pci_bus = 0;
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200646
Isaku Yamahataf4416662010-06-22 17:57:52 +0900647 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
Marcel Apfelbaum5cc7eec2015-02-16 19:29:19 +0200648
649 if (extraroots) {
650 while (pci_bus < 0xff) {
651 pci_bus++;
652 pci_bios_init_bus_rec(pci_bus, &pci_bus);
653 }
654 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200655}
656
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400657
658/****************************************************************
659 * Bus sizing
660 ****************************************************************/
661
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400662static void
Alexey Korolev030288f2012-04-19 17:44:55 +1200663pci_bios_get_bar(struct pci_device *pci, int bar,
664 int *ptype, u64 *psize, int *pis64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200665{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400666 u32 ofs = pci_bar(pci, bar);
667 u16 bdf = pci->bdf;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200668 u32 old = pci_config_readl(bdf, ofs);
Alexey Korolev030288f2012-04-19 17:44:55 +1200669 int is64 = 0, type = PCI_REGION_TYPE_MEM;
670 u64 mask;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200671
672 if (bar == PCI_ROM_SLOT) {
673 mask = PCI_ROM_ADDRESS_MASK;
674 pci_config_writel(bdf, ofs, mask);
675 } else {
Alexey Korolev030288f2012-04-19 17:44:55 +1200676 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200677 mask = PCI_BASE_ADDRESS_IO_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200678 type = PCI_REGION_TYPE_IO;
679 } else {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200680 mask = PCI_BASE_ADDRESS_MEM_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200681 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
682 type = PCI_REGION_TYPE_PREFMEM;
683 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
684 == PCI_BASE_ADDRESS_MEM_TYPE_64);
685 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200686 pci_config_writel(bdf, ofs, ~0);
687 }
Alexey Korolev030288f2012-04-19 17:44:55 +1200688 u64 val = pci_config_readl(bdf, ofs);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200689 pci_config_writel(bdf, ofs, old);
Alexey Korolev030288f2012-04-19 17:44:55 +1200690 if (is64) {
691 u32 hold = pci_config_readl(bdf, ofs + 4);
692 pci_config_writel(bdf, ofs + 4, ~0);
693 u32 high = pci_config_readl(bdf, ofs + 4);
694 pci_config_writel(bdf, ofs + 4, hold);
695 val |= ((u64)high << 32);
696 mask |= ((u64)0xffffffff << 32);
697 *psize = (~(val & mask)) + 1;
698 } else {
699 *psize = ((~(val & mask)) + 1) & 0xffffffff;
700 }
701 *ptype = type;
702 *pis64 = is64;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200703}
704
Alexey Korolevac0cd582012-04-19 17:48:54 +1200705static int pci_bios_bridge_region_is64(struct pci_region *r,
706 struct pci_device *pci, int type)
707{
708 if (type != PCI_REGION_TYPE_PREFMEM)
709 return 0;
710 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
711 if (!pmem) {
712 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
713 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
714 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
715 }
716 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
717 return 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400718 struct pci_region_entry *entry;
719 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolevac0cd582012-04-19 17:48:54 +1200720 if (!entry->is64)
721 return 0;
Alexey Korolevac0cd582012-04-19 17:48:54 +1200722 }
723 return 1;
724}
725
Alexey Korolev37c111f2012-04-26 16:51:05 +1200726static u64 pci_region_align(struct pci_region *r)
727{
Kevin O'Connora88c1972013-06-08 21:51:46 -0400728 struct pci_region_entry *entry;
729 hlist_for_each_entry(entry, &r->list, node) {
730 // The first entry in the sorted list has the largest alignment
731 return entry->align;
732 }
733 return 1;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200734}
735
736static u64 pci_region_sum(struct pci_region *r)
737{
Alexey Korolev37c111f2012-04-26 16:51:05 +1200738 u64 sum = 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400739 struct pci_region_entry *entry;
740 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolev37c111f2012-04-26 16:51:05 +1200741 sum += entry->size;
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400742 }
743 return sum;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200744}
745
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200746static void pci_region_migrate_64bit_entries(struct pci_region *from,
747 struct pci_region *to)
748{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400749 struct hlist_node *n, **last = &to->list.first;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400750 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400751 hlist_for_each_entry_safe(entry, n, &from->list, node) {
Kevin O'Connora88c1972013-06-08 21:51:46 -0400752 if (!entry->is64)
Kevin O'Connord630d142012-04-26 22:20:56 -0400753 continue;
Gerd Hoffmanna247e672013-11-26 12:57:19 +0100754 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
755 continue;
Kevin O'Connord630d142012-04-26 22:20:56 -0400756 // Move from source list to destination list.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400757 hlist_del(&entry->node);
758 hlist_add(&entry->node, last);
Gerd Hoffmann95c5afc2013-11-26 11:21:23 +0100759 last = &entry->node.next;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200760 }
761}
762
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200763static struct pci_region_entry *
764pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
Alexey Korolev030288f2012-04-19 17:44:55 +1200765 int bar, u64 size, u64 align, int type, int is64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200766{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200767 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
768 if (!entry) {
769 warn_noalloc();
770 return NULL;
771 }
772 memset(entry, 0, sizeof(*entry));
773 entry->dev = dev;
774 entry->bar = bar;
775 entry->size = size;
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400776 entry->align = align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200777 entry->is64 = is64;
778 entry->type = type;
779 // Insert into list in sorted order.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400780 struct hlist_node **pprev;
781 struct pci_region_entry *pos;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400782 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400783 if (pos->align < align || (pos->align == align && pos->size < size))
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200784 break;
785 }
Kevin O'Connora88c1972013-06-08 21:51:46 -0400786 hlist_add(&entry->node, pprev);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200787 return entry;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200788}
789
Marcel Apfelbaum76327b92015-12-07 14:05:14 +0200790static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300791{
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300792 u8 shpc_cap;
793
794 if (pcie_cap) {
795 u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf,
796 pcie_cap + PCI_EXP_FLAGS);
797 u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >>
798 (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1));
799 u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) ||
800 (port_type == PCI_EXP_TYPE_ROOT_PORT);
801 /*
802 * PCI Express SPEC, 7.8.2:
803 * Slot Implemented – When Set, this bit indicates that the Link
804 * HwInit associated with this Port is connected to a slot (as
805 * compared to being connected to a system-integrated device or
806 * being disabled).
807 * This bit is valid for Downstream Ports. This bit is undefined
808 * for Upstream Ports.
809 */
810 u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT;
811
812 return downstream_port && slot_implemented;
813 }
814
Aleksandr Bezzubikov7de1f652017-08-18 02:33:19 +0300815 shpc_cap = pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0);
Marcel Apfelbaum3aa31d72014-06-23 18:29:51 +0300816 return !!shpc_cap;
817}
818
Kevin O'Connor62ff9d52016-02-03 00:47:27 -0500819/* Test whether bridge support forwarding of transactions
820 * of a specific type.
821 * Note: disables bridge's window registers as a side effect.
822 */
823static int pci_bridge_has_region(struct pci_device *pci,
824 enum pci_region_type region_type)
825{
826 u8 base;
827
828 switch (region_type) {
829 case PCI_REGION_TYPE_IO:
830 base = PCI_IO_BASE;
831 break;
832 case PCI_REGION_TYPE_PREFMEM:
833 base = PCI_PREF_MEMORY_BASE;
834 break;
835 default:
836 /* Regular memory support is mandatory */
837 return 1;
838 }
839
840 pci_config_writeb(pci->bdf, base, 0xFF);
841
842 return pci_config_readb(pci->bdf, base) != 0;
843}
844
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200845static int pci_bios_check_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200846{
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400847 dprintf(1, "PCI: check devices\n");
848
849 // Calculate resources needed for regular (non-bus) devices.
850 struct pci_device *pci;
851 foreachpci(pci) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200852 if (pci->class == PCI_CLASS_BRIDGE_PCI)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400853 busses[pci->secondary_bus].bus_dev = pci;
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200854
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400855 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
Marcel Apfelbaum0fe4c9e2015-02-16 19:29:20 +0200856 if (!bus->bus_dev)
857 /*
858 * Resources for all root busses go in busses[0]
859 */
860 bus = &busses[0];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400861 int i;
862 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200863 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
864 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
865 continue;
Alexey Korolev030288f2012-04-19 17:44:55 +1200866 int type, is64;
867 u64 size;
868 pci_bios_get_bar(pci, i, &type, &size, &is64);
869 if (size == 0)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400870 continue;
871
Alexey Korolev5fa24b52012-04-18 17:31:58 +1200872 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
873 size = PCI_DEVICE_MEM_MIN;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200874 struct pci_region_entry *entry = pci_region_create_entry(
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400875 bus, pci, i, size, size, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200876 if (!entry)
877 return -1;
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400878
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200879 if (is64)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400880 i++;
881 }
882 }
883
884 // Propagate required bus resources to parent busses.
885 int secondary_bus;
886 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
887 struct pci_bus *s = &busses[secondary_bus];
888 if (!s->bus_dev)
889 continue;
890 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
Marcel Apfelbaum0fe4c9e2015-02-16 19:29:20 +0200891 if (!parent->bus_dev)
892 /*
893 * Resources for all root busses go in busses[0]
894 */
895 parent = &busses[0];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400896 int type;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300897 u16 bdf = s->bus_dev->bdf;
898 u8 pcie_cap = pci_find_capability(bdf, PCI_CAP_ID_EXP, 0);
899 u8 qemu_cap = pci_find_resource_reserve_capability(bdf);
900
Marcel Apfelbaum76327b92015-12-07 14:05:14 +0200901 int hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200902 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Alexey Korolev030288f2012-04-19 17:44:55 +1200903 u64 align = (type == PCI_REGION_TYPE_IO) ?
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200904 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
Marcel Apfelbaum0784d042014-04-10 21:55:22 +0300905 if (!pci_bridge_has_region(s->bus_dev, type))
906 continue;
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300907 u64 size = 0;
908 if (qemu_cap) {
909 u32 tmp_size;
910 u64 tmp_size_64;
911 switch(type) {
912 case PCI_REGION_TYPE_IO:
913 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO) |
914 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO + 4) << 32);
915 if (tmp_size_64 != (u64)-1) {
916 size = tmp_size_64;
917 }
918 break;
919 case PCI_REGION_TYPE_MEM:
920 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_MEM);
921 if (tmp_size != (u32)-1) {
922 size = tmp_size;
923 }
924 break;
925 case PCI_REGION_TYPE_PREFMEM:
926 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_32);
927 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64) |
928 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64 + 4) << 32);
929 if (tmp_size != (u32)-1 && tmp_size_64 == (u64)-1) {
930 size = tmp_size;
931 } else if (tmp_size == (u32)-1 && tmp_size_64 != (u64)-1) {
932 size = tmp_size_64;
933 } else if (tmp_size != (u32)-1 && tmp_size_64 != (u64)-1) {
934 dprintf(1, "PCI: resource reserve cap PREF32 and PREF64"
935 " conflict\n");
936 }
937 break;
938 default:
939 break;
940 }
941 }
Alexey Korolev37c111f2012-04-26 16:51:05 +1200942 if (pci_region_align(&s->r[type]) > align)
943 align = pci_region_align(&s->r[type]);
944 u64 sum = pci_region_sum(&s->r[type]);
Marcel Apfelbaum76327b92015-12-07 14:05:14 +0200945 int resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
946 if (!sum && hotplug_support && !resource_optional)
Marcel Apfelbaumc6e298e2014-04-10 21:55:21 +0300947 sum = align; /* reserve min size for hot-plug */
Aleksandr Bezzubikovec6cb172017-08-18 02:33:21 +0300948 if (size > sum) {
949 dprintf(1, "PCI: QEMU resource reserve cap: "
950 "size %08llx type %s\n",
951 size, region_type_name[type]);
952 if (type != PCI_REGION_TYPE_IO) {
953 size = ALIGN(size, align);
954 }
955 } else {
956 size = ALIGN(sum, align);
957 }
Alexey Korolevac0cd582012-04-19 17:48:54 +1200958 int is64 = pci_bios_bridge_region_is64(&s->r[type],
959 s->bus_dev, type);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200960 // entry->bar is -1 if the entry represents a bridge region
961 struct pci_region_entry *entry = pci_region_create_entry(
Alexey Korolevac0cd582012-04-19 17:48:54 +1200962 parent, s->bus_dev, -1, size, align, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200963 if (!entry)
964 return -1;
Alexey Korolev030288f2012-04-19 17:44:55 +1200965 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
Alexey Korolevf3c2b062012-04-18 17:26:43 +1200966 entry->dev->secondary_bus, size,
967 region_type_name[entry->type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200968 }
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400969 }
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200970 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400971}
972
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400973
974/****************************************************************
975 * BAR assignment
976 ****************************************************************/
977
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400978// Setup region bases (given the regions' size and alignment)
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100979static int pci_bios_init_root_regions_io(struct pci_bus *bus)
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400980{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100981 /*
982 * QEMU I/O address space usage:
983 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
984 * 1000 - 9fff free
985 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
986 * b000 - bfff power management (PORT_ACPI_PM_BASE)
987 * [ qemu 1.4+ implements pci config registers
988 * properly so guests can place the registers
989 * where they want, on older versions its fixed ]
990 * c000 - ffff free, traditionally used for pci io
991 */
992 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
993 u64 sum = pci_region_sum(r_io);
994 if (sum < 0x4000) {
995 /* traditional region is big enougth, use it */
996 r_io->base = 0xc000;
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +0200997 } else if (sum < pci_io_low_end - 0x1000) {
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +0100998 /* use the larger region at 0x1000 */
999 r_io->base = 0x1000;
1000 } else {
Gerd Hoffmann7eac0c42014-05-13 14:09:00 +02001001 /* not enouth io address space -> error out */
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001002 return -1;
1003 }
1004 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
1005 return 0;
1006}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001007
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001008static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
1009{
Alexey Korolev37c111f2012-04-26 16:51:05 +12001010 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
1011 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
1012
1013 if (pci_region_align(r_start) < pci_region_align(r_end)) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -04001014 // Swap regions to improve alignment.
Alexey Korolev37c111f2012-04-26 16:51:05 +12001015 r_end = r_start;
1016 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001017 }
Alexey Korolev37c111f2012-04-26 16:51:05 +12001018 u64 sum = pci_region_sum(r_end);
1019 u64 align = pci_region_align(r_end);
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +02001020 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
Alexey Korolev37c111f2012-04-26 16:51:05 +12001021 sum = pci_region_sum(r_start);
1022 align = pci_region_align(r_start);
1023 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
1024
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +02001025 if ((r_start->base < pcimem_start) ||
1026 (r_start->base > pcimem_end))
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -04001027 // Memory range requested is larger than available.
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001028 return -1;
1029 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001030}
1031
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001032#define PCI_IO_SHIFT 8
1033#define PCI_MEMORY_SHIFT 16
1034#define PCI_PREF_MEMORY_SHIFT 16
1035
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001036static void
Alexey Korolev35a770f2012-04-19 17:47:19 +12001037pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001038{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001039 if (entry->bar >= 0) {
Kevin O'Connor7b673002016-02-03 03:03:15 -05001040 dprintf(1, "PCI: map device bdf=%pP"
Alexey Korolev030288f2012-04-19 17:44:55 +12001041 " bar %d, addr %08llx, size %08llx [%s]\n",
Kevin O'Connor7b673002016-02-03 03:03:15 -05001042 entry->dev,
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001043 entry->bar, addr, entry->size, region_type_name[entry->type]);
1044
Alexey Korolev030288f2012-04-19 17:44:55 +12001045 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
Alexey Korolev3a297162012-04-18 17:22:29 +12001046 return;
1047 }
1048
Kevin O'Connor7b673002016-02-03 03:03:15 -05001049 u16 bdf = entry->dev->bdf;
Alexey Korolev030288f2012-04-19 17:44:55 +12001050 u64 limit = addr + entry->size - 1;
Alexey Korolev3a297162012-04-18 17:22:29 +12001051 if (entry->type == PCI_REGION_TYPE_IO) {
1052 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
1053 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
1054 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
1055 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
1056 }
1057 if (entry->type == PCI_REGION_TYPE_MEM) {
1058 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
1059 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
1060 }
1061 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
1062 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
1063 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
Alexey Korolev030288f2012-04-19 17:44:55 +12001064 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
1065 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001066 }
1067}
1068
Alexey Korolev35a770f2012-04-19 17:47:19 +12001069static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
1070{
Kevin O'Connor030a58a2013-06-13 21:24:14 -04001071 struct hlist_node *n;
Kevin O'Connora88c1972013-06-08 21:51:46 -04001072 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -04001073 hlist_for_each_entry_safe(entry, n, &r->list, node) {
Alexey Korolev35a770f2012-04-19 17:47:19 +12001074 u64 addr = r->base;
1075 r->base += entry->size;
1076 if (entry->bar == -1)
1077 // Update bus base address if entry is a bridge region
1078 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
1079 pci_region_map_one_entry(entry, addr);
Kevin O'Connora88c1972013-06-08 21:51:46 -04001080 hlist_del(&entry->node);
Alexey Korolev35a770f2012-04-19 17:47:19 +12001081 free(entry);
Alexey Korolev35a770f2012-04-19 17:47:19 +12001082 }
1083}
1084
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001085static void pci_bios_map_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001086{
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001087 if (pci_bios_init_root_regions_io(busses))
1088 panic("PCI: out of I/O address space\n");
1089
Gerd Hoffmannc72370e2013-11-26 12:51:30 +01001090 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001091 if (pci_bios_init_root_regions_mem(busses)) {
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001092 struct pci_region r64_mem, r64_pref;
Kevin O'Connora88c1972013-06-08 21:51:46 -04001093 r64_mem.list.first = NULL;
1094 r64_pref.list.first = NULL;
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001095 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
1096 &r64_mem);
1097 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
1098 &r64_pref);
1099
Gerd Hoffmannfc3cd002014-01-23 15:48:19 +01001100 if (pci_bios_init_root_regions_mem(busses))
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001101 panic("PCI: out of 32bit address space\n");
1102
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001103 u64 sum_mem = pci_region_sum(&r64_mem);
1104 u64 sum_pref = pci_region_sum(&r64_pref);
1105 u64 align_mem = pci_region_align(&r64_mem);
1106 u64 align_pref = pci_region_align(&r64_pref);
1107
Gerd Hoffmann0f474d02013-11-26 12:48:20 +01001108 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
1109 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
1110 r64_mem.base = 0x100000000LL + RamSizeOver4G;
Gerd Hoffmannf21c0062013-11-26 11:08:17 +01001111 r64_mem.base = ALIGN(r64_mem.base, align_mem);
1112 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
1113 r64_pref.base = r64_mem.base + sum_mem;
1114 r64_pref.base = ALIGN(r64_pref.base, align_pref);
1115 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001116 pcimem64_start = r64_mem.base;
1117 pcimem64_end = r64_pref.base + sum_pref;
Gerd Hoffmannf21c0062013-11-26 11:08:17 +01001118 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
Gerd Hoffmannc72370e2013-11-26 12:51:30 +01001119 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001120
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001121 pci_region_map_entries(busses, &r64_mem);
1122 pci_region_map_entries(busses, &r64_pref);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +02001123 } else {
1124 // no bars mapped high -> drop 64bit window (see dsdt)
1125 pcimem64_start = 0;
Alexey Koroleve5e5f962012-04-26 17:01:59 +12001126 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -04001127 // Map regions on each device.
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001128 int bus;
1129 for (bus = 0; bus<=MaxPCIBus; bus++) {
1130 int type;
Alexey Korolev35a770f2012-04-19 17:47:19 +12001131 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
1132 pci_region_map_entries(busses, &busses[bus].r[type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001133 }
1134}
1135
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001136
Kevin O'Connor5bab7e62011-10-01 11:33:31 -04001137/****************************************************************
1138 * Main setup code
1139 ****************************************************************/
Isaku Yamahataf4416662010-06-22 17:57:52 +09001140
Kevin O'Connor0525d292008-07-04 06:18:30 -04001141void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -04001142pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -04001143{
Kevin O'Connora2a86e22013-02-13 19:35:12 -05001144 if (!CONFIG_QEMU)
Kevin O'Connor0525d292008-07-04 06:18:30 -04001145 return;
1146
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -04001147 dprintf(3, "pci setup\n");
1148
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001149 dprintf(1, "=== PCI bus & bridge init ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +02001150 if (pci_probe_host() != 0) {
1151 return;
1152 }
Isaku Yamahataf4416662010-06-22 17:57:52 +09001153 pci_bios_init_bus();
1154
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001155 dprintf(1, "=== PCI device probing ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +02001156 pci_probe_devices();
Kevin O'Connor37956dd2011-06-21 22:22:58 -04001157
Kevin O'Connorb1c35f22012-11-26 11:05:32 -05001158 pcimem_start = RamSize;
1159 pci_bios_init_platform();
1160
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001161 dprintf(1, "=== PCI new allocation pass #1 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001162 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connor28a20e12011-10-15 11:07:30 -04001163 if (!busses) {
1164 warn_noalloc();
1165 return;
1166 }
1167 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
Alexey Korolevfa51bcd2012-04-18 17:21:19 +12001168 if (pci_bios_check_devices(busses))
1169 return;
1170
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001171 dprintf(1, "=== PCI new allocation pass #2 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -04001172 pci_bios_map_devices(busses);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001173
Kevin O'Connor3f2288f2011-10-15 12:02:14 -04001174 pci_bios_init_devices();
Gerd Hoffmann8e301472011-08-09 17:22:42 +02001175
Gerd Hoffmann82b39b22011-07-11 09:20:28 +02001176 free(busses);
Alex Williamson7adfd712013-03-20 10:58:47 -06001177
1178 pci_enable_default_vga();
Kevin O'Connor0525d292008-07-04 06:18:30 -04001179}