| Kevin O'Connor | 1fcf144 | 2008-03-11 19:42:41 -0400 | [diff] [blame] | 1 | // Global defines -- ATA register and register bits. |
| 2 | // command block & control block regs |
| 3 | #define ATA_CB_DATA 0 // data reg in/out pio_base_addr1+0 |
| 4 | #define ATA_CB_ERR 1 // error in pio_base_addr1+1 |
| 5 | #define ATA_CB_FR 1 // feature reg out pio_base_addr1+1 |
| 6 | #define ATA_CB_SC 2 // sector count in/out pio_base_addr1+2 |
| 7 | #define ATA_CB_SN 3 // sector number in/out pio_base_addr1+3 |
| 8 | #define ATA_CB_CL 4 // cylinder low in/out pio_base_addr1+4 |
| 9 | #define ATA_CB_CH 5 // cylinder high in/out pio_base_addr1+5 |
| 10 | #define ATA_CB_DH 6 // device head in/out pio_base_addr1+6 |
| 11 | #define ATA_CB_STAT 7 // primary status in pio_base_addr1+7 |
| 12 | #define ATA_CB_CMD 7 // command out pio_base_addr1+7 |
| 13 | #define ATA_CB_ASTAT 6 // alternate status in pio_base_addr2+6 |
| 14 | #define ATA_CB_DC 6 // device control out pio_base_addr2+6 |
| 15 | #define ATA_CB_DA 7 // device address in pio_base_addr2+7 |
| 16 | |
| 17 | #define ATA_CB_ER_ICRC 0x80 // ATA Ultra DMA bad CRC |
| 18 | #define ATA_CB_ER_BBK 0x80 // ATA bad block |
| 19 | #define ATA_CB_ER_UNC 0x40 // ATA uncorrected error |
| 20 | #define ATA_CB_ER_MC 0x20 // ATA media change |
| 21 | #define ATA_CB_ER_IDNF 0x10 // ATA id not found |
| 22 | #define ATA_CB_ER_MCR 0x08 // ATA media change request |
| 23 | #define ATA_CB_ER_ABRT 0x04 // ATA command aborted |
| 24 | #define ATA_CB_ER_NTK0 0x02 // ATA track 0 not found |
| 25 | #define ATA_CB_ER_NDAM 0x01 // ATA address mark not found |
| 26 | |
| 27 | #define ATA_CB_ER_P_SNSKEY 0xf0 // ATAPI sense key (mask) |
| 28 | #define ATA_CB_ER_P_MCR 0x08 // ATAPI Media Change Request |
| 29 | #define ATA_CB_ER_P_ABRT 0x04 // ATAPI command abort |
| 30 | #define ATA_CB_ER_P_EOM 0x02 // ATAPI End of Media |
| 31 | #define ATA_CB_ER_P_ILI 0x01 // ATAPI Illegal Length Indication |
| 32 | |
| 33 | // ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC) |
| 34 | #define ATA_CB_SC_P_TAG 0xf8 // ATAPI tag (mask) |
| 35 | #define ATA_CB_SC_P_REL 0x04 // ATAPI release |
| 36 | #define ATA_CB_SC_P_IO 0x02 // ATAPI I/O |
| 37 | #define ATA_CB_SC_P_CD 0x01 // ATAPI C/D |
| 38 | |
| 39 | // bits 7-4 of the device/head (CB_DH) reg |
| 40 | #define ATA_CB_DH_DEV0 0xa0 // select device 0 |
| 41 | #define ATA_CB_DH_DEV1 0xb0 // select device 1 |
| 42 | #define ATA_CB_DH_LBA 0x40 // use LBA |
| 43 | |
| 44 | // status reg (CB_STAT and CB_ASTAT) bits |
| 45 | #define ATA_CB_STAT_BSY 0x80 // busy |
| 46 | #define ATA_CB_STAT_RDY 0x40 // ready |
| 47 | #define ATA_CB_STAT_DF 0x20 // device fault |
| 48 | #define ATA_CB_STAT_WFT 0x20 // write fault (old name) |
| 49 | #define ATA_CB_STAT_SKC 0x10 // seek complete |
| 50 | #define ATA_CB_STAT_SERV 0x10 // service |
| 51 | #define ATA_CB_STAT_DRQ 0x08 // data request |
| 52 | #define ATA_CB_STAT_CORR 0x04 // corrected |
| 53 | #define ATA_CB_STAT_IDX 0x02 // index |
| 54 | #define ATA_CB_STAT_ERR 0x01 // error (ATA) |
| 55 | #define ATA_CB_STAT_CHK 0x01 // check (ATAPI) |
| 56 | |
| 57 | // device control reg (CB_DC) bits |
| 58 | #define ATA_CB_DC_HD15 0x08 // bit should always be set to one |
| 59 | #define ATA_CB_DC_SRST 0x04 // soft reset |
| 60 | #define ATA_CB_DC_NIEN 0x02 // disable interrupts |
| 61 | |
| 62 | // Most mandtory and optional ATA commands (from ATA-3), |
| 63 | #define ATA_CMD_CFA_ERASE_SECTORS 0xC0 |
| 64 | #define ATA_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03 |
| 65 | #define ATA_CMD_CFA_TRANSLATE_SECTOR 0x87 |
| 66 | #define ATA_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD |
| 67 | #define ATA_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38 |
| 68 | #define ATA_CMD_CHECK_POWER_MODE1 0xE5 |
| 69 | #define ATA_CMD_CHECK_POWER_MODE2 0x98 |
| 70 | #define ATA_CMD_DEVICE_RESET 0x08 |
| 71 | #define ATA_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90 |
| 72 | #define ATA_CMD_FLUSH_CACHE 0xE7 |
| 73 | #define ATA_CMD_FORMAT_TRACK 0x50 |
| 74 | #define ATA_CMD_IDENTIFY_DEVICE 0xEC |
| 75 | #define ATA_CMD_IDENTIFY_DEVICE_PACKET 0xA1 |
| 76 | #define ATA_CMD_IDENTIFY_PACKET_DEVICE 0xA1 |
| 77 | #define ATA_CMD_IDLE1 0xE3 |
| 78 | #define ATA_CMD_IDLE2 0x97 |
| 79 | #define ATA_CMD_IDLE_IMMEDIATE1 0xE1 |
| 80 | #define ATA_CMD_IDLE_IMMEDIATE2 0x95 |
| 81 | #define ATA_CMD_INITIALIZE_DRIVE_PARAMETERS 0x91 |
| 82 | #define ATA_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91 |
| 83 | #define ATA_CMD_NOP 0x00 |
| 84 | #define ATA_CMD_PACKET 0xA0 |
| 85 | #define ATA_CMD_READ_BUFFER 0xE4 |
| 86 | #define ATA_CMD_READ_DMA 0xC8 |
| 87 | #define ATA_CMD_READ_DMA_QUEUED 0xC7 |
| 88 | #define ATA_CMD_READ_MULTIPLE 0xC4 |
| 89 | #define ATA_CMD_READ_SECTORS 0x20 |
| 90 | #define ATA_CMD_READ_VERIFY_SECTORS 0x40 |
| 91 | #define ATA_CMD_RECALIBRATE 0x10 |
| 92 | #define ATA_CMD_REQUEST_SENSE 0x03 |
| 93 | #define ATA_CMD_SEEK 0x70 |
| 94 | #define ATA_CMD_SET_FEATURES 0xEF |
| 95 | #define ATA_CMD_SET_MULTIPLE_MODE 0xC6 |
| 96 | #define ATA_CMD_SLEEP1 0xE6 |
| 97 | #define ATA_CMD_SLEEP2 0x99 |
| 98 | #define ATA_CMD_STANDBY1 0xE2 |
| 99 | #define ATA_CMD_STANDBY2 0x96 |
| 100 | #define ATA_CMD_STANDBY_IMMEDIATE1 0xE0 |
| 101 | #define ATA_CMD_STANDBY_IMMEDIATE2 0x94 |
| 102 | #define ATA_CMD_WRITE_BUFFER 0xE8 |
| 103 | #define ATA_CMD_WRITE_DMA 0xCA |
| 104 | #define ATA_CMD_WRITE_DMA_QUEUED 0xCC |
| 105 | #define ATA_CMD_WRITE_MULTIPLE 0xC5 |
| 106 | #define ATA_CMD_WRITE_SECTORS 0x30 |
| 107 | #define ATA_CMD_WRITE_VERIFY 0x3C |