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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
8#include "util.h" // dprintf
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -05009#include "pci.h" // pci_config_readl
Kevin O'Connor9521e262008-07-04 13:04:29 -040010#include "biosvar.h" // GET_EBDA
Kevin O'Connor2ed2f582008-11-08 15:53:36 -050011#include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12#include "pci_regs.h" // PCI_COMMAND
Ian Campbell74c78782011-06-01 11:00:29 +010013#include "xen.h" // usingXen
Kevin O'Connor0525d292008-07-04 06:18:30 -040014
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020015#define PCI_IO_INDEX_SHIFT 2
16#define PCI_MEM_INDEX_SHIFT 12
Kevin O'Connor0525d292008-07-04 06:18:30 -040017
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020018#define PCI_BRIDGE_IO_MIN 0x1000
19#define PCI_BRIDGE_MEM_MIN 0x100000
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090020
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020021enum pci_region_type {
22 PCI_REGION_TYPE_IO,
23 PCI_REGION_TYPE_MEM,
24 PCI_REGION_TYPE_PREFMEM,
25 PCI_REGION_TYPE_COUNT,
26};
27
28static const char *region_type_name[] = {
29 [ PCI_REGION_TYPE_IO ] = "io",
30 [ PCI_REGION_TYPE_MEM ] = "mem",
31 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
32};
33
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040034struct pci_bus {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020035 struct {
36 /* pci region stats */
37 u32 count[32 - PCI_MEM_INDEX_SHIFT];
38 u32 sum, max;
39 /* seconday bus region sizes */
40 u32 size;
41 /* pci region assignments */
42 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
43 u32 base;
44 } r[PCI_REGION_TYPE_COUNT];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -040045 struct pci_device *bus_dev;
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040046};
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020047
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020048static int pci_size_to_index(u32 size, enum pci_region_type type)
49{
50 int index = __fls(size);
51 int shift = (type == PCI_REGION_TYPE_IO) ?
52 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
53
54 if (index < shift)
55 index = shift;
56 index -= shift;
57 return index;
58}
59
60static u32 pci_index_to_size(int index, enum pci_region_type type)
61{
62 int shift = (type == PCI_REGION_TYPE_IO) ?
63 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
64
65 return 0x1 << (index + shift);
66}
67
68static enum pci_region_type pci_addr_to_type(u32 addr)
69{
70 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
71 return PCI_REGION_TYPE_IO;
72 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
73 return PCI_REGION_TYPE_PREFMEM;
74 return PCI_REGION_TYPE_MEM;
75}
76
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040077static u32 pci_bar(struct pci_device *pci, int region_num)
Isaku Yamahataa65821d2010-06-22 17:57:50 +090078{
79 if (region_num != PCI_ROM_SLOT) {
80 return PCI_BASE_ADDRESS_0 + region_num * 4;
81 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090082
83#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040084 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
Isaku Yamahata5d0de152010-06-22 17:57:51 +090085 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090086}
87
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040088static void
89pci_set_io_region_addr(struct pci_device *pci, int region_num, u32 addr)
Kevin O'Connor0525d292008-07-04 06:18:30 -040090{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040091 pci_config_writel(pci->bdf, pci_bar(pci, region_num), addr);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090092}
93
Kevin O'Connor5bab7e62011-10-01 11:33:31 -040094
95/****************************************************************
96 * Misc. device init
97 ****************************************************************/
98
99/* host irqs corresponding to PCI irqs A-D */
100const u8 pci_irqs[4] = {
101 10, 10, 11, 11
102};
103
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400104// Return the global irq number corresponding to a host bus device irq pin.
105static int pci_slot_get_irq(u16 bdf, int pin)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400106{
Kevin O'Connorbe19cdc2008-11-09 15:33:47 -0500107 int slot_addend = pci_bdf_to_dev(bdf) - 1;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400108 return pci_irqs[(pin - 1 + slot_addend) & 3];
Kevin O'Connor0525d292008-07-04 06:18:30 -0400109}
110
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400111/* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400112static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400113{
114 int i, irq;
115 u8 elcr[2];
116
117 elcr[0] = 0x00;
118 elcr[1] = 0x00;
119 for (i = 0; i < 4; i++) {
120 irq = pci_irqs[i];
121 /* set to trigger level */
122 elcr[irq >> 3] |= (1 << (irq & 7));
123 /* activate irq remapping in PIIX */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400124 pci_config_writeb(pci->bdf, 0x60 + i, irq);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400125 }
126 outb(elcr[0], 0x4d0);
127 outb(elcr[1], 0x4d1);
128 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
129}
130
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400131static const struct pci_device_id pci_isa_bridge_tbl[] = {
132 /* PIIX3/PIIX4 PCI to ISA bridge */
133 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
134 piix_isa_bridge_init),
135 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
136 piix_isa_bridge_init),
Kevin O'Connor0525d292008-07-04 06:18:30 -0400137
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400138 PCI_DEVICE_END
139};
Kevin O'Connor0525d292008-07-04 06:18:30 -0400140
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400141static void storage_ide_init(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400142{
143 /* IDE: we map it as in ISA mode */
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400144 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE);
145 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE);
146 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE);
147 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400148}
149
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400150/* PIIX3/PIIX4 IDE */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400151static void piix_ide_init(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400152{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400153 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400154 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
155 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400156}
157
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400158static void pic_ibm_init(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400159{
160 /* PIC, IBM, MPIC & MPIC2 */
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400161 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400162}
163
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400164static void apple_macio_init(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400165{
166 /* macio bridge */
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400167 pci_set_io_region_addr(pci, 0, 0x80800000);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400168}
169
170static const struct pci_device_id pci_class_tbl[] = {
171 /* STORAGE IDE */
172 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
173 PCI_CLASS_STORAGE_IDE, piix_ide_init),
174 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
175 PCI_CLASS_STORAGE_IDE, piix_ide_init),
176 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
177 storage_ide_init),
178
179 /* PIC, IBM, MIPC & MPIC2 */
180 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
181 pic_ibm_init),
182 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
183 pic_ibm_init),
184
185 /* 0xff00 */
186 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
187 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
188
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400189 PCI_DEVICE_END,
190};
191
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400192/* PIIX4 Power Management device (for ACPI) */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400193static void piix4_pm_init(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400194{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400195 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400196 // acpi sci is hardwired to 9
197 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
198
199 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
200 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
201 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
202 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
203}
204
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400205static const struct pci_device_id pci_device_tbl[] = {
206 /* PIIX4 Power Management device (for ACPI) */
207 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
208 piix4_pm_init),
209
210 PCI_DEVICE_END,
211};
212
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400213static void pci_bios_init_device(struct pci_device *pci)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400214{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400215 u16 bdf = pci->bdf;
Kevin O'Connor99e37c42011-10-01 10:47:21 -0400216 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
217 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400218 , pci->vendor, pci->device);
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400219
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400220 pci_init_device(pci_class_tbl, pci, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400221
Kevin O'Connorb82a1e42009-10-12 10:34:51 -0400222 /* enable memory mappings */
223 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
224
Kevin O'Connor0525d292008-07-04 06:18:30 -0400225 /* map the interrupt */
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400226 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
227 if (pin != 0)
228 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(bdf, pin));
Kevin O'Connor0525d292008-07-04 06:18:30 -0400229
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400230 pci_init_device(pci_device_tbl, pci, NULL);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400231}
232
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400233static void pci_bios_init_devices(void)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900234{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400235 struct pci_device *pci;
236 foreachpci(pci) {
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400237 if (pci_bdf_to_bus(pci->bdf) != 0)
238 // Only init devices on host bus.
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400239 break;
240 pci_bios_init_device(pci);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900241 }
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400242
243 foreachpci(pci) {
244 pci_init_device(pci_isa_bridge_tbl, pci, NULL);
245 }
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900246}
247
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400248
249/****************************************************************
250 * Bus initialization
251 ****************************************************************/
252
Isaku Yamahataf4416662010-06-22 17:57:52 +0900253static void
254pci_bios_init_bus_rec(int bus, u8 *pci_bus)
255{
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400256 int bdf;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900257 u16 class;
258
259 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
260
261 /* prevent accidental access to unintended devices */
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400262 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900263 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
264 if (class == PCI_CLASS_BRIDGE_PCI) {
265 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
266 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
267 }
268 }
269
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400270 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900271 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
272 if (class != PCI_CLASS_BRIDGE_PCI) {
273 continue;
274 }
275 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
276
277 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
278 if (pribus != bus) {
279 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
280 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
281 } else {
282 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
283 }
284
285 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
286 (*pci_bus)++;
287 if (*pci_bus != secbus) {
288 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
289 secbus, *pci_bus);
290 secbus = *pci_bus;
291 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
292 } else {
293 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
294 }
295
296 /* set to max for access to all subordinate buses.
297 later set it to accurate value */
298 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
299 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
300
301 pci_bios_init_bus_rec(secbus, pci_bus);
302
303 if (subbus != *pci_bus) {
304 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
305 subbus, *pci_bus);
306 subbus = *pci_bus;
307 } else {
308 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
309 }
310 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
311 }
312}
313
314static void
315pci_bios_init_bus(void)
316{
317 u8 pci_bus = 0;
318 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200319}
320
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400321
322/****************************************************************
323 * Bus sizing
324 ****************************************************************/
325
326static u32 pci_size_roundup(u32 size)
327{
328 int index = __fls(size-1)+1;
329 return 0x1 << index;
330}
331
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400332static void
333pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200334{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400335 u32 ofs = pci_bar(pci, bar);
336 u16 bdf = pci->bdf;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200337 u32 old = pci_config_readl(bdf, ofs);
338 u32 mask;
339
340 if (bar == PCI_ROM_SLOT) {
341 mask = PCI_ROM_ADDRESS_MASK;
342 pci_config_writel(bdf, ofs, mask);
343 } else {
344 if (old & PCI_BASE_ADDRESS_SPACE_IO)
345 mask = PCI_BASE_ADDRESS_IO_MASK;
346 else
347 mask = PCI_BASE_ADDRESS_MEM_MASK;
348 pci_config_writel(bdf, ofs, ~0);
349 }
350 *val = pci_config_readl(bdf, ofs);
351 pci_config_writel(bdf, ofs, old);
352 *size = (~(*val & mask)) + 1;
353}
354
355static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
356{
357 u32 index;
358
359 index = pci_size_to_index(size, type);
360 size = pci_index_to_size(index, type);
361 bus->r[type].count[index]++;
362 bus->r[type].sum += size;
363 if (bus->r[type].max < size)
364 bus->r[type].max = size;
365}
366
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400367static void pci_bios_check_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200368{
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400369 dprintf(1, "PCI: check devices\n");
370
371 // Calculate resources needed for regular (non-bus) devices.
372 struct pci_device *pci;
373 foreachpci(pci) {
374 if (pci->class == PCI_CLASS_BRIDGE_PCI) {
375 busses[pci->secondary_bus].bus_dev = pci;
376 continue;
377 }
378 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
379 int i;
380 for (i = 0; i < PCI_NUM_REGIONS; i++) {
381 u32 val, size;
382 pci_bios_get_bar(pci, i, &val, &size);
383 if (val == 0)
384 continue;
385
386 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
387 pci->bars[i].addr = val;
388 pci->bars[i].size = size;
389 pci->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
390 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
391 == PCI_BASE_ADDRESS_MEM_TYPE_64);
392
393 if (pci->bars[i].is64)
394 i++;
395 }
396 }
397
398 // Propagate required bus resources to parent busses.
399 int secondary_bus;
400 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
401 struct pci_bus *s = &busses[secondary_bus];
402 if (!s->bus_dev)
403 continue;
404 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400405 int type;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200406 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400407 u32 limit = (type == PCI_REGION_TYPE_IO) ?
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200408 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
409 s->r[type].size = s->r[type].sum;
410 if (s->r[type].size < limit)
411 s->r[type].size = limit;
412 s->r[type].size = pci_size_roundup(s->r[type].size);
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400413 pci_bios_bus_reserve(parent, type, s->r[type].size);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200414 }
415 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400416 secondary_bus,
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200417 s->r[PCI_REGION_TYPE_IO].size,
418 s->r[PCI_REGION_TYPE_MEM].size,
419 s->r[PCI_REGION_TYPE_PREFMEM].size);
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400420 }
421}
422
423#define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
424
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400425// Setup region bases (given the regions' size and alignment)
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400426static int pci_bios_init_root_regions(struct pci_bus *bus, u32 start, u32 end)
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400427{
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400428 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
429
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400430 int reg1 = PCI_REGION_TYPE_PREFMEM, reg2 = PCI_REGION_TYPE_MEM;
431 if (bus->r[reg1].sum < bus->r[reg2].sum) {
432 // Swap regions so larger area is more likely to align well.
433 reg1 = PCI_REGION_TYPE_MEM;
434 reg2 = PCI_REGION_TYPE_PREFMEM;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400435 }
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400436 bus->r[reg2].base = ROOT_BASE(end, bus->r[reg2].sum, bus->r[reg2].max);
437 bus->r[reg1].base = ROOT_BASE(bus->r[reg2].base, bus->r[reg1].sum
438 , bus->r[reg1].max);
439 if (bus->r[reg1].base < start)
440 // Memory range requested is larger than available.
441 return -1;
442 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400443}
444
445
446/****************************************************************
447 * BAR assignment
448 ****************************************************************/
449
450static void pci_bios_init_bus_bases(struct pci_bus *bus)
451{
452 u32 base, newbase, size;
453 int type, i;
454
455 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
456 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
457 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
458 base = bus->r[type].base;
459 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
460 size = pci_index_to_size(i, type);
461 if (!bus->r[type].count[i])
462 continue;
463 newbase = base + size * bus->r[type].count[i];
464 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
465 size, bus->r[type].count[i], base, newbase - 1);
466 bus->r[type].bases[i] = base;
467 base = newbase;
468 }
469 }
470}
471
472static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
473{
474 u32 index, addr;
475
476 index = pci_size_to_index(size, type);
477 addr = bus->r[type].bases[index];
478 bus->r[type].bases[index] += pci_index_to_size(index, type);
479 return addr;
480}
481
482#define PCI_IO_SHIFT 8
483#define PCI_MEMORY_SHIFT 16
484#define PCI_PREF_MEMORY_SHIFT 16
485
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400486static void pci_bios_map_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200487{
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400488 // Setup bases for root bus.
489 dprintf(1, "PCI: init bases bus 0 (primary)\n");
490 pci_bios_init_bus_bases(&busses[0]);
491
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400492 // Map regions on each secondary bus.
493 int secondary_bus;
494 for (secondary_bus=1; secondary_bus<=MaxPCIBus; secondary_bus++) {
495 struct pci_bus *s = &busses[secondary_bus];
496 if (!s->bus_dev)
497 continue;
498 u16 bdf = s->bus_dev->bdf;
499 struct pci_bus *parent = &busses[pci_bdf_to_bus(bdf)];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400500 int type;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200501 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400502 s->r[type].base = pci_bios_bus_get_addr(
503 parent, type, s->r[type].size);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200504 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400505 dprintf(1, "PCI: init bases bus %d (secondary)\n", secondary_bus);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200506 pci_bios_init_bus_bases(s);
Gerd Hoffmann01a5c882011-07-11 09:20:29 +0200507
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400508 u32 base = s->r[PCI_REGION_TYPE_IO].base;
509 u32 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
Gerd Hoffmann01a5c882011-07-11 09:20:29 +0200510 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
511 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
512 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
513 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
514
515 base = s->r[PCI_REGION_TYPE_MEM].base;
516 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
517 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
518 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
519
520 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
521 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
522 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
523 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
524 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
525 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200526 }
527
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400528 // Map regions on each device.
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200529 struct pci_device *pci;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200530 foreachpci(pci) {
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400531 if (pci->class == PCI_CLASS_BRIDGE_PCI)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200532 continue;
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400533 u16 bdf = pci->bdf;
Kevin O'Connor99e37c42011-10-01 10:47:21 -0400534 dprintf(1, "PCI: map device bdf=%02x:%02x.%x\n"
535 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400536 struct pci_bus *bus = &busses[pci_bdf_to_bus(bdf)];
537 int i;
538 for (i = 0; i < PCI_NUM_REGIONS; i++) {
539 if (pci->bars[i].addr == 0)
540 continue;
541
542 int type = pci_addr_to_type(pci->bars[i].addr);
543 u32 addr = pci_bios_bus_get_addr(bus, type, pci->bars[i].size);
544 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
545 i, addr, pci->bars[i].size, region_type_name[type]);
546 pci_set_io_region_addr(pci, i, addr);
547
Kevin O'Connor139d5ac2011-12-30 16:36:16 -0500548 if (pci->bars[i].is64) {
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400549 i++;
Kevin O'Connor139d5ac2011-12-30 16:36:16 -0500550 pci_set_io_region_addr(pci, i, 0);
551 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400552 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200553 }
554}
555
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200556
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400557/****************************************************************
558 * Main setup code
559 ****************************************************************/
Isaku Yamahataf4416662010-06-22 17:57:52 +0900560
Kevin O'Connor0525d292008-07-04 06:18:30 -0400561void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400562pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400563{
Kevin O'Connor37956dd2011-06-21 22:22:58 -0400564 if (CONFIG_COREBOOT || usingXen()) {
565 // PCI setup already done by coreboot or Xen - just do probe.
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200566 pci_probe_devices();
Kevin O'Connor0525d292008-07-04 06:18:30 -0400567 return;
Kevin O'Connor37956dd2011-06-21 22:22:58 -0400568 }
Kevin O'Connor0525d292008-07-04 06:18:30 -0400569
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400570 dprintf(3, "pci setup\n");
571
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200572 u32 start = BUILD_PCIMEM_START;
Gerd Hoffmann60a348b2011-07-11 09:20:31 +0200573 u32 end = BUILD_PCIMEM_END;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200574
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200575 dprintf(1, "=== PCI bus & bridge init ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200576 if (pci_probe_host() != 0) {
577 return;
578 }
Isaku Yamahataf4416662010-06-22 17:57:52 +0900579 pci_bios_init_bus();
580
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200581 dprintf(1, "=== PCI device probing ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200582 pci_probe_devices();
Kevin O'Connor37956dd2011-06-21 22:22:58 -0400583
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200584 dprintf(1, "=== PCI new allocation pass #1 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400585 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connor28a20e12011-10-15 11:07:30 -0400586 if (!busses) {
587 warn_noalloc();
588 return;
589 }
590 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400591 pci_bios_check_devices(busses);
592 if (pci_bios_init_root_regions(&busses[0], start, end) != 0) {
Gerd Hoffmann01a5c882011-07-11 09:20:29 +0200593 panic("PCI: out of address space\n");
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200594 }
595
596 dprintf(1, "=== PCI new allocation pass #2 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400597 pci_bios_map_devices(busses);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200598
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400599 pci_bios_init_devices();
Gerd Hoffmann8e301472011-08-09 17:22:42 +0200600
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200601 free(busses);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400602}