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Kevin O'Connor59f02832009-10-12 10:09:15 -04001#ifndef __USB_OHCI_H
2#define __USB_OHCI_H
3
4// usb-ohci.c
5struct usb_s;
Kevin O'Connora5826b52009-10-24 17:57:29 -04006void ohci_init(void *data);
Kevin O'Connor357bdfa2010-02-26 08:57:13 -05007struct usb_pipe;
8void ohci_free_pipe(struct usb_pipe *p);
9struct usb_pipe *ohci_alloc_control_pipe(u32 endp);
10int ohci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
Kevin O'Connor59f02832009-10-12 10:09:15 -040011 , void *data, int datasize);
Kevin O'Connor991eaff2010-02-13 21:51:47 -050012struct usb_pipe *ohci_alloc_intr_pipe(u32 endp, int frameexp);
Kevin O'Connor1c46a542009-10-17 23:53:32 -040013int ohci_poll_intr(struct usb_pipe *pipe, void *data);
Kevin O'Connor59f02832009-10-12 10:09:15 -040014
15
16/****************************************************************
17 * ohci structs and flags
18 ****************************************************************/
19
20struct ohci_ed {
21 u32 hwINFO;
22 u32 hwTailP;
23 u32 hwHeadP;
24 u32 hwNextED;
25} PACKED;
26
27#define ED_ISO (1 << 15)
28#define ED_SKIP (1 << 14)
29#define ED_LOWSPEED (1 << 13)
30#define ED_OUT (0x01 << 11)
31#define ED_IN (0x02 << 11)
32
33#define ED_C (0x02)
34#define ED_H (0x01)
35
36struct ohci_td {
37 u32 hwINFO;
38 u32 hwCBP;
39 u32 hwNextTD;
40 u32 hwBE;
41} PACKED;
42
43#define TD_CC 0xf0000000
44#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
45#define TD_DI 0x00E00000
Kevin O'Connor59f02832009-10-12 10:09:15 -040046
47#define TD_DONE 0x00020000
48#define TD_ISO 0x00010000
49
50#define TD_EC 0x0C000000
51#define TD_T 0x03000000
52#define TD_T_DATA0 0x02000000
53#define TD_T_DATA1 0x03000000
54#define TD_T_TOGGLE 0x00000000
55#define TD_DP 0x00180000
56#define TD_DP_SETUP 0x00000000
57#define TD_DP_IN 0x00100000
58#define TD_DP_OUT 0x00080000
59
60#define TD_R 0x00040000
61
62struct ohci_hcca {
63 u32 int_table[32];
64 u32 frame_no;
65 u32 done_head;
66 u8 reserved[120];
67} PACKED;
68
69struct ohci_regs {
70 u32 revision;
71 u32 control;
72 u32 cmdstatus;
73 u32 intrstatus;
74 u32 intrenable;
75 u32 intrdisable;
76
77 u32 hcca;
78 u32 ed_periodcurrent;
79 u32 ed_controlhead;
80 u32 ed_controlcurrent;
81 u32 ed_bulkhead;
82 u32 ed_bulkcurrent;
83 u32 donehead;
84
85 u32 fminterval;
86 u32 fmremaining;
87 u32 fmnumber;
88 u32 periodicstart;
89 u32 lsthresh;
90
91 u32 roothub_a;
92 u32 roothub_b;
93 u32 roothub_status;
94 u32 roothub_portstatus[15];
95} PACKED;
96
Kevin O'Connor1c46a542009-10-17 23:53:32 -040097#define OHCI_CTRL_CBSR (3 << 0)
98#define OHCI_CTRL_PLE (1 << 2)
99#define OHCI_CTRL_CLE (1 << 4)
Kevin O'Connor357bdfa2010-02-26 08:57:13 -0500100#define OHCI_CTRL_BLE (1 << 5)
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400101#define OHCI_CTRL_HCFS (3 << 6)
102# define OHCI_USB_RESET (0 << 6)
103# define OHCI_USB_OPER (2 << 6)
104#define OHCI_CTRL_RWC (1 << 9)
105
106#define OHCI_HCR (1 << 0)
107#define OHCI_CLF (1 << 1)
108
Kevin O'Connor59f02832009-10-12 10:09:15 -0400109#define OHCI_INTR_MIE (1 << 31)
110
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400111#define RH_PS_CCS 0x00000001
112#define RH_PS_PES 0x00000002
113#define RH_PS_PSS 0x00000004
114#define RH_PS_POCI 0x00000008
115#define RH_PS_PRS 0x00000010
116#define RH_PS_PPS 0x00000100
117#define RH_PS_LSDA 0x00000200
118#define RH_PS_CSC 0x00010000
119#define RH_PS_PESC 0x00020000
120#define RH_PS_PSSC 0x00040000
121#define RH_PS_OCIC 0x00080000
122#define RH_PS_PRSC 0x00100000
123
124#define RH_HS_LPS 0x00000001
125#define RH_HS_OCI 0x00000002
126#define RH_HS_DRWE 0x00008000
127#define RH_HS_LPSC 0x00010000
128#define RH_HS_OCIC 0x00020000
129#define RH_HS_CRWE 0x80000000
130
131#define RH_B_DR 0x0000ffff
132#define RH_B_PPCM 0xffff0000
133
134#define RH_A_NDP (0xff << 0)
135#define RH_A_PSM (1 << 8)
136#define RH_A_NPS (1 << 9)
137#define RH_A_DT (1 << 10)
138#define RH_A_OCPM (1 << 11)
139#define RH_A_NOCP (1 << 12)
140#define RH_A_POTPGT (0xff << 24)
141
Kevin O'Connor59f02832009-10-12 10:09:15 -0400142#endif // usb-ohci.h