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Kevin O'Connore1e000b2011-12-31 03:30:40 -05001#include "vgabios.h" // struct vbe_modeinfo
Kevin O'Connore6bc4c12012-01-21 11:26:37 -05002#include "vbe.h" // VBE_CAPABILITY_8BIT_DAC
Kevin O'Connor5108c692011-12-31 19:13:45 -05003#include "bochsvga.h" // bochsvga_set_mode
4#include "util.h" // dprintf
Kevin O'Connore1e000b2011-12-31 03:30:40 -05005#include "config.h" // CONFIG_*
Kevin O'Connore6bc4c12012-01-21 11:26:37 -05006#include "biosvar.h" // GET_GLOBAL
Kevin O'Connored68e5b2011-12-31 04:15:12 -05007#include "stdvga.h" // VGAREG_SEQU_ADDRESS
Kevin O'Connor97cc3542012-01-14 16:59:21 -05008#include "pci.h" // pci_config_readl
9#include "pci_regs.h" // PCI_BASE_ADDRESS_0
Julian Pidancet87879e22011-12-19 05:08:00 +000010
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050011static struct bochsvga_mode
Julian Pidancet87879e22011-12-19 05:08:00 +000012{
13 u16 mode;
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050014 struct vgamode_s info;
Kevin O'Connorf1e217d2011-12-31 03:18:18 -050015} bochsvga_modes[] VAR16 = {
Julian Pidancet87879e22011-12-19 05:08:00 +000016 /* standard modes */
Kevin O'Connor03776022012-01-21 11:00:11 -050017 { 0x100, { MM_PACKED, 640, 400, 8, 8, 16, SEG_GRAPH } },
18 { 0x101, { MM_PACKED, 640, 480, 8, 8, 16, SEG_GRAPH } },
19 { 0x102, { MM_PLANAR, 800, 600, 4, 8, 16, SEG_GRAPH } },
20 { 0x103, { MM_PACKED, 800, 600, 8, 8, 16, SEG_GRAPH } },
21 { 0x104, { MM_PLANAR, 1024, 768, 4, 8, 16, SEG_GRAPH } },
22 { 0x105, { MM_PACKED, 1024, 768, 8, 8, 16, SEG_GRAPH } },
23 { 0x106, { MM_PLANAR, 1280, 1024, 4, 8, 16, SEG_GRAPH } },
24 { 0x107, { MM_PACKED, 1280, 1024, 8, 8, 16, SEG_GRAPH } },
25 { 0x10D, { MM_DIRECT, 320, 200, 15, 8, 16, SEG_GRAPH } },
26 { 0x10E, { MM_DIRECT, 320, 200, 16, 8, 16, SEG_GRAPH } },
27 { 0x10F, { MM_DIRECT, 320, 200, 24, 8, 16, SEG_GRAPH } },
28 { 0x110, { MM_DIRECT, 640, 480, 15, 8, 16, SEG_GRAPH } },
29 { 0x111, { MM_DIRECT, 640, 480, 16, 8, 16, SEG_GRAPH } },
30 { 0x112, { MM_DIRECT, 640, 480, 24, 8, 16, SEG_GRAPH } },
31 { 0x113, { MM_DIRECT, 800, 600, 15, 8, 16, SEG_GRAPH } },
32 { 0x114, { MM_DIRECT, 800, 600, 16, 8, 16, SEG_GRAPH } },
33 { 0x115, { MM_DIRECT, 800, 600, 24, 8, 16, SEG_GRAPH } },
34 { 0x116, { MM_DIRECT, 1024, 768, 15, 8, 16, SEG_GRAPH } },
35 { 0x117, { MM_DIRECT, 1024, 768, 16, 8, 16, SEG_GRAPH } },
36 { 0x118, { MM_DIRECT, 1024, 768, 24, 8, 16, SEG_GRAPH } },
37 { 0x119, { MM_DIRECT, 1280, 1024, 15, 8, 16, SEG_GRAPH } },
38 { 0x11A, { MM_DIRECT, 1280, 1024, 16, 8, 16, SEG_GRAPH } },
39 { 0x11B, { MM_DIRECT, 1280, 1024, 24, 8, 16, SEG_GRAPH } },
40 { 0x11C, { MM_PACKED, 1600, 1200, 8, 8, 16, SEG_GRAPH } },
41 { 0x11D, { MM_DIRECT, 1600, 1200, 15, 8, 16, SEG_GRAPH } },
42 { 0x11E, { MM_DIRECT, 1600, 1200, 16, 8, 16, SEG_GRAPH } },
43 { 0x11F, { MM_DIRECT, 1600, 1200, 24, 8, 16, SEG_GRAPH } },
Julian Pidancet87879e22011-12-19 05:08:00 +000044 /* BOCHS modes */
Kevin O'Connor03776022012-01-21 11:00:11 -050045 { 0x140, { MM_DIRECT, 320, 200, 32, 8, 16, SEG_GRAPH } },
46 { 0x141, { MM_DIRECT, 640, 400, 32, 8, 16, SEG_GRAPH } },
47 { 0x142, { MM_DIRECT, 640, 480, 32, 8, 16, SEG_GRAPH } },
48 { 0x143, { MM_DIRECT, 800, 600, 32, 8, 16, SEG_GRAPH } },
49 { 0x144, { MM_DIRECT, 1024, 768, 32, 8, 16, SEG_GRAPH } },
50 { 0x145, { MM_DIRECT, 1280, 1024, 32, 8, 16, SEG_GRAPH } },
51 { 0x146, { MM_PACKED, 320, 200, 8, 8, 16, SEG_GRAPH } },
52 { 0x147, { MM_DIRECT, 1600, 1200, 32, 8, 16, SEG_GRAPH } },
53 { 0x148, { MM_PACKED, 1152, 864, 8, 8, 16, SEG_GRAPH } },
54 { 0x149, { MM_DIRECT, 1152, 864, 15, 8, 16, SEG_GRAPH } },
55 { 0x14a, { MM_DIRECT, 1152, 864, 16, 8, 16, SEG_GRAPH } },
56 { 0x14b, { MM_DIRECT, 1152, 864, 24, 8, 16, SEG_GRAPH } },
57 { 0x14c, { MM_DIRECT, 1152, 864, 32, 8, 16, SEG_GRAPH } },
58 { 0x178, { MM_DIRECT, 1280, 800, 16, 8, 16, SEG_GRAPH } },
59 { 0x179, { MM_DIRECT, 1280, 800, 24, 8, 16, SEG_GRAPH } },
60 { 0x17a, { MM_DIRECT, 1280, 800, 32, 8, 16, SEG_GRAPH } },
61 { 0x17b, { MM_DIRECT, 1280, 960, 16, 8, 16, SEG_GRAPH } },
62 { 0x17c, { MM_DIRECT, 1280, 960, 24, 8, 16, SEG_GRAPH } },
63 { 0x17d, { MM_DIRECT, 1280, 960, 32, 8, 16, SEG_GRAPH } },
64 { 0x17e, { MM_DIRECT, 1440, 900, 16, 8, 16, SEG_GRAPH } },
65 { 0x17f, { MM_DIRECT, 1440, 900, 24, 8, 16, SEG_GRAPH } },
66 { 0x180, { MM_DIRECT, 1440, 900, 32, 8, 16, SEG_GRAPH } },
67 { 0x181, { MM_DIRECT, 1400, 1050, 16, 8, 16, SEG_GRAPH } },
68 { 0x182, { MM_DIRECT, 1400, 1050, 24, 8, 16, SEG_GRAPH } },
69 { 0x183, { MM_DIRECT, 1400, 1050, 32, 8, 16, SEG_GRAPH } },
70 { 0x184, { MM_DIRECT, 1680, 1050, 16, 8, 16, SEG_GRAPH } },
71 { 0x185, { MM_DIRECT, 1680, 1050, 24, 8, 16, SEG_GRAPH } },
72 { 0x186, { MM_DIRECT, 1680, 1050, 32, 8, 16, SEG_GRAPH } },
73 { 0x187, { MM_DIRECT, 1920, 1200, 16, 8, 16, SEG_GRAPH } },
74 { 0x188, { MM_DIRECT, 1920, 1200, 24, 8, 16, SEG_GRAPH } },
75 { 0x189, { MM_DIRECT, 1920, 1200, 32, 8, 16, SEG_GRAPH } },
76 { 0x18a, { MM_DIRECT, 2560, 1600, 16, 8, 16, SEG_GRAPH } },
77 { 0x18b, { MM_DIRECT, 2560, 1600, 24, 8, 16, SEG_GRAPH } },
78 { 0x18c, { MM_DIRECT, 2560, 1600, 32, 8, 16, SEG_GRAPH } },
Julian Pidancet87879e22011-12-19 05:08:00 +000079};
80
Kevin O'Connore6bc4c12012-01-21 11:26:37 -050081static int is_bochsvga_mode(struct vgamode_s *vmode_g)
82{
83 return (vmode_g >= &bochsvga_modes[0].info
84 && vmode_g <= &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)-1].info);
85}
86
Julian Pidancet8bd766f2011-12-19 05:08:01 +000087static u16 dispi_get_max_xres(void)
88{
89 u16 en;
90 u16 xres;
91
92 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
93
94 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
95 xres = dispi_read(VBE_DISPI_INDEX_XRES);
96 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
97
98 return xres;
99}
100
101static u16 dispi_get_max_bpp(void)
102{
103 u16 en;
104 u16 bpp;
105
106 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
107
108 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
109 bpp = dispi_read(VBE_DISPI_INDEX_BPP);
110 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
111
112 return bpp;
113}
114
Julian Pidancet87879e22011-12-19 05:08:00 +0000115/* Called only during POST */
116int
Kevin O'Connor161d2012011-12-31 19:42:21 -0500117bochsvga_init(void)
Julian Pidancet87879e22011-12-19 05:08:00 +0000118{
Kevin O'Connor161d2012011-12-31 19:42:21 -0500119 int ret = stdvga_init();
120 if (ret)
121 return ret;
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000122
123 /* Sanity checks */
124 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
125 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
126 dprintf(1, "No VBE DISPI interface detected\n");
127 return -1;
128 }
129
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000130 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
131
Kevin O'Connor8cf8f8e2012-01-16 19:05:27 -0500132 u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
133 int bdf = GET_GLOBAL(VgaBDF);
134 if (CONFIG_VGA_PCI && bdf >= 0)
135 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500136 & PCI_BASE_ADDRESS_MEM_MASK);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000137
Kevin O'Connor3339c052012-01-13 20:00:35 -0500138 SET_VGA(VBE_framebuffer, lfb_addr);
139 u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
140 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
141 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000142
Kevin O'Connor3339c052012-01-13 20:00:35 -0500143 dprintf(1, "VBE DISPI detected. lfb_addr=%x\n", lfb_addr);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000144
145 return 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000146}
147
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500148static int mode_valid(struct vgamode_s *vmode_g)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000149{
150 u16 max_xres = dispi_get_max_xres();
151 u16 max_bpp = dispi_get_max_bpp();
Kevin O'Connor3339c052012-01-13 20:00:35 -0500152 u32 max_mem = GET_GLOBAL(VBE_total_memory);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000153
Kevin O'Connor3339c052012-01-13 20:00:35 -0500154 u16 width = GET_GLOBAL(vmode_g->width);
155 u16 height = GET_GLOBAL(vmode_g->height);
156 u8 depth = GET_GLOBAL(vmode_g->depth);
157 u32 mem = width * height * DIV_ROUND_UP(depth, 8);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000158
Kevin O'Connor3339c052012-01-13 20:00:35 -0500159 return width <= max_xres && depth <= max_bpp && mem <= max_mem;
160}
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000161
Kevin O'Connor3339c052012-01-13 20:00:35 -0500162struct vgamode_s *bochsvga_find_mode(int mode)
163{
164 struct bochsvga_mode *m = bochsvga_modes;
165 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
166 if (GET_GLOBAL(m->mode) == mode) {
167 if (! mode_valid(&m->info))
168 return NULL;
169 return &m->info;
170 }
171 return stdvga_find_mode(mode);
Julian Pidancet87879e22011-12-19 05:08:00 +0000172}
173
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500174void
175bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
Julian Pidancet87879e22011-12-19 05:08:00 +0000176{
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500177 struct bochsvga_mode *m = bochsvga_modes;
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500178 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500179 if (!mode_valid(&m->info))
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000180 continue;
181
182 dprintf(1, "VBE found mode %x valid.\n", GET_GLOBAL(m->mode));
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500183 SET_FARVAR(seg, *dest, GET_GLOBAL(m->mode));
184 dest++;
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000185 }
Julian Pidancet87879e22011-12-19 05:08:00 +0000186
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500187 stdvga_list_modes(seg, dest, last);
Julian Pidancet87879e22011-12-19 05:08:00 +0000188}
189
Kevin O'Connor3339c052012-01-13 20:00:35 -0500190static void
Kevin O'Connorf1e217d2011-12-31 03:18:18 -0500191bochsvga_hires_enable(int enable)
Julian Pidancet87879e22011-12-19 05:08:00 +0000192{
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000193 u16 flags = enable ?
194 VBE_DISPI_ENABLED |
195 VBE_DISPI_LFB_ENABLED |
196 VBE_DISPI_NOCLEARMEM : 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000197
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000198 dispi_write(VBE_DISPI_INDEX_ENABLE, flags);
Julian Pidancet87879e22011-12-19 05:08:00 +0000199}
200
Kevin O'Connor9961f992012-01-21 11:53:44 -0500201int
202bochsvga_get_window(struct vgamode_s *vmode_g, int window)
203{
204 if (window != 0)
205 return -1;
206 return dispi_read(VBE_DISPI_INDEX_BANK);
207}
208
209int
210bochsvga_set_window(struct vgamode_s *vmode_g, int window, int val)
211{
212 if (window != 0)
213 return -1;
214 dispi_write(VBE_DISPI_INDEX_BANK, val);
215 if (dispi_read(VBE_DISPI_INDEX_BANK) != val)
216 return -1;
217 return 0;
218}
219
Kevin O'Connor3876b532012-01-24 00:07:44 -0500220int
221bochsvga_get_linelength(struct vgamode_s *vmode_g)
222{
223 return dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * vga_bpp(vmode_g) / 8;
224}
225
226int
227bochsvga_set_linelength(struct vgamode_s *vmode_g, int val)
228{
229 stdvga_set_linelength(vmode_g, val);
230 int pixels = (val * 8) / vga_bpp(vmode_g);
231 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, pixels);
232 return 0;
233}
234
Kevin O'Connord61fc532012-01-27 20:37:45 -0500235int
236bochsvga_get_displaystart(struct vgamode_s *vmode_g)
237{
238 int bpp = vga_bpp(vmode_g);
239 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
240 int x = dispi_read(VBE_DISPI_INDEX_X_OFFSET);
241 int y = dispi_read(VBE_DISPI_INDEX_Y_OFFSET);
242 return x * bpp / 8 + linelength * y;
243}
244
245int
246bochsvga_set_displaystart(struct vgamode_s *vmode_g, int val)
247{
248 stdvga_set_displaystart(vmode_g, val);
249 int bpp = vga_bpp(vmode_g);
250 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
251 dispi_write(VBE_DISPI_INDEX_X_OFFSET, (val % linelength) * 8 / bpp);
252 dispi_write(VBE_DISPI_INDEX_Y_OFFSET, val / linelength);
253 return 0;
254}
255
Kevin O'Connor3339c052012-01-13 20:00:35 -0500256static void
257bochsvga_clear_scr(void)
258{
259 u16 en;
260
261 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
262 en &= ~VBE_DISPI_NOCLEARMEM;
263 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
264}
265
Kevin O'Connor5108c692011-12-31 19:13:45 -0500266int
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500267bochsvga_set_mode(struct vgamode_s *vmode_g, int flags)
Julian Pidancet87879e22011-12-19 05:08:00 +0000268{
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500269 if (! is_bochsvga_mode(vmode_g)) {
Kevin O'Connor5108c692011-12-31 19:13:45 -0500270 bochsvga_hires_enable(0);
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500271 return stdvga_set_mode(vmode_g, flags);
Kevin O'Connor5108c692011-12-31 19:13:45 -0500272 }
273
Kevin O'Connor5108c692011-12-31 19:13:45 -0500274 bochsvga_hires_enable(1);
275
Kevin O'Connor3339c052012-01-13 20:00:35 -0500276 u8 depth = GET_GLOBAL(vmode_g->depth);
277 if (depth == 4)
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500278 stdvga_set_mode(stdvga_find_mode(0x6a), 0);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500279 if (depth == 8)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000280 // XXX load_dac_palette(3);
281 ;
Julian Pidancet87879e22011-12-19 05:08:00 +0000282
Kevin O'Connor3339c052012-01-13 20:00:35 -0500283 dispi_write(VBE_DISPI_INDEX_BPP, depth);
284 u16 width = GET_GLOBAL(vmode_g->width);
285 u16 height = GET_GLOBAL(vmode_g->height);
286 dispi_write(VBE_DISPI_INDEX_XRES, width);
287 dispi_write(VBE_DISPI_INDEX_YRES, height);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000288 dispi_write(VBE_DISPI_INDEX_BANK, 0);
289
290 /* VGA compat setup */
291 //XXX: This probably needs some reverse engineering
Kevin O'Connor184705f2012-01-14 22:17:43 -0500292 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
293 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
294 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500295 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
Kevin O'Connor184705f2012-01-14 22:17:43 -0500296 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
297 u8 v = 0;
298 if ((height - 1) & 0x0100)
299 v |= 0x02;
300 if ((height - 1) & 0x0200)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000301 v |= 0x40;
Kevin O'Connor184705f2012-01-14 22:17:43 -0500302 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000303
Kevin O'Connor184705f2012-01-14 22:17:43 -0500304 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
305 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
306 stdvga_attr_mask(0x10, 0x00, 0x01);
307 stdvga_grdc_write(0x06, 0x05);
308 stdvga_sequ_write(0x02, 0x0f);
Kevin O'Connor3339c052012-01-13 20:00:35 -0500309 if (depth >= 8) {
Kevin O'Connor184705f2012-01-14 22:17:43 -0500310 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
311 stdvga_attr_mask(0x10, 0x00, 0x40);
312 stdvga_sequ_mask(0x04, 0x00, 0x08);
313 stdvga_grdc_mask(0x05, 0x20, 0x40);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000314 }
315
Kevin O'Connor5108c692011-12-31 19:13:45 -0500316 if (flags & MF_LINEARFB) {
317 /* Linear frame buffer */
318 /* XXX: ??? */
319 }
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500320 if (!(flags & MF_NOCLEARMEM)) {
Kevin O'Connor5108c692011-12-31 19:13:45 -0500321 bochsvga_clear_scr();
322 }
323
324 return 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000325}