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Kevin O'Connor0525d292008-07-04 06:18:30 -04001// Initialize PCI devices (on emulators)
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor0525d292008-07-04 06:18:30 -04007
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04008#include "acpi.h" // acpi_pm1a_cnt
9#include "config.h" // CONFIG_*
10#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
Kevin O'Connor5d369d82013-09-02 20:48:46 -040011#include "hw/pci.h" // pci_config_readl
12#include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
13#include "hw/pci_regs.h" // PCI_COMMAND
Kevin O'Connor4bc49972012-05-13 22:58:08 -040014#include "ioport.h" // PORT_ATA1_CMD_BASE
Kevin O'Connora88c1972013-06-08 21:51:46 -040015#include "list.h" // struct hlist_node
Kevin O'Connor9dea5902013-09-14 20:23:54 -040016#include "malloc.h" // free
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040017#include "memmap.h" // add_e820
18#include "output.h" // dprintf
19#include "paravirt.h" // RamSize
Kevin O'Connorfa9c66a2013-09-14 19:10:40 -040020#include "string.h" // memset
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040021#include "util.h" // pci_setup
Isaku Yamahata72a590e2012-11-28 10:17:33 +010022
Alexey Korolev5fa24b52012-04-18 17:31:58 +120023#define PCI_DEVICE_MEM_MIN 0x1000
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020024#define PCI_BRIDGE_IO_MIN 0x1000
25#define PCI_BRIDGE_MEM_MIN 0x100000
Isaku Yamahataaf0963d2010-06-22 17:57:53 +090026
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020027enum pci_region_type {
28 PCI_REGION_TYPE_IO,
29 PCI_REGION_TYPE_MEM,
30 PCI_REGION_TYPE_PREFMEM,
31 PCI_REGION_TYPE_COUNT,
32};
33
34static const char *region_type_name[] = {
35 [ PCI_REGION_TYPE_IO ] = "io",
36 [ PCI_REGION_TYPE_MEM ] = "mem",
37 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
38};
39
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +020040u64 pcimem_start = BUILD_PCIMEM_START;
41u64 pcimem_end = BUILD_PCIMEM_END;
42u64 pcimem64_start = BUILD_PCIMEM64_START;
43u64 pcimem64_end = BUILD_PCIMEM64_END;
44
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120045struct pci_region_entry {
46 struct pci_device *dev;
47 int bar;
Alexey Korolev030288f2012-04-19 17:44:55 +120048 u64 size;
49 u64 align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120050 int is64;
51 enum pci_region_type type;
Kevin O'Connora88c1972013-06-08 21:51:46 -040052 struct hlist_node node;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +120053};
54
Alexey Korolev35a770f2012-04-19 17:47:19 +120055struct pci_region {
Alexey Korolev35a770f2012-04-19 17:47:19 +120056 /* pci region assignments */
57 u64 base;
Kevin O'Connora88c1972013-06-08 21:51:46 -040058 struct hlist_head list;
Alexey Korolev35a770f2012-04-19 17:47:19 +120059};
60
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040061struct pci_bus {
Alexey Korolev35a770f2012-04-19 17:47:19 +120062 struct pci_region r[PCI_REGION_TYPE_COUNT];
Kevin O'Connor2c4c2112011-10-15 11:42:48 -040063 struct pci_device *bus_dev;
Kevin O'Connorb725dcb2011-10-15 11:53:38 -040064};
Gerd Hoffmann82b39b22011-07-11 09:20:28 +020065
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040066static u32 pci_bar(struct pci_device *pci, int region_num)
Isaku Yamahataa65821d2010-06-22 17:57:50 +090067{
68 if (region_num != PCI_ROM_SLOT) {
69 return PCI_BASE_ADDRESS_0 + region_num * 4;
70 }
Isaku Yamahata5d0de152010-06-22 17:57:51 +090071
72#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040073 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
Isaku Yamahata5d0de152010-06-22 17:57:51 +090074 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
Isaku Yamahataa65821d2010-06-22 17:57:50 +090075}
76
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -040077static void
Alexey Korolev030288f2012-04-19 17:44:55 +120078pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
Kevin O'Connor0525d292008-07-04 06:18:30 -040079{
Alexey Korolev030288f2012-04-19 17:44:55 +120080 u32 ofs = pci_bar(pci, bar);
81 pci_config_writel(pci->bdf, ofs, addr);
82 if (is64)
83 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
Isaku Yamahatab9e47212010-06-22 17:57:47 +090084}
85
Kevin O'Connor5bab7e62011-10-01 11:33:31 -040086
87/****************************************************************
88 * Misc. device init
89 ****************************************************************/
90
91/* host irqs corresponding to PCI irqs A-D */
92const u8 pci_irqs[4] = {
93 10, 10, 11, 11
94};
95
Alex Williamsondbb7a662013-02-21 09:12:23 -070096static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
97{
98 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
99
100 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
101}
102
103static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
104 dummy_pci_slot_get_irq;
Alex Williamsonb9490402013-02-15 14:11:41 -0700105
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400106// Return the global irq number corresponding to a host bus device irq pin.
Alex Williamsonb9490402013-02-15 14:11:41 -0700107static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400108{
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200109 int slot_addend = 0;
110
111 while (pci->parent != NULL) {
112 slot_addend += pci_bdf_to_dev(pci->bdf);
113 pci = pci->parent;
114 }
115 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400116 return pci_irqs[(pin - 1 + slot_addend) & 3];
Kevin O'Connor0525d292008-07-04 06:18:30 -0400117}
118
Alex Williamsonb9490402013-02-15 14:11:41 -0700119static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
120{
121 int irq, slot, pin_addend = 0;
122
123 while (pci->parent != NULL) {
124 pin_addend += pci_bdf_to_dev(pci->bdf);
125 pci = pci->parent;
126 }
127 slot = pci_bdf_to_dev(pci->bdf);
128
129 switch (slot) {
130 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
131 with a different starting index - see q35-acpi-dsdt.dsl */
132 case 0 ... 24:
133 irq = pci_irqs[(pin - 1 + pin_addend + slot) & 3];
134 break;
135 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
136 case 25 ... 31:
137 irq = pci_irqs[(pin - 1 + pin_addend) & 3];
138 break;
139 }
140
141 return irq;
142}
143
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400144/* PIIX3/PIIX4 PCI to ISA bridge */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500145static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400146{
147 int i, irq;
148 u8 elcr[2];
149
150 elcr[0] = 0x00;
151 elcr[1] = 0x00;
152 for (i = 0; i < 4; i++) {
153 irq = pci_irqs[i];
154 /* set to trigger level */
155 elcr[irq >> 3] |= (1 << (irq & 7));
156 /* activate irq remapping in PIIX */
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400157 pci_config_writeb(pci->bdf, 0x60 + i, irq);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400158 }
159 outb(elcr[0], 0x4d0);
160 outb(elcr[1], 0x4d1);
161 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
162}
163
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100164/* ICH9 LPC PCI to ISA bridge */
165/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500166void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100167{
168 u16 bdf = dev->bdf;
169 int i, irq;
170 u8 elcr[2];
171
172 elcr[0] = 0x00;
173 elcr[1] = 0x00;
174
175 for (i = 0; i < 4; i++) {
176 irq = pci_irqs[i];
177 /* set to trigger level */
178 elcr[irq >> 3] |= (1 << (irq & 7));
179
180 /* activate irq remapping in LPC */
181
182 /* PIRQ[A-D] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700183 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100184 /* PIRQ[E-H] routing */
Alex Williamson555a2132013-02-15 14:11:35 -0700185 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100186 }
187 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
188 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
189 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
190
191 /* pm io base */
192 pci_config_writel(bdf, ICH9_LPC_PMBASE,
193 PORT_ACPI_PM_BASE | ICH9_LPC_PMBASE_RTE);
194
195 /* acpi enable, SCI: IRQ9 000b = irq9*/
196 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
197
Gerd Hoffmann5b631092013-07-25 09:47:18 +0200198 acpi_pm1a_cnt = PORT_ACPI_PM_BASE + 0x04;
Kevin O'Connor118605f2013-07-20 11:06:51 -0400199 pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100200}
201
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500202static void storage_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400203{
204 /* IDE: we map it as in ISA mode */
Alexey Korolev030288f2012-04-19 17:44:55 +1200205 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
206 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
207 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
208 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400209}
210
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400211/* PIIX3/PIIX4 IDE */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500212static void piix_ide_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400213{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400214 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400215 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
216 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400217}
218
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500219static void pic_ibm_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400220{
221 /* PIC, IBM, MPIC & MPIC2 */
Alexey Korolev030288f2012-04-19 17:44:55 +1200222 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400223}
224
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500225static void apple_macio_setup(struct pci_device *pci, void *arg)
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400226{
227 /* macio bridge */
Alexey Korolev030288f2012-04-19 17:44:55 +1200228 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400229}
230
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400231/* PIIX4 Power Management device (for ACPI) */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500232static void piix4_pm_setup(struct pci_device *pci, void *arg)
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400233{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400234 u16 bdf = pci->bdf;
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400235 // acpi sci is hardwired to 9
236 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
237
238 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
239 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
240 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
241 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
Gerd Hoffmann455a7c82012-09-06 08:01:00 +0200242
Gerd Hoffmann5b631092013-07-25 09:47:18 +0200243 acpi_pm1a_cnt = PORT_ACPI_PM_BASE + 0x04;
Kevin O'Connor118605f2013-07-20 11:06:51 -0400244 pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
Kevin O'Connor6e4583c2011-06-19 10:09:26 -0400245}
246
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100247/* ICH9 SMBUS */
248/* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500249void ich9_smbus_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100250{
251 u16 bdf = dev->bdf;
252 /* map smbus into io space */
253 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
254 PORT_SMB_BASE | PCI_BASE_ADDRESS_SPACE_IO);
255
256 /* enable SMBus */
257 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
258}
259
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400260static const struct pci_device_id pci_device_tbl[] = {
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500261 /* PIIX3/PIIX4 PCI to ISA bridge */
262 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500263 piix_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500264 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500265 piix_isa_bridge_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100266 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500267 mch_isa_bridge_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500268
269 /* STORAGE IDE */
270 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500271 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500272 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500273 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500274 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500275 storage_ide_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500276
277 /* PIC, IBM, MIPC & MPIC2 */
278 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500279 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500280 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500281 pic_ibm_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500282
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400283 /* PIIX4 Power Management device (for ACPI) */
284 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500285 piix4_pm_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100286 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500287 ich9_smbus_setup),
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400288
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500289 /* 0xff00 */
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500290 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
291 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500292
Kevin O'Connor0d6b8d52010-07-10 13:12:37 -0400293 PCI_DEVICE_END,
294};
295
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400296static void pci_bios_init_device(struct pci_device *pci)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400297{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400298 u16 bdf = pci->bdf;
Kevin O'Connor99e37c42011-10-01 10:47:21 -0400299 dprintf(1, "PCI: init bdf=%02x:%02x.%x id=%04x:%04x\n"
300 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf)
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400301 , pci->vendor, pci->device);
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400302
Kevin O'Connor0525d292008-07-04 06:18:30 -0400303 /* map the interrupt */
Kevin O'Connor0ce21382011-10-01 14:52:35 -0400304 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
305 if (pin != 0)
Gerd Hoffmann0c8f58d2012-05-04 17:33:36 +0200306 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
Kevin O'Connor0525d292008-07-04 06:18:30 -0400307
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400308 pci_init_device(pci_device_tbl, pci, NULL);
Kevin O'Connor31dcfb02012-11-20 20:29:26 -0500309
310 /* enable memory mappings */
Isaku Yamahatad146ab82012-11-28 10:17:32 +0100311 pci_config_maskw(bdf, PCI_COMMAND, 0,
312 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
Kevin O'Connor0525d292008-07-04 06:18:30 -0400313}
314
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400315static void pci_bios_init_devices(void)
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900316{
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400317 struct pci_device *pci;
318 foreachpci(pci) {
Kevin O'Connor278b19f2011-06-21 22:41:15 -0400319 pci_bios_init_device(pci);
Isaku Yamahataaf0963d2010-06-22 17:57:53 +0900320 }
321}
322
Alex Williamson7adfd712013-03-20 10:58:47 -0600323static void pci_enable_default_vga(void)
324{
325 struct pci_device *pci;
326
327 foreachpci(pci) {
328 if (is_pci_vga(pci)) {
329 dprintf(1, "PCI: Using %02x:%02x.%x for primary VGA\n",
330 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
331 pci_bdf_to_fn(pci->bdf));
332 return;
333 }
334 }
335
336 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
337 if (!pci) {
338 dprintf(1, "PCI: No VGA devices found\n");
339 return;
340 }
341
342 dprintf(1, "PCI: Enabling %02x:%02x.%x for primary VGA\n",
343 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
344 pci_bdf_to_fn(pci->bdf));
345
346 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
347 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
348
349 while (pci->parent) {
350 pci = pci->parent;
351
352 dprintf(1, "PCI: Setting VGA enable on bridge %02x:%02x.%x\n",
353 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
354 pci_bdf_to_fn(pci->bdf));
355
356 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
357 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
358 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
359 }
360}
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400361
362/****************************************************************
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500363 * Platform device initialization
364 ****************************************************************/
365
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500366void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500367{
368 if (RamSize <= 0x80000000)
369 pcimem_start = 0x80000000;
370 else if (RamSize <= 0xc0000000)
371 pcimem_start = 0xc0000000;
Alex Williamsonb9490402013-02-15 14:11:41 -0700372
373 pci_slot_get_irq = piix_pci_slot_get_irq;
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500374}
375
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500376void mch_mem_addr_setup(struct pci_device *dev, void *arg)
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100377{
378 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
379 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
380
381 /* setup mmconfig */
382 u16 bdf = dev->bdf;
383 u32 upper = addr >> 32;
384 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
385 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
386 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
387 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
388 add_e820(addr, size, E820_RESERVED);
389
390 /* setup pci i/o window (above mmconfig) */
391 pcimem_start = addr + size;
Alex Williamsonb9490402013-02-15 14:11:41 -0700392
393 pci_slot_get_irq = mch_pci_slot_get_irq;
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100394}
395
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500396static const struct pci_device_id pci_platform_tbl[] = {
397 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500398 i440fx_mem_addr_setup),
Isaku Yamahata72a590e2012-11-28 10:17:33 +0100399 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500400 mch_mem_addr_setup),
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500401 PCI_DEVICE_END
402};
403
404static void pci_bios_init_platform(void)
405{
406 struct pci_device *pci;
407 foreachpci(pci) {
408 pci_init_device(pci_platform_tbl, pci, NULL);
409 }
410}
411
412
413/****************************************************************
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400414 * Bus initialization
415 ****************************************************************/
416
Isaku Yamahataf4416662010-06-22 17:57:52 +0900417static void
418pci_bios_init_bus_rec(int bus, u8 *pci_bus)
419{
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400420 int bdf;
Isaku Yamahataf4416662010-06-22 17:57:52 +0900421 u16 class;
422
423 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
424
425 /* prevent accidental access to unintended devices */
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400426 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900427 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
428 if (class == PCI_CLASS_BRIDGE_PCI) {
429 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
430 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
431 }
432 }
433
Kevin O'Connor2b333e42011-07-02 14:49:41 -0400434 foreachbdf(bdf, bus) {
Isaku Yamahataf4416662010-06-22 17:57:52 +0900435 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
436 if (class != PCI_CLASS_BRIDGE_PCI) {
437 continue;
438 }
439 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
440
441 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
442 if (pribus != bus) {
443 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
444 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
445 } else {
446 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
447 }
448
449 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
450 (*pci_bus)++;
451 if (*pci_bus != secbus) {
452 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
453 secbus, *pci_bus);
454 secbus = *pci_bus;
455 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
456 } else {
457 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
458 }
459
460 /* set to max for access to all subordinate buses.
461 later set it to accurate value */
462 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
463 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
464
465 pci_bios_init_bus_rec(secbus, pci_bus);
466
467 if (subbus != *pci_bus) {
468 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
469 subbus, *pci_bus);
470 subbus = *pci_bus;
471 } else {
472 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
473 }
474 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
475 }
476}
477
478static void
479pci_bios_init_bus(void)
480{
481 u8 pci_bus = 0;
482 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200483}
484
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400485
486/****************************************************************
487 * Bus sizing
488 ****************************************************************/
489
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400490static void
Alexey Korolev030288f2012-04-19 17:44:55 +1200491pci_bios_get_bar(struct pci_device *pci, int bar,
492 int *ptype, u64 *psize, int *pis64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200493{
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400494 u32 ofs = pci_bar(pci, bar);
495 u16 bdf = pci->bdf;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200496 u32 old = pci_config_readl(bdf, ofs);
Alexey Korolev030288f2012-04-19 17:44:55 +1200497 int is64 = 0, type = PCI_REGION_TYPE_MEM;
498 u64 mask;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200499
500 if (bar == PCI_ROM_SLOT) {
501 mask = PCI_ROM_ADDRESS_MASK;
502 pci_config_writel(bdf, ofs, mask);
503 } else {
Alexey Korolev030288f2012-04-19 17:44:55 +1200504 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200505 mask = PCI_BASE_ADDRESS_IO_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200506 type = PCI_REGION_TYPE_IO;
507 } else {
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200508 mask = PCI_BASE_ADDRESS_MEM_MASK;
Alexey Korolev030288f2012-04-19 17:44:55 +1200509 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
510 type = PCI_REGION_TYPE_PREFMEM;
511 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
512 == PCI_BASE_ADDRESS_MEM_TYPE_64);
513 }
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200514 pci_config_writel(bdf, ofs, ~0);
515 }
Alexey Korolev030288f2012-04-19 17:44:55 +1200516 u64 val = pci_config_readl(bdf, ofs);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200517 pci_config_writel(bdf, ofs, old);
Alexey Korolev030288f2012-04-19 17:44:55 +1200518 if (is64) {
519 u32 hold = pci_config_readl(bdf, ofs + 4);
520 pci_config_writel(bdf, ofs + 4, ~0);
521 u32 high = pci_config_readl(bdf, ofs + 4);
522 pci_config_writel(bdf, ofs + 4, hold);
523 val |= ((u64)high << 32);
524 mask |= ((u64)0xffffffff << 32);
525 *psize = (~(val & mask)) + 1;
526 } else {
527 *psize = ((~(val & mask)) + 1) & 0xffffffff;
528 }
529 *ptype = type;
530 *pis64 = is64;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200531}
532
Alexey Korolevac0cd582012-04-19 17:48:54 +1200533static int pci_bios_bridge_region_is64(struct pci_region *r,
534 struct pci_device *pci, int type)
535{
536 if (type != PCI_REGION_TYPE_PREFMEM)
537 return 0;
538 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
539 if (!pmem) {
540 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
541 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
542 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
543 }
544 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
545 return 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400546 struct pci_region_entry *entry;
547 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolevac0cd582012-04-19 17:48:54 +1200548 if (!entry->is64)
549 return 0;
Alexey Korolevac0cd582012-04-19 17:48:54 +1200550 }
551 return 1;
552}
553
Alexey Korolev37c111f2012-04-26 16:51:05 +1200554static u64 pci_region_align(struct pci_region *r)
555{
Kevin O'Connora88c1972013-06-08 21:51:46 -0400556 struct pci_region_entry *entry;
557 hlist_for_each_entry(entry, &r->list, node) {
558 // The first entry in the sorted list has the largest alignment
559 return entry->align;
560 }
561 return 1;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200562}
563
564static u64 pci_region_sum(struct pci_region *r)
565{
Alexey Korolev37c111f2012-04-26 16:51:05 +1200566 u64 sum = 0;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400567 struct pci_region_entry *entry;
568 hlist_for_each_entry(entry, &r->list, node) {
Alexey Korolev37c111f2012-04-26 16:51:05 +1200569 sum += entry->size;
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400570 }
571 return sum;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200572}
573
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200574static void pci_region_migrate_64bit_entries(struct pci_region *from,
575 struct pci_region *to)
576{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400577 struct hlist_node *n, **last = &to->list.first;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400578 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400579 hlist_for_each_entry_safe(entry, n, &from->list, node) {
Kevin O'Connora88c1972013-06-08 21:51:46 -0400580 if (!entry->is64)
Kevin O'Connord630d142012-04-26 22:20:56 -0400581 continue;
Kevin O'Connord630d142012-04-26 22:20:56 -0400582 // Move from source list to destination list.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400583 hlist_del(&entry->node);
584 hlist_add(&entry->node, last);
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200585 }
586}
587
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200588static struct pci_region_entry *
589pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
Alexey Korolev030288f2012-04-19 17:44:55 +1200590 int bar, u64 size, u64 align, int type, int is64)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200591{
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200592 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
593 if (!entry) {
594 warn_noalloc();
595 return NULL;
596 }
597 memset(entry, 0, sizeof(*entry));
598 entry->dev = dev;
599 entry->bar = bar;
600 entry->size = size;
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400601 entry->align = align;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200602 entry->is64 = is64;
603 entry->type = type;
604 // Insert into list in sorted order.
Kevin O'Connora88c1972013-06-08 21:51:46 -0400605 struct hlist_node **pprev;
606 struct pci_region_entry *pos;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400607 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400608 if (pos->align < align || (pos->align == align && pos->size < size))
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200609 break;
610 }
Kevin O'Connora88c1972013-06-08 21:51:46 -0400611 hlist_add(&entry->node, pprev);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200612 return entry;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200613}
614
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200615static int pci_bios_check_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200616{
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400617 dprintf(1, "PCI: check devices\n");
618
619 // Calculate resources needed for regular (non-bus) devices.
620 struct pci_device *pci;
621 foreachpci(pci) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200622 if (pci->class == PCI_CLASS_BRIDGE_PCI)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400623 busses[pci->secondary_bus].bus_dev = pci;
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200624
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400625 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
626 int i;
627 for (i = 0; i < PCI_NUM_REGIONS; i++) {
Alexey Korolev1a9f47f2012-04-19 17:40:13 +1200628 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
629 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
630 continue;
Alexey Korolev030288f2012-04-19 17:44:55 +1200631 int type, is64;
632 u64 size;
633 pci_bios_get_bar(pci, i, &type, &size, &is64);
634 if (size == 0)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400635 continue;
636
Alexey Korolev5fa24b52012-04-18 17:31:58 +1200637 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
638 size = PCI_DEVICE_MEM_MIN;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200639 struct pci_region_entry *entry = pci_region_create_entry(
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400640 bus, pci, i, size, size, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200641 if (!entry)
642 return -1;
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400643
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200644 if (is64)
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400645 i++;
646 }
647 }
648
649 // Propagate required bus resources to parent busses.
650 int secondary_bus;
651 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
652 struct pci_bus *s = &busses[secondary_bus];
653 if (!s->bus_dev)
654 continue;
655 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
Kevin O'Connorcbbdcf22011-10-01 13:13:29 -0400656 int type;
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200657 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
Alexey Korolev030288f2012-04-19 17:44:55 +1200658 u64 align = (type == PCI_REGION_TYPE_IO) ?
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200659 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
Alexey Korolev37c111f2012-04-26 16:51:05 +1200660 if (pci_region_align(&s->r[type]) > align)
661 align = pci_region_align(&s->r[type]);
662 u64 sum = pci_region_sum(&s->r[type]);
663 u64 size = ALIGN(sum, align);
Alexey Korolevac0cd582012-04-19 17:48:54 +1200664 int is64 = pci_bios_bridge_region_is64(&s->r[type],
665 s->bus_dev, type);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200666 // entry->bar is -1 if the entry represents a bridge region
667 struct pci_region_entry *entry = pci_region_create_entry(
Alexey Korolevac0cd582012-04-19 17:48:54 +1200668 parent, s->bus_dev, -1, size, align, type, is64);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200669 if (!entry)
670 return -1;
Alexey Korolev030288f2012-04-19 17:44:55 +1200671 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
Alexey Korolevf3c2b062012-04-18 17:26:43 +1200672 entry->dev->secondary_bus, size,
673 region_type_name[entry->type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200674 }
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400675 }
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200676 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400677}
678
Kevin O'Connore5d71ca2012-04-26 22:04:34 -0400679
680/****************************************************************
681 * BAR assignment
682 ****************************************************************/
683
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400684// Setup region bases (given the regions' size and alignment)
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200685static int pci_bios_init_root_regions(struct pci_bus *bus)
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400686{
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400687 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
688
Alexey Korolev37c111f2012-04-26 16:51:05 +1200689 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
690 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
691
692 if (pci_region_align(r_start) < pci_region_align(r_end)) {
Kevin O'Connor3d1bc9d2012-04-01 12:30:32 -0400693 // Swap regions to improve alignment.
Alexey Korolev37c111f2012-04-26 16:51:05 +1200694 r_end = r_start;
695 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400696 }
Alexey Korolev37c111f2012-04-26 16:51:05 +1200697 u64 sum = pci_region_sum(r_end);
698 u64 align = pci_region_align(r_end);
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +0200699 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
Alexey Korolev37c111f2012-04-26 16:51:05 +1200700 sum = pci_region_sum(r_start);
701 align = pci_region_align(r_start);
702 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
703
Gerd Hoffmanne55c4e82012-06-07 10:34:32 +0200704 if ((r_start->base < pcimem_start) ||
705 (r_start->base > pcimem_end))
Kevin O'Connora8dcc5b2011-10-01 12:08:57 -0400706 // Memory range requested is larger than available.
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200707 return -1;
708 return 0;
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400709}
710
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400711#define PCI_IO_SHIFT 8
712#define PCI_MEMORY_SHIFT 16
713#define PCI_PREF_MEMORY_SHIFT 16
714
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200715static void
Alexey Korolev35a770f2012-04-19 17:47:19 +1200716pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200717{
718 u16 bdf = entry->dev->bdf;
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200719 if (entry->bar >= 0) {
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200720 dprintf(1, "PCI: map device bdf=%02x:%02x.%x"
Alexey Korolev030288f2012-04-19 17:44:55 +1200721 " bar %d, addr %08llx, size %08llx [%s]\n",
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200722 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf),
723 entry->bar, addr, entry->size, region_type_name[entry->type]);
724
Alexey Korolev030288f2012-04-19 17:44:55 +1200725 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
Alexey Korolev3a297162012-04-18 17:22:29 +1200726 return;
727 }
728
Alexey Korolev030288f2012-04-19 17:44:55 +1200729 u64 limit = addr + entry->size - 1;
Alexey Korolev3a297162012-04-18 17:22:29 +1200730 if (entry->type == PCI_REGION_TYPE_IO) {
731 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
732 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
733 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
734 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
735 }
736 if (entry->type == PCI_REGION_TYPE_MEM) {
737 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
738 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
739 }
740 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
741 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
742 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
Alexey Korolev030288f2012-04-19 17:44:55 +1200743 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
744 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200745 }
746}
747
Alexey Korolev35a770f2012-04-19 17:47:19 +1200748static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
749{
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400750 struct hlist_node *n;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400751 struct pci_region_entry *entry;
Kevin O'Connor030a58a2013-06-13 21:24:14 -0400752 hlist_for_each_entry_safe(entry, n, &r->list, node) {
Alexey Korolev35a770f2012-04-19 17:47:19 +1200753 u64 addr = r->base;
754 r->base += entry->size;
755 if (entry->bar == -1)
756 // Update bus base address if entry is a bridge region
757 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
758 pci_region_map_one_entry(entry, addr);
Kevin O'Connora88c1972013-06-08 21:51:46 -0400759 hlist_del(&entry->node);
Alexey Korolev35a770f2012-04-19 17:47:19 +1200760 free(entry);
Alexey Korolev35a770f2012-04-19 17:47:19 +1200761 }
762}
763
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400764static void pci_bios_map_devices(struct pci_bus *busses)
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200765{
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200766 if (pci_bios_init_root_regions(busses)) {
767 struct pci_region r64_mem, r64_pref;
Kevin O'Connora88c1972013-06-08 21:51:46 -0400768 r64_mem.list.first = NULL;
769 r64_pref.list.first = NULL;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200770 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
771 &r64_mem);
772 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
773 &r64_pref);
774
775 if (pci_bios_init_root_regions(busses))
776 panic("PCI: out of 32bit address space\n");
777
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200778 u64 sum_mem = pci_region_sum(&r64_mem);
779 u64 sum_pref = pci_region_sum(&r64_pref);
780 u64 align_mem = pci_region_align(&r64_mem);
781 u64 align_pref = pci_region_align(&r64_pref);
782
783 r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
784 r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
785 pcimem64_start = r64_mem.base;
786 pcimem64_end = r64_pref.base + sum_pref;
787
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200788 pci_region_map_entries(busses, &r64_mem);
789 pci_region_map_entries(busses, &r64_pref);
Gerd Hoffmann5283b2e2012-06-12 09:27:15 +0200790 } else {
791 // no bars mapped high -> drop 64bit window (see dsdt)
792 pcimem64_start = 0;
Alexey Koroleve5e5f962012-04-26 17:01:59 +1200793 }
Kevin O'Connor2c4c2112011-10-15 11:42:48 -0400794 // Map regions on each device.
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200795 int bus;
796 for (bus = 0; bus<=MaxPCIBus; bus++) {
797 int type;
Alexey Korolev35a770f2012-04-19 17:47:19 +1200798 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
799 pci_region_map_entries(busses, &busses[bus].r[type]);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200800 }
801}
802
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200803
Kevin O'Connor5bab7e62011-10-01 11:33:31 -0400804/****************************************************************
805 * Main setup code
806 ****************************************************************/
Isaku Yamahataf4416662010-06-22 17:57:52 +0900807
Kevin O'Connor0525d292008-07-04 06:18:30 -0400808void
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400809pci_setup(void)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400810{
Kevin O'Connora2a86e22013-02-13 19:35:12 -0500811 if (!CONFIG_QEMU)
Kevin O'Connor0525d292008-07-04 06:18:30 -0400812 return;
813
Kevin O'Connor40f5b5a2009-09-13 10:46:57 -0400814 dprintf(3, "pci setup\n");
815
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200816 dprintf(1, "=== PCI bus & bridge init ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200817 if (pci_probe_host() != 0) {
818 return;
819 }
Isaku Yamahataf4416662010-06-22 17:57:52 +0900820 pci_bios_init_bus();
821
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200822 dprintf(1, "=== PCI device probing ===\n");
Jan Kiszka58e6b3f2011-09-21 08:16:21 +0200823 pci_probe_devices();
Kevin O'Connor37956dd2011-06-21 22:22:58 -0400824
Kevin O'Connorb1c35f22012-11-26 11:05:32 -0500825 pcimem_start = RamSize;
826 pci_bios_init_platform();
827
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200828 dprintf(1, "=== PCI new allocation pass #1 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400829 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
Kevin O'Connor28a20e12011-10-15 11:07:30 -0400830 if (!busses) {
831 warn_noalloc();
832 return;
833 }
834 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
Alexey Korolevfa51bcd2012-04-18 17:21:19 +1200835 if (pci_bios_check_devices(busses))
836 return;
837
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200838 dprintf(1, "=== PCI new allocation pass #2 ===\n");
Kevin O'Connorb725dcb2011-10-15 11:53:38 -0400839 pci_bios_map_devices(busses);
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200840
Kevin O'Connor3f2288f2011-10-15 12:02:14 -0400841 pci_bios_init_devices();
Gerd Hoffmann8e301472011-08-09 17:22:42 +0200842
Gerd Hoffmann82b39b22011-07-11 09:20:28 +0200843 free(busses);
Alex Williamson7adfd712013-03-20 10:58:47 -0600844
845 pci_enable_default_vga();
Kevin O'Connor0525d292008-07-04 06:18:30 -0400846}