blob: a47be648a9c8e987f96cdaaf71676a23a3a20013 [file] [log] [blame]
Kevin O'Connor276d4a92008-06-11 22:47:01 -04001// Support for enabling/disabling BIOS ram shadowing.
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
6// This file may be distributed under the terms of the GNU GPLv3 license.
7
8#include "acpi.h" // struct rsdp_descriptor
9#include "util.h" // memcpy
10#include "memmap.h" // bios_table_cur_addr
11#include "pci.h" // pci_find_device
12
13
14/****************************************************/
15/* ACPI tables init */
16
17/* Table structure from Linux kernel (the ACPI tables are under the
18 BSD license) */
19
20#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
21 u8 signature [4]; /* ACPI signature (4 ASCII characters) */\
22 u32 length; /* Length of table, in bytes, including header */\
23 u8 revision; /* ACPI Specification minor version # */\
24 u8 checksum; /* To make sum of entire table == 0 */\
25 u8 oem_id [6]; /* OEM identification */\
26 u8 oem_table_id [8]; /* OEM table identification */\
27 u32 oem_revision; /* OEM revision number */\
28 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */\
29 u32 asl_compiler_revision; /* ASL compiler revision number */
30
31
32struct acpi_table_header /* ACPI common table header */
33{
34 ACPI_TABLE_HEADER_DEF
35};
36
37/*
38 * ACPI 1.0 Root System Description Table (RSDT)
39 */
40struct rsdt_descriptor_rev1
41{
42 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
43 u32 table_offset_entry [3]; /* Array of pointers to other */
44 /* ACPI tables */
45};
46
47/*
48 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
49 */
50struct facs_descriptor_rev1
51{
52 u8 signature[4]; /* ACPI Signature */
53 u32 length; /* Length of structure, in bytes */
54 u32 hardware_signature; /* Hardware configuration signature */
55 u32 firmware_waking_vector; /* ACPI OS waking vector */
56 u32 global_lock; /* Global Lock */
57 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
58 u32 reserved1 : 31; /* Must be 0 */
59 u8 resverved3 [40]; /* Reserved - must be zero */
60};
61
62
63/*
64 * ACPI 1.0 Fixed ACPI Description Table (FADT)
65 */
66struct fadt_descriptor_rev1
67{
68 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
69 u32 firmware_ctrl; /* Physical address of FACS */
70 u32 dsdt; /* Physical address of DSDT */
71 u8 model; /* System Interrupt Model */
72 u8 reserved1; /* Reserved */
73 u16 sci_int; /* System vector of SCI interrupt */
74 u32 smi_cmd; /* Port address of SMI command port */
75 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
76 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
77 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
78 u8 reserved2; /* Reserved - must be zero */
79 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
80 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
81 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
82 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
83 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
84 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
85 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
86 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
87 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
88 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
89 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
90 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
91 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
92 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
93 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
94 u8 reserved3; /* Reserved */
95 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
96 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
97 u16 flush_size; /* Size of area read to flush caches */
98 u16 flush_stride; /* Stride used in flushing caches */
99 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
100 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
101 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
102 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
103 u8 century; /* Index to century in RTC CMOS RAM */
104 u8 reserved4; /* Reserved */
105 u8 reserved4a; /* Reserved */
106 u8 reserved4b; /* Reserved */
107#if 0
108 u32 wb_invd : 1; /* The wbinvd instruction works properly */
109 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
110 u32 proc_c1 : 1; /* All processors support C1 state */
111 u32 plvl2_up : 1; /* C2 state works on MP system */
112 u32 pwr_button : 1; /* Power button is handled as a generic feature */
113 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
114 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
115 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
116 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
117 u32 reserved5 : 23; /* Reserved - must be zero */
118#else
119 u32 flags;
120#endif
121};
122
123/*
124 * MADT values and structures
125 */
126
127/* Values for MADT PCATCompat */
128
129#define DUAL_PIC 0
130#define MULTIPLE_APIC 1
131
132
133/* Master MADT */
134
135struct multiple_apic_table
136{
137 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
138 u32 local_apic_address; /* Physical address of local APIC */
139#if 0
140 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
141 u32 reserved1 : 31;
142#else
143 u32 flags;
144#endif
145};
146
147
148/* Values for Type in APIC_HEADER_DEF */
149
150#define APIC_PROCESSOR 0
151#define APIC_IO 1
152#define APIC_XRUPT_OVERRIDE 2
153#define APIC_NMI 3
154#define APIC_LOCAL_NMI 4
155#define APIC_ADDRESS_OVERRIDE 5
156#define APIC_IO_SAPIC 6
157#define APIC_LOCAL_SAPIC 7
158#define APIC_XRUPT_SOURCE 8
159#define APIC_RESERVED 9 /* 9 and greater are reserved */
160
161/*
162 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
163 */
164#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
165 u8 type; \
166 u8 length;
167
168/* Sub-structures for MADT */
169
170struct madt_processor_apic
171{
172 APIC_HEADER_DEF
173 u8 processor_id; /* ACPI processor id */
174 u8 local_apic_id; /* Processor's local APIC id */
175#if 0
176 u32 processor_enabled: 1; /* Processor is usable if set */
177 u32 reserved2 : 31; /* Reserved, must be zero */
178#else
179 u32 flags;
180#endif
181};
182
183struct madt_io_apic
184{
185 APIC_HEADER_DEF
186 u8 io_apic_id; /* I/O APIC ID */
187 u8 reserved; /* Reserved - must be zero */
188 u32 address; /* APIC physical address */
189 u32 interrupt; /* Global system interrupt where INTI
190 * lines start */
191};
192
193#include "acpi-dsdt.hex"
194
195static inline u16 cpu_to_le16(u16 x)
196{
197 return x;
198}
199
200static inline u32 cpu_to_le32(u32 x)
201{
202 return x;
203}
204
205static void acpi_build_table_header(struct acpi_table_header *h,
206 char *sig, int len, u8 rev)
207{
208 memcpy(h->signature, sig, 4);
209 h->length = cpu_to_le32(len);
210 h->revision = rev;
211#if (CONFIG_QEMU == 1)
212 memcpy(h->oem_id, "QEMU ", 6);
213 memcpy(h->oem_table_id, "QEMU", 4);
214#else
215 memcpy(h->oem_id, "BOCHS ", 6);
216 memcpy(h->oem_table_id, "BXPC", 4);
217#endif
218 memcpy(h->oem_table_id + 4, sig, 4);
219 h->oem_revision = cpu_to_le32(1);
220#if (CONFIG_QEMU == 1)
221 memcpy(h->asl_compiler_id, "QEMU", 4);
222#else
223 memcpy(h->asl_compiler_id, "BXPC", 4);
224#endif
225 h->asl_compiler_revision = cpu_to_le32(1);
226 h->checksum = -checksum((void *)h, len);
227}
228
229static int
230acpi_build_processor_ssdt(u8 *ssdt)
231{
232 u8 *ssdt_ptr = ssdt;
233 int i, length;
234 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
235
236 ssdt_ptr[9] = 0; // checksum;
237 ssdt_ptr += sizeof(struct acpi_table_header);
238
239 // caluculate the length of processor block and scope block excluding PkgLength
240 length = 0x0d * acpi_cpus + 4;
241
242 // build processor scope header
243 *(ssdt_ptr++) = 0x10; // ScopeOp
244 if (length <= 0x3e) {
245 *(ssdt_ptr++) = length + 1;
246 } else {
247 *(ssdt_ptr++) = 0x7F;
248 *(ssdt_ptr++) = (length + 2) >> 6;
249 }
250 *(ssdt_ptr++) = '_'; // Name
251 *(ssdt_ptr++) = 'P';
252 *(ssdt_ptr++) = 'R';
253 *(ssdt_ptr++) = '_';
254
255 // build object for each processor
256 for(i=0;i<acpi_cpus;i++) {
257 *(ssdt_ptr++) = 0x5B; // ProcessorOp
258 *(ssdt_ptr++) = 0x83;
259 *(ssdt_ptr++) = 0x0B; // Length
260 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
261 *(ssdt_ptr++) = 'P';
262 if ((i & 0xf0) != 0)
263 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
264 else
265 *(ssdt_ptr++) = 'U';
266 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
267 *(ssdt_ptr++) = i;
268 *(ssdt_ptr++) = 0x10; // Processor block address
269 *(ssdt_ptr++) = 0xb0;
270 *(ssdt_ptr++) = 0;
271 *(ssdt_ptr++) = 0;
272 *(ssdt_ptr++) = 6; // Processor block length
273 }
274
275 acpi_build_table_header((struct acpi_table_header *)ssdt,
276 "SSDT", ssdt_ptr - ssdt, 1);
277
278 return ssdt_ptr - ssdt;
279}
280
281/* base_addr must be a multiple of 4KB */
282void acpi_bios_init(void)
283{
284 // This code is hardcoded for PIIX4 Power Management device.
285 PCIDevice d;
286 int ret = pci_find_device(0x8086, 0x7113, 0, &d);
287 if (ret)
288 // Device not found
289 return;
290
291 struct rsdp_descriptor *rsdp;
292 struct rsdt_descriptor_rev1 *rsdt;
293 struct fadt_descriptor_rev1 *fadt;
294 struct facs_descriptor_rev1 *facs;
295 struct multiple_apic_table *madt;
296 u8 *dsdt, *ssdt;
297 u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
298 u32 acpi_tables_size, madt_addr, madt_size;
299 int i;
300
301 /* reserve memory space for tables */
302#if (CONFIG_USE_EBDA_TABLES == 1)
303 ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
304 rsdp = (void *)(ebda_cur_addr);
305 ebda_cur_addr += sizeof(*rsdp);
306#else
307 bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
308 rsdp = (void *)(bios_table_cur_addr);
309 bios_table_cur_addr += sizeof(*rsdp);
310#endif
311
312 addr = base_addr = GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE;
313 add_e820(addr, CONFIG_ACPI_DATA_SIZE, E820_ACPI);
314 rsdt_addr = addr;
315 rsdt = (void *)(addr);
316 addr += sizeof(*rsdt);
317
318 fadt_addr = addr;
319 fadt = (void *)(addr);
320 addr += sizeof(*fadt);
321
322 /* XXX: FACS should be in RAM */
323 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
324 facs_addr = addr;
325 facs = (void *)(addr);
326 addr += sizeof(*facs);
327
328 dsdt_addr = addr;
329 dsdt = (void *)(addr);
330 addr += sizeof(AmlCode);
331
332 ssdt_addr = addr;
333 ssdt = (void *)(addr);
334 addr += acpi_build_processor_ssdt(ssdt);
335
336 addr = (addr + 7) & ~7;
337 madt_addr = addr;
338 madt_size = sizeof(*madt) +
339 sizeof(struct madt_processor_apic) * smp_cpus +
340 sizeof(struct madt_io_apic);
341 madt = (void *)(addr);
342 addr += madt_size;
343
344 acpi_tables_size = addr - base_addr;
345
346 dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
347 " ACPI DATA addr=0x%08lx size=0x%x\n",
348 (unsigned long)rsdp,
349 (unsigned long)rsdt, acpi_tables_size);
350
351 /* RSDP */
352 memset(rsdp, 0, sizeof(*rsdp));
353 memcpy(rsdp->signature, "RSD PTR ", 8);
354#if (CONFIG_QEMU == 1)
355 memcpy(rsdp->oem_id, "QEMU ", 6);
356#else
357 memcpy(rsdp->oem_id, "BOCHS ", 6);
358#endif
359 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
360 rsdp->checksum = -checksum((void *)rsdp, 20);
361
362 /* RSDT */
363 memset(rsdt, 0, sizeof(*rsdt));
364 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
365 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
366 rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
367 acpi_build_table_header((struct acpi_table_header *)rsdt,
368 "RSDT", sizeof(*rsdt), 1);
369
370 /* FADT */
371 memset(fadt, 0, sizeof(*fadt));
372 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
373 fadt->dsdt = cpu_to_le32(dsdt_addr);
374 fadt->model = 1;
375 fadt->reserved1 = 0;
376 int pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
377 fadt->sci_int = cpu_to_le16(pm_sci_int);
378 fadt->smi_cmd = cpu_to_le32(BUILD_SMI_CMD_IO_ADDR);
379 fadt->acpi_enable = 0xf1;
380 fadt->acpi_disable = 0xf0;
381 fadt->pm1a_evt_blk = cpu_to_le32(BUILD_PM_IO_BASE);
382 fadt->pm1a_cnt_blk = cpu_to_le32(BUILD_PM_IO_BASE + 0x04);
383 fadt->pm_tmr_blk = cpu_to_le32(BUILD_PM_IO_BASE + 0x08);
384 fadt->pm1_evt_len = 4;
385 fadt->pm1_cnt_len = 2;
386 fadt->pm_tmr_len = 4;
387 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
388 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
389 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
390 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
391 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
392 sizeof(*fadt), 1);
393
394 /* FACS */
395 memset(facs, 0, sizeof(*facs));
396 memcpy(facs->signature, "FACS", 4);
397 facs->length = cpu_to_le32(sizeof(*facs));
398
399 /* DSDT */
400 memcpy(dsdt, AmlCode, sizeof(AmlCode));
401
402 /* MADT */
403 {
404 struct madt_processor_apic *apic;
405 struct madt_io_apic *io_apic;
406
407 memset(madt, 0, madt_size);
408 madt->local_apic_address = cpu_to_le32(0xfee00000);
409 madt->flags = cpu_to_le32(1);
410 apic = (void *)(madt + 1);
411 for(i=0;i<smp_cpus;i++) {
412 apic->type = APIC_PROCESSOR;
413 apic->length = sizeof(*apic);
414 apic->processor_id = i;
415 apic->local_apic_id = i;
416 apic->flags = cpu_to_le32(1);
417 apic++;
418 }
419 io_apic = (void *)apic;
420 io_apic->type = APIC_IO;
421 io_apic->length = sizeof(*io_apic);
422 io_apic->io_apic_id = smp_cpus;
423 io_apic->address = cpu_to_le32(0xfec00000);
424 io_apic->interrupt = cpu_to_le32(0);
425
426 acpi_build_table_header((struct acpi_table_header *)madt,
427 "APIC", madt_size, 1);
428 }
429}