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Kevin O'Connord9211ee2012-01-31 22:54:49 -05001// Bochs VGA interface to extended "VBE" modes
2//
3// Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2011 Julian Pidancet <julian.pidancet@citrix.com>
5// Copyright (C) 2002 Jeroen Janssen
6//
7// This file may be distributed under the terms of the GNU LGPLv3 license.
8
Kevin O'Connore6bc4c12012-01-21 11:26:37 -05009#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040010#include "bochsvga.h" // bochsvga_set_mode
11#include "config.h" // CONFIG_*
Kevin O'Connor5d369d82013-09-02 20:48:46 -040012#include "hw/pci.h" // pci_config_readl
13#include "hw/pci_regs.h" // PCI_BASE_ADDRESS_0
Kevin O'Connor2d2fa312013-09-14 21:55:26 -040014#include "output.h" // dprintf
Kevin O'Connor2e57c812013-09-14 22:29:32 -040015#include "std/vbe.h" // VBE_CAPABILITY_8BIT_DAC
Kevin O'Connorc682ffe2016-08-05 11:48:20 -040016#include "stdvga.h" // stdvga_get_linelength
Kevin O'Connor2f2ec112016-08-05 11:14:58 -040017#include "vgabios.h" // SET_VGA
18#include "vgautil.h" // VBE_total_memory
Kevin O'Connor4ade5232013-09-18 21:41:48 -040019#include "x86.h" // outw
Julian Pidancet87879e22011-12-19 05:08:00 +000020
Kevin O'Connor933bb762012-02-01 21:54:55 -050021
22/****************************************************************
23 * Mode tables
24 ****************************************************************/
25
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050026static struct bochsvga_mode
Julian Pidancet87879e22011-12-19 05:08:00 +000027{
28 u16 mode;
Kevin O'Connorc4a0b972012-01-09 20:21:31 -050029 struct vgamode_s info;
Kevin O'Connorf1e217d2011-12-31 03:18:18 -050030} bochsvga_modes[] VAR16 = {
Julian Pidancet87879e22011-12-19 05:08:00 +000031 /* standard modes */
Kevin O'Connor03776022012-01-21 11:00:11 -050032 { 0x100, { MM_PACKED, 640, 400, 8, 8, 16, SEG_GRAPH } },
33 { 0x101, { MM_PACKED, 640, 480, 8, 8, 16, SEG_GRAPH } },
34 { 0x102, { MM_PLANAR, 800, 600, 4, 8, 16, SEG_GRAPH } },
35 { 0x103, { MM_PACKED, 800, 600, 8, 8, 16, SEG_GRAPH } },
36 { 0x104, { MM_PLANAR, 1024, 768, 4, 8, 16, SEG_GRAPH } },
37 { 0x105, { MM_PACKED, 1024, 768, 8, 8, 16, SEG_GRAPH } },
38 { 0x106, { MM_PLANAR, 1280, 1024, 4, 8, 16, SEG_GRAPH } },
39 { 0x107, { MM_PACKED, 1280, 1024, 8, 8, 16, SEG_GRAPH } },
40 { 0x10D, { MM_DIRECT, 320, 200, 15, 8, 16, SEG_GRAPH } },
41 { 0x10E, { MM_DIRECT, 320, 200, 16, 8, 16, SEG_GRAPH } },
42 { 0x10F, { MM_DIRECT, 320, 200, 24, 8, 16, SEG_GRAPH } },
43 { 0x110, { MM_DIRECT, 640, 480, 15, 8, 16, SEG_GRAPH } },
44 { 0x111, { MM_DIRECT, 640, 480, 16, 8, 16, SEG_GRAPH } },
45 { 0x112, { MM_DIRECT, 640, 480, 24, 8, 16, SEG_GRAPH } },
46 { 0x113, { MM_DIRECT, 800, 600, 15, 8, 16, SEG_GRAPH } },
47 { 0x114, { MM_DIRECT, 800, 600, 16, 8, 16, SEG_GRAPH } },
48 { 0x115, { MM_DIRECT, 800, 600, 24, 8, 16, SEG_GRAPH } },
49 { 0x116, { MM_DIRECT, 1024, 768, 15, 8, 16, SEG_GRAPH } },
50 { 0x117, { MM_DIRECT, 1024, 768, 16, 8, 16, SEG_GRAPH } },
51 { 0x118, { MM_DIRECT, 1024, 768, 24, 8, 16, SEG_GRAPH } },
52 { 0x119, { MM_DIRECT, 1280, 1024, 15, 8, 16, SEG_GRAPH } },
53 { 0x11A, { MM_DIRECT, 1280, 1024, 16, 8, 16, SEG_GRAPH } },
54 { 0x11B, { MM_DIRECT, 1280, 1024, 24, 8, 16, SEG_GRAPH } },
55 { 0x11C, { MM_PACKED, 1600, 1200, 8, 8, 16, SEG_GRAPH } },
56 { 0x11D, { MM_DIRECT, 1600, 1200, 15, 8, 16, SEG_GRAPH } },
57 { 0x11E, { MM_DIRECT, 1600, 1200, 16, 8, 16, SEG_GRAPH } },
58 { 0x11F, { MM_DIRECT, 1600, 1200, 24, 8, 16, SEG_GRAPH } },
Julian Pidancet87879e22011-12-19 05:08:00 +000059 /* BOCHS modes */
Kevin O'Connor03776022012-01-21 11:00:11 -050060 { 0x140, { MM_DIRECT, 320, 200, 32, 8, 16, SEG_GRAPH } },
61 { 0x141, { MM_DIRECT, 640, 400, 32, 8, 16, SEG_GRAPH } },
62 { 0x142, { MM_DIRECT, 640, 480, 32, 8, 16, SEG_GRAPH } },
63 { 0x143, { MM_DIRECT, 800, 600, 32, 8, 16, SEG_GRAPH } },
64 { 0x144, { MM_DIRECT, 1024, 768, 32, 8, 16, SEG_GRAPH } },
65 { 0x145, { MM_DIRECT, 1280, 1024, 32, 8, 16, SEG_GRAPH } },
66 { 0x146, { MM_PACKED, 320, 200, 8, 8, 16, SEG_GRAPH } },
67 { 0x147, { MM_DIRECT, 1600, 1200, 32, 8, 16, SEG_GRAPH } },
68 { 0x148, { MM_PACKED, 1152, 864, 8, 8, 16, SEG_GRAPH } },
69 { 0x149, { MM_DIRECT, 1152, 864, 15, 8, 16, SEG_GRAPH } },
70 { 0x14a, { MM_DIRECT, 1152, 864, 16, 8, 16, SEG_GRAPH } },
71 { 0x14b, { MM_DIRECT, 1152, 864, 24, 8, 16, SEG_GRAPH } },
72 { 0x14c, { MM_DIRECT, 1152, 864, 32, 8, 16, SEG_GRAPH } },
Kevin O'Connora9dcc882013-11-30 11:04:09 -050073 { 0x175, { MM_DIRECT, 1280, 768, 16, 8, 16, SEG_GRAPH } },
74 { 0x176, { MM_DIRECT, 1280, 768, 24, 8, 16, SEG_GRAPH } },
75 { 0x177, { MM_DIRECT, 1280, 768, 32, 8, 16, SEG_GRAPH } },
Kevin O'Connor03776022012-01-21 11:00:11 -050076 { 0x178, { MM_DIRECT, 1280, 800, 16, 8, 16, SEG_GRAPH } },
77 { 0x179, { MM_DIRECT, 1280, 800, 24, 8, 16, SEG_GRAPH } },
78 { 0x17a, { MM_DIRECT, 1280, 800, 32, 8, 16, SEG_GRAPH } },
79 { 0x17b, { MM_DIRECT, 1280, 960, 16, 8, 16, SEG_GRAPH } },
80 { 0x17c, { MM_DIRECT, 1280, 960, 24, 8, 16, SEG_GRAPH } },
81 { 0x17d, { MM_DIRECT, 1280, 960, 32, 8, 16, SEG_GRAPH } },
82 { 0x17e, { MM_DIRECT, 1440, 900, 16, 8, 16, SEG_GRAPH } },
83 { 0x17f, { MM_DIRECT, 1440, 900, 24, 8, 16, SEG_GRAPH } },
84 { 0x180, { MM_DIRECT, 1440, 900, 32, 8, 16, SEG_GRAPH } },
85 { 0x181, { MM_DIRECT, 1400, 1050, 16, 8, 16, SEG_GRAPH } },
86 { 0x182, { MM_DIRECT, 1400, 1050, 24, 8, 16, SEG_GRAPH } },
87 { 0x183, { MM_DIRECT, 1400, 1050, 32, 8, 16, SEG_GRAPH } },
88 { 0x184, { MM_DIRECT, 1680, 1050, 16, 8, 16, SEG_GRAPH } },
89 { 0x185, { MM_DIRECT, 1680, 1050, 24, 8, 16, SEG_GRAPH } },
90 { 0x186, { MM_DIRECT, 1680, 1050, 32, 8, 16, SEG_GRAPH } },
91 { 0x187, { MM_DIRECT, 1920, 1200, 16, 8, 16, SEG_GRAPH } },
92 { 0x188, { MM_DIRECT, 1920, 1200, 24, 8, 16, SEG_GRAPH } },
93 { 0x189, { MM_DIRECT, 1920, 1200, 32, 8, 16, SEG_GRAPH } },
94 { 0x18a, { MM_DIRECT, 2560, 1600, 16, 8, 16, SEG_GRAPH } },
95 { 0x18b, { MM_DIRECT, 2560, 1600, 24, 8, 16, SEG_GRAPH } },
96 { 0x18c, { MM_DIRECT, 2560, 1600, 32, 8, 16, SEG_GRAPH } },
Kevin O'Connora9dcc882013-11-30 11:04:09 -050097 { 0x18d, { MM_DIRECT, 1280, 720, 16, 8, 16, SEG_GRAPH } },
98 { 0x18e, { MM_DIRECT, 1280, 720, 24, 8, 16, SEG_GRAPH } },
99 { 0x18f, { MM_DIRECT, 1280, 720, 32, 8, 16, SEG_GRAPH } },
100 { 0x190, { MM_DIRECT, 1920, 1080, 16, 8, 16, SEG_GRAPH } },
101 { 0x191, { MM_DIRECT, 1920, 1080, 24, 8, 16, SEG_GRAPH } },
102 { 0x192, { MM_DIRECT, 1920, 1080, 32, 8, 16, SEG_GRAPH } },
Julian Pidancet87879e22011-12-19 05:08:00 +0000103};
104
Gerd Hoffmann53663502013-09-05 10:16:18 +0200105static int dispi_found VAR16 = 0;
106
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500107static int is_bochsvga_mode(struct vgamode_s *vmode_g)
108{
109 return (vmode_g >= &bochsvga_modes[0].info
110 && vmode_g <= &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)-1].info);
111}
112
Kevin O'Connor3339c052012-01-13 20:00:35 -0500113struct vgamode_s *bochsvga_find_mode(int mode)
114{
115 struct bochsvga_mode *m = bochsvga_modes;
Gerd Hoffmann53663502013-09-05 10:16:18 +0200116 if (GET_GLOBAL(dispi_found))
117 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
118 if (GET_GLOBAL(m->mode) == mode)
119 return &m->info;
Kevin O'Connor3339c052012-01-13 20:00:35 -0500120 return stdvga_find_mode(mode);
Julian Pidancet87879e22011-12-19 05:08:00 +0000121}
122
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500123void
124bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
Julian Pidancet87879e22011-12-19 05:08:00 +0000125{
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500126 struct bochsvga_mode *m = bochsvga_modes;
Gerd Hoffmann53663502013-09-05 10:16:18 +0200127 if (GET_GLOBAL(dispi_found)) {
128 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
129 u16 mode = GET_GLOBAL(m->mode);
130 if (mode == 0xffff)
131 continue;
132 SET_FARVAR(seg, *dest, mode);
133 dest++;
134 }
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000135 }
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500136 stdvga_list_modes(seg, dest, last);
Julian Pidancet87879e22011-12-19 05:08:00 +0000137}
138
Kevin O'Connor933bb762012-02-01 21:54:55 -0500139
140/****************************************************************
141 * Helper functions
142 ****************************************************************/
143
Kevin O'Connor4ade5232013-09-18 21:41:48 -0400144static inline u16 dispi_read(u16 reg)
145{
146 outw(reg, VBE_DISPI_IOPORT_INDEX);
147 return inw(VBE_DISPI_IOPORT_DATA);
148}
149static inline void dispi_write(u16 reg, u16 val)
150{
151 outw(reg, VBE_DISPI_IOPORT_INDEX);
152 outw(val, VBE_DISPI_IOPORT_DATA);
153}
154
Paolo Bonzini9c291482015-01-01 21:27:46 +0100155static u8
156bochsvga_dispi_enabled(void)
157{
158 if (!GET_GLOBAL(dispi_found))
159 return 0;
160 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
161 if (!(en & VBE_DISPI_ENABLED))
162 return 0;
163 return 1;
164}
165
Kevin O'Connor9961f992012-01-21 11:53:44 -0500166int
167bochsvga_get_window(struct vgamode_s *vmode_g, int window)
168{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100169 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200170 return stdvga_get_window(vmode_g, window);
Kevin O'Connor9961f992012-01-21 11:53:44 -0500171 if (window != 0)
172 return -1;
173 return dispi_read(VBE_DISPI_INDEX_BANK);
174}
175
176int
177bochsvga_set_window(struct vgamode_s *vmode_g, int window, int val)
178{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100179 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200180 return stdvga_set_window(vmode_g, window, val);
Kevin O'Connor9961f992012-01-21 11:53:44 -0500181 if (window != 0)
182 return -1;
183 dispi_write(VBE_DISPI_INDEX_BANK, val);
184 if (dispi_read(VBE_DISPI_INDEX_BANK) != val)
185 return -1;
186 return 0;
187}
188
Kevin O'Connor3876b532012-01-24 00:07:44 -0500189int
190bochsvga_get_linelength(struct vgamode_s *vmode_g)
191{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100192 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200193 return stdvga_get_linelength(vmode_g);
Kevin O'Connor3876b532012-01-24 00:07:44 -0500194 return dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * vga_bpp(vmode_g) / 8;
195}
196
197int
198bochsvga_set_linelength(struct vgamode_s *vmode_g, int val)
199{
200 stdvga_set_linelength(vmode_g, val);
Paolo Bonzini9c291482015-01-01 21:27:46 +0100201 if (bochsvga_dispi_enabled()) {
Gerd Hoffmann53663502013-09-05 10:16:18 +0200202 int pixels = (val * 8) / vga_bpp(vmode_g);
203 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, pixels);
204 }
Kevin O'Connor3876b532012-01-24 00:07:44 -0500205 return 0;
206}
207
Kevin O'Connord61fc532012-01-27 20:37:45 -0500208int
209bochsvga_get_displaystart(struct vgamode_s *vmode_g)
210{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100211 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200212 return stdvga_get_displaystart(vmode_g);
Kevin O'Connord61fc532012-01-27 20:37:45 -0500213 int bpp = vga_bpp(vmode_g);
214 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
215 int x = dispi_read(VBE_DISPI_INDEX_X_OFFSET);
216 int y = dispi_read(VBE_DISPI_INDEX_Y_OFFSET);
217 return x * bpp / 8 + linelength * y;
218}
219
220int
221bochsvga_set_displaystart(struct vgamode_s *vmode_g, int val)
222{
223 stdvga_set_displaystart(vmode_g, val);
Paolo Bonzini9c291482015-01-01 21:27:46 +0100224 if (bochsvga_dispi_enabled()) {
Gerd Hoffmann53663502013-09-05 10:16:18 +0200225 int bpp = vga_bpp(vmode_g);
226 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
Kevin O'Connor06c6d472013-11-30 11:45:46 -0500227 if (!linelength)
228 return 0;
Gerd Hoffmann53663502013-09-05 10:16:18 +0200229 dispi_write(VBE_DISPI_INDEX_X_OFFSET, (val % linelength) * 8 / bpp);
230 dispi_write(VBE_DISPI_INDEX_Y_OFFSET, val / linelength);
231 }
Kevin O'Connord61fc532012-01-27 20:37:45 -0500232 return 0;
233}
234
Kevin O'Connore737b172012-02-04 11:08:39 -0500235int
236bochsvga_get_dacformat(struct vgamode_s *vmode_g)
237{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100238 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200239 return stdvga_get_dacformat(vmode_g);
Kevin O'Connore737b172012-02-04 11:08:39 -0500240 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
241 return (en & VBE_DISPI_8BIT_DAC) ? 8 : 6;
242}
243
244int
245bochsvga_set_dacformat(struct vgamode_s *vmode_g, int val)
246{
Paolo Bonzini9c291482015-01-01 21:27:46 +0100247 if (!bochsvga_dispi_enabled())
Gerd Hoffmann53663502013-09-05 10:16:18 +0200248 return stdvga_set_dacformat(vmode_g, val);
Kevin O'Connore737b172012-02-04 11:08:39 -0500249 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
250 if (val == 6)
251 en &= ~VBE_DISPI_8BIT_DAC;
252 else if (val == 8)
253 en |= VBE_DISPI_8BIT_DAC;
254 else
255 return -1;
256 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
257 return 0;
258}
259
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500260static int
261bochsvga_save_state(u16 seg, u16 *info)
Kevin O'Connor2469f892012-02-04 12:40:02 -0500262{
Kevin O'Connor2469f892012-02-04 12:40:02 -0500263 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
264 SET_FARVAR(seg, *info, en);
265 info++;
266 if (!(en & VBE_DISPI_ENABLED))
267 return 0;
268 int i;
269 for (i = VBE_DISPI_INDEX_XRES; i <= VBE_DISPI_INDEX_Y_OFFSET; i++)
270 if (i != VBE_DISPI_INDEX_ENABLE) {
271 u16 v = dispi_read(i);
272 SET_FARVAR(seg, *info, v);
273 info++;
274 }
275 return 0;
276}
277
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500278static int
279bochsvga_restore_state(u16 seg, u16 *info)
Kevin O'Connor2469f892012-02-04 12:40:02 -0500280{
Kevin O'Connor2469f892012-02-04 12:40:02 -0500281 u16 en = GET_FARVAR(seg, *info);
282 info++;
283 if (!(en & VBE_DISPI_ENABLED)) {
284 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
285 return 0;
286 }
287 int i;
288 for (i = VBE_DISPI_INDEX_XRES; i <= VBE_DISPI_INDEX_Y_OFFSET; i++)
289 if (i == VBE_DISPI_INDEX_ENABLE) {
290 dispi_write(i, en);
291 } else {
292 dispi_write(i, GET_FARVAR(seg, *info));
293 info++;
294 }
295 return 0;
296}
297
Kevin O'Connor20dc4192014-02-05 20:52:25 -0500298int
299bochsvga_save_restore(int cmd, u16 seg, void *data)
300{
301 int ret = stdvga_save_restore(cmd, seg, data);
302 if (ret < 0 || !(cmd & SR_REGISTERS) || !GET_GLOBAL(dispi_found))
303 return ret;
304
305 u16 *info = (data + ret);
306 if (cmd & SR_SAVE)
307 bochsvga_save_state(seg, info);
308 if (cmd & SR_RESTORE)
309 bochsvga_restore_state(seg, info);
310 return ret + (VBE_DISPI_INDEX_Y_OFFSET-VBE_DISPI_INDEX_XRES+1)*sizeof(u16);
311}
312
Kevin O'Connor933bb762012-02-01 21:54:55 -0500313
314/****************************************************************
315 * Mode setting
316 ****************************************************************/
317
Kevin O'Connor5108c692011-12-31 19:13:45 -0500318int
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500319bochsvga_set_mode(struct vgamode_s *vmode_g, int flags)
Julian Pidancet87879e22011-12-19 05:08:00 +0000320{
Gerd Hoffmann53663502013-09-05 10:16:18 +0200321 if (GET_GLOBAL(dispi_found))
322 dispi_write(VBE_DISPI_INDEX_ENABLE, VBE_DISPI_DISABLED);
Kevin O'Connorc8845022012-01-31 22:51:56 -0500323 if (! is_bochsvga_mode(vmode_g))
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500324 return stdvga_set_mode(vmode_g, flags);
Gerd Hoffmann53663502013-09-05 10:16:18 +0200325 if (!GET_GLOBAL(dispi_found))
326 return -1;
Kevin O'Connor5108c692011-12-31 19:13:45 -0500327
Kevin O'Connor5b6936e2013-11-29 18:43:35 -0500328 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
329 if (memmodel == MM_PLANAR)
Kevin O'Connore6bc4c12012-01-21 11:26:37 -0500330 stdvga_set_mode(stdvga_find_mode(0x6a), 0);
Kevin O'Connor5b6936e2013-11-29 18:43:35 -0500331 if (memmodel == MM_PACKED && !(flags & MF_NOPALETTE))
332 stdvga_set_packed_palette();
Julian Pidancet87879e22011-12-19 05:08:00 +0000333
Kevin O'Connor5b6936e2013-11-29 18:43:35 -0500334 dispi_write(VBE_DISPI_INDEX_BPP, GET_GLOBAL(vmode_g->depth));
Kevin O'Connor3339c052012-01-13 20:00:35 -0500335 u16 width = GET_GLOBAL(vmode_g->width);
336 u16 height = GET_GLOBAL(vmode_g->height);
337 dispi_write(VBE_DISPI_INDEX_XRES, width);
338 dispi_write(VBE_DISPI_INDEX_YRES, height);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000339 dispi_write(VBE_DISPI_INDEX_BANK, 0);
Kevin O'Connorc8845022012-01-31 22:51:56 -0500340 u16 bf = ((flags & MF_NOCLEARMEM ? VBE_DISPI_NOCLEARMEM : 0)
341 | (flags & MF_LINEARFB ? VBE_DISPI_LFB_ENABLED : 0));
342 dispi_write(VBE_DISPI_INDEX_ENABLE, VBE_DISPI_ENABLED | bf);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000343
344 /* VGA compat setup */
Kevin O'Connor184705f2012-01-14 22:17:43 -0500345 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
346 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
347 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
Kevin O'Connorc8845022012-01-31 22:51:56 -0500348 stdvga_set_linelength(vmode_g, width);
Kevin O'Connor184705f2012-01-14 22:17:43 -0500349 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
350 u8 v = 0;
351 if ((height - 1) & 0x0100)
352 v |= 0x02;
353 if ((height - 1) & 0x0200)
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000354 v |= 0x40;
Kevin O'Connor184705f2012-01-14 22:17:43 -0500355 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000356
Kevin O'Connor184705f2012-01-14 22:17:43 -0500357 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
358 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
359 stdvga_attr_mask(0x10, 0x00, 0x01);
360 stdvga_grdc_write(0x06, 0x05);
361 stdvga_sequ_write(0x02, 0x0f);
Kevin O'Connor5b6936e2013-11-29 18:43:35 -0500362 if (memmodel != MM_PLANAR) {
Kevin O'Connor184705f2012-01-14 22:17:43 -0500363 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
364 stdvga_attr_mask(0x10, 0x00, 0x40);
365 stdvga_sequ_mask(0x04, 0x00, 0x08);
366 stdvga_grdc_mask(0x05, 0x20, 0x40);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000367 }
David Woodhouse0069a312013-02-08 15:50:54 +0000368 stdvga_attrindex_write(0x20);
Julian Pidancet8bd766f2011-12-19 05:08:01 +0000369
Kevin O'Connor5108c692011-12-31 19:13:45 -0500370 return 0;
Julian Pidancet87879e22011-12-19 05:08:00 +0000371}
Kevin O'Connor933bb762012-02-01 21:54:55 -0500372
373
374/****************************************************************
375 * Init
376 ****************************************************************/
377
378int
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500379bochsvga_setup(void)
Kevin O'Connor933bb762012-02-01 21:54:55 -0500380{
Kevin O'Connord83c87b2013-01-21 01:14:12 -0500381 int ret = stdvga_setup();
Kevin O'Connor933bb762012-02-01 21:54:55 -0500382 if (ret)
383 return ret;
384
385 /* Sanity checks */
386 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
387 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
Gerd Hoffmann53663502013-09-05 10:16:18 +0200388 dprintf(1, "No VBE DISPI interface detected, falling back to stdvga\n");
389 return 0;
Kevin O'Connor933bb762012-02-01 21:54:55 -0500390 }
391
392 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
Gerd Hoffmann53663502013-09-05 10:16:18 +0200393 SET_VGA(dispi_found, 1);
Kevin O'Connor933bb762012-02-01 21:54:55 -0500394
Kevin O'Connorcfd7ef92012-02-02 22:52:17 -0500395 if (GET_GLOBAL(HaveRunInit))
396 return 0;
397
Kevin O'Connor933bb762012-02-01 21:54:55 -0500398 u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
399 int bdf = GET_GLOBAL(VgaBDF);
400 if (CONFIG_VGA_PCI && bdf >= 0) {
Gerd Hoffmann5d598772013-12-12 14:55:14 +0100401 u16 vendor = pci_config_readw(bdf, PCI_VENDOR_ID);
402 int barid;
403 switch (vendor) {
404 case 0x15ad: /* qemu vmware vga */
Kevin O'Connor933bb762012-02-01 21:54:55 -0500405 barid = 1;
Gerd Hoffmann5d598772013-12-12 14:55:14 +0100406 break;
Gerd Hoffmann87f848e2015-04-08 10:36:22 +0200407 default: /* stdvga, qxl, virtio */
Gerd Hoffmann5d598772013-12-12 14:55:14 +0100408 barid = 0;
409 break;
Kevin O'Connor933bb762012-02-01 21:54:55 -0500410 }
Gerd Hoffmann5d598772013-12-12 14:55:14 +0100411 u32 bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_0 + barid * 4);
Kevin O'Connor933bb762012-02-01 21:54:55 -0500412 lfb_addr = bar & PCI_BASE_ADDRESS_MEM_MASK;
413 dprintf(1, "VBE DISPI: bdf %02x:%02x.%x, bar %d\n", pci_bdf_to_bus(bdf)
414 , pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf), barid);
415 }
416
417 SET_VGA(VBE_framebuffer, lfb_addr);
418 u32 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K) * 64 * 1024;
419 SET_VGA(VBE_total_memory, totalmem);
Kevin O'Connor49ddd9e2012-09-04 13:16:36 -0400420 SET_VGA(VBE_win_granularity, 64);
Kevin O'Connor933bb762012-02-01 21:54:55 -0500421 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
422
423 dprintf(1, "VBE DISPI: lfb_addr=%x, size %d MB\n",
Gerd Hoffmann091dd172012-02-06 15:51:43 +0100424 lfb_addr, totalmem >> 20);
Kevin O'Connor933bb762012-02-01 21:54:55 -0500425
426 // Validate modes
427 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
428 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
429 u16 max_xres = dispi_read(VBE_DISPI_INDEX_XRES);
430 u16 max_bpp = dispi_read(VBE_DISPI_INDEX_BPP);
431 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
432 struct bochsvga_mode *m = bochsvga_modes;
433 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++) {
434 u16 width = GET_GLOBAL(m->info.width);
435 u16 height = GET_GLOBAL(m->info.height);
436 u8 depth = GET_GLOBAL(m->info.depth);
437 u32 mem = (height * DIV_ROUND_UP(width * vga_bpp(&m->info), 8)
Kevin O'Connor68f56aa2013-09-10 10:41:33 -0400438 * stdvga_vram_ratio(&m->info));
Kevin O'Connor933bb762012-02-01 21:54:55 -0500439
440 if (width > max_xres || depth > max_bpp || mem > totalmem) {
441 dprintf(1, "Removing mode %x\n", GET_GLOBAL(m->mode));
442 SET_VGA(m->mode, 0xffff);
443 }
444 }
445
446 return 0;
447}