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Kevin O'Connorf076a3e2008-02-25 22:25:15 -05001// 16bit code to handle system clocks.
2//
Kevin O'Connorabf31d32010-07-26 22:33:54 -04003// Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05004// Copyright (C) 2002 MandrakeSoft S.A.
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05007
Kevin O'Connor9521e262008-07-04 13:04:29 -04008#include "biosvar.h" // SET_BDA
Kevin O'Connorf076a3e2008-02-25 22:25:15 -05009#include "util.h" // debug_enter
10#include "disk.h" // floppy_tick
Kevin O'Connor4b60c002008-02-25 22:29:55 -050011#include "cmos.h" // inb_cmos
Kevin O'Connord21c0892008-11-26 17:02:43 -050012#include "pic.h" // eoi_pic1
Kevin O'Connor9521e262008-07-04 13:04:29 -040013#include "bregs.h" // struct bregs
Kevin O'Connor15157a32008-12-13 11:10:37 -050014#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor0e885762010-05-01 22:14:40 -040015#include "usb-hid.h" // usb_check_event
Kevin O'Connor4b60c002008-02-25 22:29:55 -050016
Kevin O'Connor5be04902008-05-18 17:12:06 -040017// RTC register flags
18#define RTC_A_UIP 0x80
Kevin O'Connorf3587592009-02-15 13:02:56 -050019
20#define RTC_B_SET 0x80
21#define RTC_B_PIE 0x40
22#define RTC_B_AIE 0x20
23#define RTC_B_UIE 0x10
24#define RTC_B_BIN 0x04
25#define RTC_B_24HR 0x02
26#define RTC_B_DSE 0x01
27
Kevin O'Connor5be04902008-05-18 17:12:06 -040028
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050029// Bits for PORT_PS2_CTRLB
30#define PPCB_T2GATE (1<<0)
31#define PPCB_SPKR (1<<1)
32#define PPCB_T2OUT (1<<5)
33
34// Bits for PORT_PIT_MODE
35#define PM_SEL_TIMER0 (0<<6)
36#define PM_SEL_TIMER1 (1<<6)
37#define PM_SEL_TIMER2 (2<<6)
38#define PM_SEL_READBACK (3<<6)
39#define PM_ACCESS_LATCH (0<<4)
40#define PM_ACCESS_LOBYTE (1<<4)
41#define PM_ACCESS_HIBYTE (2<<4)
42#define PM_ACCESS_WORD (3<<4)
43#define PM_MODE0 (0<<1)
44#define PM_MODE1 (1<<1)
45#define PM_MODE2 (2<<1)
46#define PM_MODE3 (3<<1)
47#define PM_MODE4 (4<<1)
48#define PM_MODE5 (5<<1)
49#define PM_CNT_BINARY (0<<0)
50#define PM_CNT_BCD (1<<0)
Kevin O'Connor745de852012-01-29 14:15:14 -050051#define PM_READ_COUNTER0 (1<<1)
52#define PM_READ_COUNTER1 (1<<2)
53#define PM_READ_COUNTER2 (1<<3)
54#define PM_READ_STATUSVALUE (0<<4)
55#define PM_READ_VALUE (1<<4)
56#define PM_READ_STATUS (2<<4)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050057
58
59/****************************************************************
60 * TSC timer
61 ****************************************************************/
62
Kevin O'Connor6aee52d2009-09-27 20:07:40 -040063#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050064
Kevin O'Connor372e0712009-09-09 09:51:31 -040065u32 cpu_khz VAR16VISIBLE;
Kevin O'Connor745de852012-01-29 14:15:14 -050066u8 no_tsc VAR16VISIBLE;
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050067
68static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -050069calibrate_tsc(void)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050070{
Kevin O'Connor745de852012-01-29 14:15:14 -050071 u32 eax, ebx, ecx, edx, cpuid_features = 0;
72 cpuid(0, &eax, &ebx, &ecx, &edx);
73 if (eax > 0)
74 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
75
76 if (!(cpuid_features & CPUID_TSC)) {
77 SET_GLOBAL(no_tsc, 1);
78 SET_GLOBAL(cpu_khz, PIT_TICK_RATE / 1000);
79 dprintf(3, "386/486 class CPU. Using TSC emulation\n");
80 return;
81 }
82
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -050083 // Setup "timer2"
84 u8 orig = inb(PORT_PS2_CTRLB);
85 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
86 /* binary, mode 0, LSB/MSB, Ch 2 */
87 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
88 /* LSB of ticks */
89 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
90 /* MSB of ticks */
91 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
92
93 u64 start = rdtscll();
94 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
95 ;
96 u64 end = rdtscll();
97
98 // Restore PORT_PS2_CTRLB
99 outb(orig, PORT_PS2_CTRLB);
100
101 // Store calibrated cpu khz.
102 u64 diff = end - start;
103 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
104 , (u32)start, (u32)end, (u32)diff);
105 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
Kevin O'Connor15157a32008-12-13 11:10:37 -0500106 SET_GLOBAL(cpu_khz, hz / 1000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500107
108 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
109}
110
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400111/* TSC emulation timekeepers */
112u64 TSC_8254 VARLOW;
113int Last_TSC_8254 VARLOW;
114
Kevin O'Connor745de852012-01-29 14:15:14 -0500115static u64
116emulate_tsc(void)
117{
Kevin O'Connor745de852012-01-29 14:15:14 -0500118 /* read timer 0 current count */
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400119 u64 ret = GET_LOW(TSC_8254);
120 /* readback mode has slightly shifted registers, works on all
121 * 8254, readback PIT0 latch */
Kevin O'Connor745de852012-01-29 14:15:14 -0500122 outb(PM_SEL_READBACK | PM_READ_VALUE | PM_READ_COUNTER0, PORT_PIT_MODE);
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400123 int cnt = (inb(PORT_PIT_COUNTER0) | (inb(PORT_PIT_COUNTER0) << 8));
124 int d = GET_LOW(Last_TSC_8254) - cnt;
Kevin O'Connor745de852012-01-29 14:15:14 -0500125 /* Determine the ticks count from last invocation of this function */
126 ret += (d > 0) ? d : (PIT_TICK_INTERVAL + d);
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400127 SET_LOW(Last_TSC_8254, cnt);
128 SET_LOW(TSC_8254, ret);
Kevin O'Connor745de852012-01-29 14:15:14 -0500129 return ret;
130}
131
132static u64
133get_tsc(void)
134{
135 if (unlikely(GET_GLOBAL(no_tsc)))
136 return emulate_tsc();
137 return rdtscll();
138}
139
140int
141check_tsc(u64 end)
142{
143 return (s64)(get_tsc() - end) > 0;
144}
145
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500146static void
Kevin O'Connor89eb6242009-10-22 22:30:37 -0400147tscdelay(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500148{
Kevin O'Connor745de852012-01-29 14:15:14 -0500149 u64 start = get_tsc();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500150 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400151 while (!check_tsc(end))
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500152 cpu_relax();
153}
154
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400155static void
156tscsleep(u64 diff)
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500157{
Kevin O'Connor745de852012-01-29 14:15:14 -0500158 u64 start = get_tsc();
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400159 u64 end = start + diff;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400160 while (!check_tsc(end))
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400161 yield();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500162}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400163
164void ndelay(u32 count) {
165 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500166}
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400167void udelay(u32 count) {
168 tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
169}
170void mdelay(u32 count) {
171 tscdelay(count * GET_GLOBAL(cpu_khz));
172}
173
174void nsleep(u32 count) {
175 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
176}
177void usleep(u32 count) {
178 tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
179}
180void msleep(u32 count) {
181 tscsleep(count * GET_GLOBAL(cpu_khz));
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500182}
183
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500184// Return the TSC value that is 'msecs' time in the future.
185u64
186calc_future_tsc(u32 msecs)
187{
Kevin O'Connor15157a32008-12-13 11:10:37 -0500188 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor745de852012-01-29 14:15:14 -0500189 return get_tsc() + ((u64)khz * msecs);
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500190}
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400191u64
192calc_future_tsc_usec(u32 usecs)
193{
194 u32 khz = GET_GLOBAL(cpu_khz);
Kevin O'Connor745de852012-01-29 14:15:14 -0500195 return get_tsc() + ((u64)(khz/1000) * usecs);
Kevin O'Connor1c46a542009-10-17 23:53:32 -0400196}
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500197
Kevin O'Connor5be04902008-05-18 17:12:06 -0400198
199/****************************************************************
200 * Init
201 ****************************************************************/
202
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500203static int
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500204rtc_updating(void)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500205{
206 // This function checks to see if the update-in-progress bit
207 // is set in CMOS Status Register A. If not, it returns 0.
208 // If it is set, it tries to wait until there is a transition
209 // to 0, and will return 0 if such a transition occurs. A -1
210 // is returned only after timing out. The maximum period
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500211 // that this bit should be set is constrained to (1984+244)
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500212 // useconds, but we wait for longer just to be sure.
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500213
Kevin O'Connorf3587592009-02-15 13:02:56 -0500214 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500215 return 0;
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500216 u64 end = calc_future_tsc(15);
217 for (;;) {
Kevin O'Connorf3587592009-02-15 13:02:56 -0500218 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500219 return 0;
Kevin O'Connor144817b2010-05-23 10:46:49 -0400220 if (check_tsc(end))
Kevin O'Connor11cc6622010-03-13 23:04:41 -0500221 // update-in-progress never transitioned to 0
222 return -1;
223 yield();
224 }
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500225}
226
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500227static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500228pit_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400229{
230 // timer0: binary count, 16bit count, mode 2
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500231 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400232 // maximum count of 0000H = 18.2Hz
233 outb(0x0, PORT_PIT_COUNTER0);
234 outb(0x0, PORT_PIT_COUNTER0);
235}
236
Kevin O'Connorf3587592009-02-15 13:02:56 -0500237static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500238init_rtc(void)
Kevin O'Connorf3587592009-02-15 13:02:56 -0500239{
Kevin O'Connor4f5586c2009-02-16 10:14:10 -0500240 outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
Kevin O'Connorf3587592009-02-15 13:02:56 -0500241 u8 regB = inb_cmos(CMOS_STATUS_B);
242 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
243 inb_cmos(CMOS_STATUS_C);
244 inb_cmos(CMOS_STATUS_D);
245}
246
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400247static u32
248bcd2bin(u8 val)
249{
250 return (val & 0xf) + ((val >> 4) * 10);
251}
252
253void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500254timer_setup(void)
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400255{
Kevin O'Connor35192dd2008-06-08 19:18:33 -0400256 dprintf(3, "init timer\n");
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500257 calibrate_tsc();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400258 pit_setup();
259
Kevin O'Connorf3587592009-02-15 13:02:56 -0500260 init_rtc();
Kevin O'Connor4e6c9702008-12-13 10:45:50 -0500261 rtc_updating();
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400262 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400263 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400264 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400265 u32 ticks = (hours * 60 + minutes) * 60 + seconds;
266 ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400267 SET_BDA(timer_counter, ticks);
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400268
Kevin O'Connorcc9e1bf2010-07-28 21:31:38 -0400269 enable_hwirq(0, FUNC16(entry_08));
270 enable_hwirq(8, FUNC16(entry_70));
Kevin O'Connore6eb3f52008-04-13 17:37:41 -0400271}
272
Kevin O'Connor5be04902008-05-18 17:12:06 -0400273
274/****************************************************************
275 * Standard clock functions
276 ****************************************************************/
277
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400278#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
279
280// Calculate the timer value at 'count' number of full timer ticks in
281// the future.
282u32
283calc_future_timer_ticks(u32 count)
284{
285 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
286}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400287
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400288// Return the timer value that is 'msecs' time in the future.
289u32
290calc_future_timer(u32 msecs)
291{
Kevin O'Connorbb685912010-05-23 12:40:40 -0400292 if (!msecs)
293 return GET_BDA(timer_counter);
Kevin O'Connorabf31d32010-07-26 22:33:54 -0400294 u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400295 u32 ticks = DIV_ROUND_UP(kticks, 1000);
296 return calc_future_timer_ticks(ticks);
297}
Kevin O'Connorbb685912010-05-23 12:40:40 -0400298
Kevin O'Connorb5cc2ca2010-05-23 11:38:53 -0400299// Check if the given timer value has passed.
300int
301check_timer(u32 end)
302{
303 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
304 < (TICKS_PER_DAY/2));
305}
306
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500307// get current clock count
308static void
309handle_1a00(struct bregs *regs)
310{
Kevin O'Connor68c51392010-03-13 22:23:44 -0500311 yield();
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500312 u32 ticks = GET_BDA(timer_counter);
313 regs->cx = ticks >> 16;
314 regs->dx = ticks;
315 regs->al = GET_BDA(timer_rollover);
316 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor6c781222008-03-09 12:19:23 -0400317 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500318}
319
320// Set Current Clock Count
321static void
322handle_1a01(struct bregs *regs)
323{
324 u32 ticks = (regs->cx << 16) | regs->dx;
325 SET_BDA(timer_counter, ticks);
326 SET_BDA(timer_rollover, 0); // reset flag
Kevin O'Connor15157a32008-12-13 11:10:37 -0500327 // XXX - should use set_code_success()?
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500328 regs->ah = 0;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400329 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500330}
331
332// Read CMOS Time
333static void
334handle_1a02(struct bregs *regs)
335{
336 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500337 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500338 return;
339 }
340
341 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
342 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
343 regs->ch = inb_cmos(CMOS_RTC_HOURS);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500344 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500345 regs->ah = 0;
346 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400347 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500348}
349
350// Set CMOS Time
351static void
352handle_1a03(struct bregs *regs)
353{
354 // Using a debugger, I notice the following masking/setting
355 // of bits in Status Register B, by setting Reg B to
356 // a few values and getting its value after INT 1A was called.
357 //
358 // try#1 try#2 try#3
359 // before 1111 1101 0111 1101 0000 0000
360 // after 0110 0010 0110 0010 0000 0010
361 //
362 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
363 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
364 if (rtc_updating()) {
365 init_rtc();
366 // fall through as if an update were not in progress
367 }
368 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
369 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
370 outb_cmos(regs->ch, CMOS_RTC_HOURS);
371 // Set Daylight Savings time enabled bit to requested value
Kevin O'Connorf3587592009-02-15 13:02:56 -0500372 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
373 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500374 outb_cmos(val8, CMOS_STATUS_B);
375 regs->ah = 0;
376 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400377 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500378}
379
380// Read CMOS Date
381static void
382handle_1a04(struct bregs *regs)
383{
384 regs->ah = 0;
385 if (rtc_updating()) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500386 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500387 return;
388 }
389 regs->cl = inb_cmos(CMOS_RTC_YEAR);
390 regs->dh = inb_cmos(CMOS_RTC_MONTH);
391 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500392 if (CONFIG_COREBOOT) {
393 if (regs->cl > 0x80)
394 regs->ch = 0x19;
395 else
396 regs->ch = 0x20;
397 } else {
398 regs->ch = inb_cmos(CMOS_CENTURY);
399 }
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500400 regs->al = regs->ch;
Kevin O'Connor6c781222008-03-09 12:19:23 -0400401 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500402}
403
404// Set CMOS Date
405static void
406handle_1a05(struct bregs *regs)
407{
408 // Using a debugger, I notice the following masking/setting
409 // of bits in Status Register B, by setting Reg B to
410 // a few values and getting its value after INT 1A was called.
411 //
412 // try#1 try#2 try#3 try#4
413 // before 1111 1101 0111 1101 0000 0010 0000 0000
414 // after 0110 1101 0111 1101 0000 0010 0000 0000
415 //
416 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
417 // My assumption: RegB = (RegB & 01111111b)
418 if (rtc_updating()) {
419 init_rtc();
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500420 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500421 return;
422 }
423 outb_cmos(regs->cl, CMOS_RTC_YEAR);
424 outb_cmos(regs->dh, CMOS_RTC_MONTH);
425 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
Kevin O'Connorf3587592009-02-15 13:02:56 -0500426 if (!CONFIG_COREBOOT)
427 outb_cmos(regs->ch, CMOS_CENTURY);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400428 // clear halt-clock bit
429 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500430 outb_cmos(val8, CMOS_STATUS_B);
431 regs->ah = 0;
432 regs->al = val8; // AL = val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400433 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500434}
435
436// Set Alarm Time in CMOS
437static void
438handle_1a06(struct bregs *regs)
439{
440 // Using a debugger, I notice the following masking/setting
441 // of bits in Status Register B, by setting Reg B to
442 // a few values and getting its value after INT 1A was called.
443 //
444 // try#1 try#2 try#3
445 // before 1101 1111 0101 1111 0000 0000
446 // after 0110 1111 0111 1111 0010 0000
447 //
448 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
449 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
450 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
451 regs->ax = 0;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500452 if (val8 & RTC_B_AIE) {
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500453 // Alarm interrupt enabled already
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500454 set_invalid(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500455 return;
456 }
457 if (rtc_updating()) {
458 init_rtc();
459 // fall through as if an update were not in progress
460 }
461 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
462 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
463 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500464 // enable Status Reg B alarm bit, clear halt clock bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400465 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
Kevin O'Connor6c781222008-03-09 12:19:23 -0400466 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500467}
468
469// Turn off Alarm
470static void
471handle_1a07(struct bregs *regs)
472{
473 // Using a debugger, I notice the following masking/setting
474 // of bits in Status Register B, by setting Reg B to
475 // a few values and getting its value after INT 1A was called.
476 //
477 // try#1 try#2 try#3 try#4
478 // before 1111 1101 0111 1101 0010 0000 0010 0010
479 // after 0100 0101 0101 0101 0000 0000 0000 0010
480 //
481 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
482 // My assumption: RegB = (RegB & 01010111b)
483 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
484 // clear clock-halt bit, disable alarm bit
Kevin O'Connor5be04902008-05-18 17:12:06 -0400485 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500486 regs->ah = 0;
487 regs->al = val8; // val last written to Reg B
Kevin O'Connor6c781222008-03-09 12:19:23 -0400488 set_success(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500489}
490
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500491// Unsupported
492static void
493handle_1aXX(struct bregs *regs)
494{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500495 set_unimplemented(regs);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500496}
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500497
498// INT 1Ah Time-of-day Service Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500499void VISIBLE16
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500500handle_1a(struct bregs *regs)
501{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400502 debug_enter(regs, DEBUG_HDL_1a);
Kevin O'Connor4b60c002008-02-25 22:29:55 -0500503 switch (regs->ah) {
504 case 0x00: handle_1a00(regs); break;
505 case 0x01: handle_1a01(regs); break;
506 case 0x02: handle_1a02(regs); break;
507 case 0x03: handle_1a03(regs); break;
508 case 0x04: handle_1a04(regs); break;
509 case 0x05: handle_1a05(regs); break;
510 case 0x06: handle_1a06(regs); break;
511 case 0x07: handle_1a07(regs); break;
512 case 0xb1: handle_1ab1(regs); break;
513 default: handle_1aXX(regs); break;
514 }
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500515}
516
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500517// INT 08h System Timer ISR Entry Point
Kevin O'Connor19786762008-03-05 21:09:59 -0500518void VISIBLE16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500519handle_08(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500520{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400521 debug_isr(DEBUG_ISR_08);
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500522
523 floppy_tick();
524
525 u32 counter = GET_BDA(timer_counter);
526 counter++;
527 // compare to one days worth of timer ticks at 18.2 hz
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400528 if (counter >= TICKS_PER_DAY) {
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500529 // there has been a midnight rollover at this point
530 counter = 0;
531 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
532 }
533
534 SET_BDA(timer_counter, counter);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500535
Kevin O'Connor0e885762010-05-01 22:14:40 -0400536 usb_check_event();
Kevin O'Connor114592f2009-09-28 21:32:08 -0400537
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500538 // chain to user timer tick INT #0x1c
Kevin O'Connora83ff552009-01-01 21:00:59 -0500539 u32 eax=0, flags;
540 call16_simpint(0x1c, &eax, &flags);
Kevin O'Connored128492008-03-11 11:14:59 -0400541
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400542 eoi_pic1();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500543}
544
Kevin O'Connor5be04902008-05-18 17:12:06 -0400545
546/****************************************************************
547 * Periodic timer
548 ****************************************************************/
549
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400550int RTCusers VARLOW;
551
Kevin O'Connorad901592009-12-13 11:25:25 -0500552void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500553useRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500554{
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400555 int count = GET_LOW(RTCusers);
556 SET_LOW(RTCusers, count+1);
Kevin O'Connorad901592009-12-13 11:25:25 -0500557 if (count)
558 return;
559 // Turn on the Periodic Interrupt timer
560 u8 bRegister = inb_cmos(CMOS_STATUS_B);
561 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
562}
563
564void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500565releaseRTC(void)
Kevin O'Connorad901592009-12-13 11:25:25 -0500566{
Kevin O'Connor9d254d42012-05-13 12:18:36 -0400567 int count = GET_LOW(RTCusers);
568 SET_LOW(RTCusers, count-1);
Kevin O'Connorad901592009-12-13 11:25:25 -0500569 if (count != 1)
570 return;
571 // Clear the Periodic Interrupt.
572 u8 bRegister = inb_cmos(CMOS_STATUS_B);
573 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
574}
575
Kevin O'Connor5be04902008-05-18 17:12:06 -0400576static int
Kevin O'Connor72743f12008-05-24 23:04:09 -0400577set_usertimer(u32 usecs, u16 seg, u16 offset)
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500578{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400579 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
580 return -1;
581
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500582 // Interval not already set.
583 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400584 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
Kevin O'Connor72743f12008-05-24 23:04:09 -0400585 SET_BDA(user_wait_timeout, usecs);
Kevin O'Connorad901592009-12-13 11:25:25 -0500586 useRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400587 return 0;
588}
589
590static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500591clear_usertimer(void)
Kevin O'Connor5be04902008-05-18 17:12:06 -0400592{
Kevin O'Connorad901592009-12-13 11:25:25 -0500593 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
594 return;
Kevin O'Connor5be04902008-05-18 17:12:06 -0400595 // Turn off status byte.
596 SET_BDA(rtc_wait_flag, 0);
Kevin O'Connorad901592009-12-13 11:25:25 -0500597 releaseRTC();
Kevin O'Connor5be04902008-05-18 17:12:06 -0400598}
599
Kevin O'Connor5be04902008-05-18 17:12:06 -0400600#define RET_ECLOCKINUSE 0x83
601
Kevin O'Connord21c0892008-11-26 17:02:43 -0500602// Wait for CX:DX microseconds
Kevin O'Connor5be04902008-05-18 17:12:06 -0400603void
604handle_1586(struct bregs *regs)
605{
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500606 // Use the rtc to wait for the specified time.
607 u8 statusflag = 0;
608 u32 count = (regs->cx << 16) | regs->dx;
609 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
610 if (ret) {
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500611 set_code_invalid(regs, RET_ECLOCKINUSE);
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500612 return;
613 }
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500614 while (!statusflag)
Kevin O'Connoree2efa72009-09-20 15:33:08 -0400615 wait_irq();
Kevin O'Connorbc2aecd2008-11-28 16:40:06 -0500616 set_success(regs);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400617}
618
619// Set Interval requested.
620static void
621handle_158300(struct bregs *regs)
622{
623 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
624 if (ret)
625 // Interval already set.
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500626 set_code_invalid(regs, RET_EUNSUPPORTED);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400627 else
628 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500629}
630
631// Clear interval requested
632static void
633handle_158301(struct bregs *regs)
634{
Kevin O'Connor5be04902008-05-18 17:12:06 -0400635 clear_usertimer();
636 set_success(regs);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500637}
638
639static void
640handle_1583XX(struct bregs *regs)
641{
Kevin O'Connordfefeb52009-12-13 13:04:17 -0500642 set_code_unimplemented(regs, RET_EUNSUPPORTED);
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500643 regs->al--;
Kevin O'Connorbdce35f2008-02-26 21:33:14 -0500644}
645
646void
647handle_1583(struct bregs *regs)
648{
649 switch (regs->al) {
650 case 0x00: handle_158300(regs); break;
651 case 0x01: handle_158301(regs); break;
652 default: handle_1583XX(regs); break;
653 }
654}
655
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400656#define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
657
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500658// int70h: IRQ8 - CMOS RTC
Kevin O'Connor19786762008-03-05 21:09:59 -0500659void VISIBLE16
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500660handle_70(void)
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500661{
Kevin O'Connor15c1f222008-06-12 22:59:43 -0400662 debug_isr(DEBUG_ISR_70);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500663
664 // Check which modes are enabled and have occurred.
665 u8 registerB = inb_cmos(CMOS_STATUS_B);
666 u8 registerC = inb_cmos(CMOS_STATUS_C);
667
Kevin O'Connor5be04902008-05-18 17:12:06 -0400668 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500669 goto done;
Kevin O'Connorf3587592009-02-15 13:02:56 -0500670 if (registerC & RTC_B_AIE) {
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500671 // Handle Alarm Interrupt.
Kevin O'Connora83ff552009-01-01 21:00:59 -0500672 u32 eax=0, flags;
673 call16_simpint(0x4a, &eax, &flags);
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500674 }
Kevin O'Connorf3587592009-02-15 13:02:56 -0500675 if (!(registerC & RTC_B_PIE))
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500676 goto done;
677
678 // Handle Periodic Interrupt.
679
Kevin O'Connorad901592009-12-13 11:25:25 -0500680 check_preempt();
681
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500682 if (!GET_BDA(rtc_wait_flag))
683 goto done;
684
685 // Wait Interval (Int 15, AH=83) active.
686 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400687 if (time < USEC_PER_RTC) {
Kevin O'Connor5be04902008-05-18 17:12:06 -0400688 // Done waiting - write to specified flag byte.
Kevin O'Connor9f985422009-09-09 11:34:39 -0400689 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
690 u16 ptr_seg = segoff.seg;
691 u8 *ptr_far = (u8*)(segoff.offset+0);
692 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
693 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
Kevin O'Connor5be04902008-05-18 17:12:06 -0400694
695 clear_usertimer();
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500696 } else {
697 // Continue waiting.
Kevin O'Connor6aee52d2009-09-27 20:07:40 -0400698 time -= USEC_PER_RTC;
Kevin O'Connor38fcbfe2008-02-25 22:30:47 -0500699 SET_BDA(user_wait_timeout, time);
700 }
701
702done:
Kevin O'Connorf54c1502008-06-14 15:56:16 -0400703 eoi_pic2();
Kevin O'Connorf076a3e2008-02-25 22:25:15 -0500704}