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Kevin O'Connor84ad59a2008-07-04 05:47:26 -04001// CPU count detection
2//
3// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2006 Fabrice Bellard
5//
Kevin O'Connorb1b7c2a2009-01-15 20:52:58 -05006// This file may be distributed under the terms of the GNU LGPLv3 license.
Kevin O'Connor84ad59a2008-07-04 05:47:26 -04007
8#include "util.h" // dprintf
Kevin O'Connor9521e262008-07-04 13:04:29 -04009#include "config.h" // CONFIG_*
Kevin O'Connor31bfad62008-12-16 23:50:52 -050010#include "cmos.h" // CMOS_BIOS_SMP_COUNT
Kevin O'Connora50ec8d2009-06-15 23:16:15 -040011#include "farptr.h" // ASSERT32
Kevin O'Connor84705852009-10-08 22:13:15 -040012#include "paravirt.h"
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040013
Kevin O'Connorf5c11612008-12-14 10:11:45 -050014#define APIC_ICR_LOW ((u8*)BUILD_APIC_ADDR + 0x300)
15#define APIC_SVR ((u8*)BUILD_APIC_ADDR + 0x0F0)
Kevin O'Connor19c1a762009-11-14 13:43:01 -050016#define APIC_LINT0 ((u8*)BUILD_APIC_ADDR + 0x350)
17#define APIC_LINT1 ((u8*)BUILD_APIC_ADDR + 0x360)
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040018
19#define APIC_ENABLED 0x0100
20
Kevin O'Connor372e0712009-09-09 09:51:31 -040021struct { u32 ecx, eax, edx; } smp_mtrr[16] VAR16VISIBLE;
22u32 smp_mtrr_count VAR16VISIBLE;
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040023
24void
25wrmsr_smp(u32 index, u64 val)
26{
27 wrmsr(index, val);
28 if (smp_mtrr_count >= ARRAY_SIZE(smp_mtrr))
29 return;
30 smp_mtrr[smp_mtrr_count].ecx = index;
31 smp_mtrr[smp_mtrr_count].eax = val;
32 smp_mtrr[smp_mtrr_count].edx = val >> 32;
33 smp_mtrr_count++;
34}
35
Kevin O'Connor372e0712009-09-09 09:51:31 -040036u32 CountCPUs VAR16VISIBLE;
Kevin O'Connor84705852009-10-08 22:13:15 -040037u32 MaxCountCPUs VAR16VISIBLE;
Kevin O'Connora06bfb62008-12-06 19:37:56 -050038extern void smp_ap_boot_code();
Kevin O'Connor4a754b32008-12-28 21:37:27 -050039ASM16(
Kevin O'Connora06bfb62008-12-06 19:37:56 -050040 " .global smp_ap_boot_code\n"
41 "smp_ap_boot_code:\n"
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040042
43 // Setup data segment
Kevin O'Connora06bfb62008-12-06 19:37:56 -050044 " movw $" __stringify(SEG_BIOS) ", %ax\n"
Kevin O'Connor484270d2008-08-17 10:50:57 -040045 " movw %ax, %ds\n"
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040046
47 // MTRR setup
48 " movl $smp_mtrr, %esi\n"
49 " movl smp_mtrr_count, %ebx\n"
50 "1:testl %ebx, %ebx\n"
51 " jz 2f\n"
52 " movl 0(%esi), %ecx\n"
53 " movl 4(%esi), %eax\n"
54 " movl 8(%esi), %edx\n"
55 " wrmsr\n"
56 " addl $12, %esi\n"
57 " decl %ebx\n"
58 " jmp 1b\n"
59 "2:\n"
60
61 // Increment the cpu counter
62 " lock incl CountCPUs\n"
63
Kevin O'Connor484270d2008-08-17 10:50:57 -040064 // Halt the processor.
Kevin O'Connor60b69992009-02-07 13:25:25 -050065 "1:hlt\n"
66 " jmp 1b\n"
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040067 );
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040068
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040069// find and initialize the CPUs by launching a SIPI to them
70void
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040071smp_probe(void)
72{
Kevin O'Connor0b60a062009-06-15 23:03:05 -040073 ASSERT32();
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040074 u32 eax, ebx, ecx, cpuid_features;
75 cpuid(1, &eax, &ebx, &ecx, &cpuid_features);
Kevin O'Connora06bfb62008-12-06 19:37:56 -050076 if (! (cpuid_features & CPUID_APIC)) {
77 // No apic - only the main cpu is present.
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040078 CountCPUs= 1;
79 return;
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040080 }
Kevin O'Connor84ad59a2008-07-04 05:47:26 -040081
Kevin O'Connora06bfb62008-12-06 19:37:56 -050082 // Init the counter.
Kevin O'Connore97ca7b2009-06-21 09:10:28 -040083 writel(&CountCPUs, 1);
Kevin O'Connora06bfb62008-12-06 19:37:56 -050084
85 // Setup jump trampoline to counter code.
86 u64 old = *(u64*)BUILD_AP_BOOT_ADDR;
87 // ljmpw $SEG_BIOS, $(smp_ap_boot_code - BUILD_BIOS_ADDR)
88 u64 new = (0xea | ((u64)SEG_BIOS<<24)
89 | (((u32)smp_ap_boot_code - BUILD_BIOS_ADDR) << 8));
90 *(u64*)BUILD_AP_BOOT_ADDR = new;
91
92 // enable local APIC
Kevin O'Connorf5c11612008-12-14 10:11:45 -050093 u32 val = readl(APIC_SVR);
94 writel(APIC_SVR, val | APIC_ENABLED);
Kevin O'Connora06bfb62008-12-06 19:37:56 -050095
Kevin O'Connor19c1a762009-11-14 13:43:01 -050096 if (! CONFIG_COREBOOT) {
97 /* Set LINT0 as Ext_INT, level triggered */
98 writel(APIC_LINT0, 0x8700);
99
100 /* Set LINT1 as NMI, level triggered */
101 writel(APIC_LINT1, 0x8400);
102 }
103
Kevin O'Connora06bfb62008-12-06 19:37:56 -0500104 // broadcast SIPI
Kevin O'Connorf5c11612008-12-14 10:11:45 -0500105 writel(APIC_ICR_LOW, 0x000C4500);
Kevin O'Connora06bfb62008-12-06 19:37:56 -0500106 u32 sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
Kevin O'Connorf5c11612008-12-14 10:11:45 -0500107 writel(APIC_ICR_LOW, 0x000C4600 | sipi_vector);
Kevin O'Connora06bfb62008-12-06 19:37:56 -0500108
109 // Wait for other CPUs to process the SIPI.
Kevin O'Connordb981072009-11-09 19:21:44 -0500110 if (CONFIG_COREBOOT) {
Kevin O'Connor10ad7992009-10-24 11:06:08 -0400111 msleep(10);
Kevin O'Connordb981072009-11-09 19:21:44 -0500112 } else {
113 u8 cmos_smp_count = inb_cmos(CMOS_BIOS_SMP_COUNT);
114 while (cmos_smp_count + 1 != readl(&CountCPUs))
115 ;
116 }
Kevin O'Connora06bfb62008-12-06 19:37:56 -0500117
118 // Restore memory.
Kevin O'Connora06bfb62008-12-06 19:37:56 -0500119 *(u64*)BUILD_AP_BOOT_ADDR = old;
120
Kevin O'Connor84705852009-10-08 22:13:15 -0400121 MaxCountCPUs = qemu_cfg_get_max_cpus();
122 if (!MaxCountCPUs || MaxCountCPUs < CountCPUs)
123 MaxCountCPUs = CountCPUs;
124
125 dprintf(1, "Found %d cpu(s) max supported %d cpu(s)\n", readl(&CountCPUs),
126 MaxCountCPUs);
Kevin O'Connor84ad59a2008-07-04 05:47:26 -0400127}
Kevin O'Connoracf13742008-11-29 11:19:19 -0500128
Kevin O'Connore97ca7b2009-06-21 09:10:28 -0400129// Reset variables to zero
Kevin O'Connoracf13742008-11-29 11:19:19 -0500130void
131smp_probe_setup(void)
132{
Kevin O'Connore97ca7b2009-06-21 09:10:28 -0400133 CountCPUs = 0;
134 smp_mtrr_count = 0;
Kevin O'Connoracf13742008-11-29 11:19:19 -0500135}