blob: 5591ad2097763f5655a6be0fb8edff8cac2b91b6 [file] [log] [blame]
Kevin O'Connor3471fdb2012-01-14 19:02:43 -05001// Standard VGA IO port access
2//
3// Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net>
4//
5// This file may be distributed under the terms of the GNU LGPLv3 license.
6
7#include "stdvga.h" // stdvga_pelmask_read
8#include "ioport.h" // inb
9
10u8
11stdvga_pelmask_read(void)
12{
13 return inb(VGAREG_PEL_MASK);
14}
15
16void
17stdvga_pelmask_write(u8 value)
18{
19 outb(value, VGAREG_PEL_MASK);
20}
21
22
23u8
24stdvga_misc_read(void)
25{
26 return inb(VGAREG_READ_MISC_OUTPUT);
27}
28
29void
30stdvga_misc_write(u8 value)
31{
32 outb(value, VGAREG_WRITE_MISC_OUTPUT);
33}
34
35void
36stdvga_misc_mask(u8 off, u8 on)
37{
38 stdvga_misc_write((stdvga_misc_read() & ~off) | on);
39}
40
41
42u8
43stdvga_sequ_read(u8 index)
44{
45 outb(index, VGAREG_SEQU_ADDRESS);
46 return inb(VGAREG_SEQU_DATA);
47}
48
49void
50stdvga_sequ_write(u8 index, u8 value)
51{
52 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
53}
54
55void
56stdvga_sequ_mask(u8 index, u8 off, u8 on)
57{
58 outb(index, VGAREG_SEQU_ADDRESS);
59 u8 v = inb(VGAREG_SEQU_DATA);
60 outb((v & ~off) | on, VGAREG_SEQU_DATA);
61}
62
63
64u8
65stdvga_grdc_read(u8 index)
66{
67 outb(index, VGAREG_GRDC_ADDRESS);
68 return inb(VGAREG_GRDC_DATA);
69}
70
71void
72stdvga_grdc_write(u8 index, u8 value)
73{
74 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
75}
76
77void
78stdvga_grdc_mask(u8 index, u8 off, u8 on)
79{
80 outb(index, VGAREG_GRDC_ADDRESS);
81 u8 v = inb(VGAREG_GRDC_DATA);
82 outb((v & ~off) | on, VGAREG_GRDC_DATA);
83}
84
85
86u8
87stdvga_crtc_read(u16 crtc_addr, u8 index)
88{
89 outb(index, crtc_addr);
90 return inb(crtc_addr + 1);
91}
92
93void
94stdvga_crtc_write(u16 crtc_addr, u8 index, u8 value)
95{
96 outw((value<<8) | index, crtc_addr);
97}
98
99void
100stdvga_crtc_mask(u16 crtc_addr, u8 index, u8 off, u8 on)
101{
102 outb(index, crtc_addr);
103 u8 v = inb(crtc_addr + 1);
104 outb((v & ~off) | on, crtc_addr + 1);
105}
106
107
108u8
109stdvga_attr_read(u8 index)
110{
111 inb(VGAREG_ACTL_RESET);
112 u8 orig = inb(VGAREG_ACTL_ADDRESS);
113 outb(index, VGAREG_ACTL_ADDRESS);
114 u8 v = inb(VGAREG_ACTL_READ_DATA);
115 inb(VGAREG_ACTL_RESET);
116 outb(orig, VGAREG_ACTL_ADDRESS);
117 return v;
118}
119
120void
121stdvga_attr_write(u8 index, u8 value)
122{
123 inb(VGAREG_ACTL_RESET);
124 u8 orig = inb(VGAREG_ACTL_ADDRESS);
125 outb(index, VGAREG_ACTL_ADDRESS);
126 outb(value, VGAREG_ACTL_WRITE_DATA);
127 outb(orig, VGAREG_ACTL_ADDRESS);
128}
129
130void
131stdvga_attr_mask(u8 index, u8 off, u8 on)
132{
133 inb(VGAREG_ACTL_RESET);
134 u8 orig = inb(VGAREG_ACTL_ADDRESS);
135 outb(index, VGAREG_ACTL_ADDRESS);
136 u8 v = inb(VGAREG_ACTL_READ_DATA);
137 outb((v & ~off) | on, VGAREG_ACTL_WRITE_DATA);
138 outb(orig, VGAREG_ACTL_ADDRESS);
139}
140
141u8
142stdvga_attrindex_read(void)
143{
144 inb(VGAREG_ACTL_RESET);
145 return inb(VGAREG_ACTL_ADDRESS);
146}
147
148void
149stdvga_attrindex_write(u8 value)
150{
151 inb(VGAREG_ACTL_RESET);
152 outb(value, VGAREG_ACTL_ADDRESS);
153}
154
155
156void
157stdvga_dac_read(u16 seg, u8 *data_far, u8 start, int count)
158{
159 outb(start, VGAREG_DAC_READ_ADDRESS);
160 while (count) {
161 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
162 data_far++;
163 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
164 data_far++;
165 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
166 data_far++;
167 count--;
168 }
169}
170
171void
172stdvga_dac_write(u16 seg, u8 *data_far, u8 start, int count)
173{
174 outb(start, VGAREG_DAC_WRITE_ADDRESS);
175 while (count) {
176 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
177 data_far++;
178 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
179 data_far++;
180 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
181 data_far++;
182 count--;
183 }
184}