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Kevin O'Connor3471fdb2012-01-14 19:02:43 -05001// Standard VGA driver code
Kevin O'Connorc0c7df62009-05-17 18:11:33 -04002//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (C) 2001-2008 the LGPL VGABios developers Team
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connor88ca7412011-12-31 04:24:20 -05008#include "stdvga.h" // stdvga_init
Kevin O'Connorc0c7df62009-05-17 18:11:33 -04009#include "ioport.h" // outb
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040010#include "farptr.h" // SET_FARVAR
Kevin O'Connorc990f272011-12-31 16:00:54 -050011#include "biosvar.h" // GET_GLOBAL
Kevin O'Connor2bec7d62011-12-31 04:31:16 -050012#include "util.h" // memcpy_far
Kevin O'Connor5108c692011-12-31 19:13:45 -050013#include "vbe.h" // VBE_RETURN_STATUS_FAILED
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040014
15
16/****************************************************************
17 * Attribute control
18 ****************************************************************/
19
Kevin O'Connora0ecb052009-05-18 23:34:00 -040020void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050021stdvga_set_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040022{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040023 u8 v1 = color & 0x0f;
24 if (v1 & 0x08)
25 v1 += 0x08;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050026 stdvga_attr_write(0x00, v1);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040027
28 int i;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050029 for (i = 1; i < 4; i++)
30 stdvga_attr_mask(i, 0x10, color & 0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040031}
32
33void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050034stdvga_set_overscan_border_color(u8 color)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040035{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050036 stdvga_attr_write(0x11, color);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040037}
38
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040039u8
Kevin O'Connor88ca7412011-12-31 04:24:20 -050040stdvga_get_overscan_border_color(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040041{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050042 return stdvga_attr_read(0x11);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040043}
44
45void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050046stdvga_set_palette(u8 palid)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040047{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040048 int i;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050049 for (i = 1; i < 4; i++)
50 stdvga_attr_mask(i, 0x01, palid & 0x01);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040051}
52
53void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050054stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040055{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040056 int i;
57 for (i = 0; i < 0x10; i++) {
Kevin O'Connor86d2e002012-01-14 22:17:07 -050058 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040059 data_far++;
60 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -050061 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040062}
63
64void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050065stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040066{
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040067 int i;
68 for (i = 0; i < 0x10; i++) {
Kevin O'Connor86d2e002012-01-14 22:17:07 -050069 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040070 data_far++;
71 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -050072 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040073}
74
75void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050076stdvga_toggle_intensity(u8 flag)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040077{
Kevin O'Connor86d2e002012-01-14 22:17:07 -050078 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040079}
80
81void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050082stdvga_select_video_dac_color_page(u8 flag, u8 data)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040083{
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040084 if (!(flag & 0x01)) {
85 // select paging mode
Kevin O'Connor86d2e002012-01-14 22:17:07 -050086 stdvga_attr_mask(0x10, 0x80, data << 7);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040087 return;
88 }
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040089 // select page
Kevin O'Connor86d2e002012-01-14 22:17:07 -050090 u8 val = stdvga_attr_read(0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040091 if (!(val & 0x80))
Kevin O'Connor8bc059e2009-05-17 21:19:36 -040092 data <<= 2;
93 data &= 0x0f;
Kevin O'Connor86d2e002012-01-14 22:17:07 -050094 stdvga_attr_write(0x14, data);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040095}
96
97void
Kevin O'Connor88ca7412011-12-31 04:24:20 -050098stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -040099{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500100 u8 val1 = stdvga_attr_read(0x10) >> 7;
101 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400102 if (!(val1 & 0x01))
103 val2 >>= 2;
Kevin O'Connor8bc059e2009-05-17 21:19:36 -0400104 *pmode = val1;
105 *curpage = val2;
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400106}
107
108
109/****************************************************************
110 * DAC control
111 ****************************************************************/
112
113void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500114stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400115{
116 /* XXX: check this */
117 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
118 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500119 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500120 stdvga_dac_read(seg, info->dac, 0, 256);
Kevin O'Connorca668642009-05-21 23:06:08 -0400121 SET_FARVAR(seg, info->color_select, 0);
122}
123
124void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500125stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400126{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500127 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500128 stdvga_dac_write(seg, info->dac, 0, 256);
Kevin O'Connorca668642009-05-21 23:06:08 -0400129 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
130}
131
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500132void
133stdvga_perform_gray_scale_summing(u16 start, u16 count)
134{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500135 stdvga_attrindex_write(0x00);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500136 int i;
137 for (i = start; i < start+count; i++) {
138 u8 rgb[3];
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500139 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500140
141 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
142 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
143 if (intensity > 0x3f)
144 intensity = 0x3f;
145
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500146 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500147 }
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500148 stdvga_attrindex_write(0x20);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500149}
150
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400151
152/****************************************************************
153 * Memory control
154 ****************************************************************/
155
156void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500157stdvga_set_text_block_specifier(u8 spec)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400158{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500159 stdvga_sequ_write(0x03, spec);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400160}
161
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500162
163/****************************************************************
164 * Font loading
165 ****************************************************************/
166
167static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500168get_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400169{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500170 stdvga_sequ_write(0x00, 0x01);
171 stdvga_sequ_write(0x02, 0x04);
172 stdvga_sequ_write(0x04, 0x07);
173 stdvga_sequ_write(0x00, 0x03);
174 stdvga_grdc_write(0x04, 0x02);
175 stdvga_grdc_write(0x05, 0x00);
176 stdvga_grdc_write(0x06, 0x04);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400177}
178
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500179static void
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500180release_font_access(void)
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400181{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500182 stdvga_sequ_write(0x00, 0x01);
183 stdvga_sequ_write(0x02, 0x03);
184 stdvga_sequ_write(0x04, 0x03);
185 stdvga_sequ_write(0x00, 0x03);
186 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
187 stdvga_grdc_write(0x06, v);
188 stdvga_grdc_write(0x04, 0x00);
189 stdvga_grdc_write(0x05, 0x10);
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400190}
191
Kevin O'Connor2bec7d62011-12-31 04:31:16 -0500192void
193stdvga_load_font(u16 seg, void *src_far, u16 count
194 , u16 start, u8 destflags, u8 fontsize)
195{
196 get_font_access();
197 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
198 void *dest_far = (void*)(blockaddr + start*32);
199 u16 i;
200 for (i = 0; i < count; i++)
201 memcpy_far(SEG_GRAPH, dest_far + i*32
202 , seg, src_far + i*fontsize, fontsize);
203 release_font_access();
204}
205
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400206
207/****************************************************************
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400208 * CRTC registers
209 ****************************************************************/
210
Kevin O'Connorc990f272011-12-31 16:00:54 -0500211u16
212stdvga_get_crtc(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400213{
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500214 if (stdvga_misc_read() & 1)
Kevin O'Connorc990f272011-12-31 16:00:54 -0500215 return VGAREG_VGA_CRTC_ADDRESS;
216 return VGAREG_MDA_CRTC_ADDRESS;
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400217}
218
219void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500220stdvga_set_cursor_shape(u8 start, u8 end)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400221{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500222 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500223 stdvga_crtc_write(crtc_addr, 0x0a, start);
224 stdvga_crtc_write(crtc_addr, 0x0b, end);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400225}
226
227void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500228stdvga_set_active_page(u16 address)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400229{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500230 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500231 stdvga_crtc_write(crtc_addr, 0x0c, address >> 8);
232 stdvga_crtc_write(crtc_addr, 0x0d, address);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400233}
234
235void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500236stdvga_set_cursor_pos(u16 address)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400237{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500238 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500239 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
240 stdvga_crtc_write(crtc_addr, 0x0f, address);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400241}
242
243void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500244stdvga_set_scan_lines(u8 lines)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400245{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500246 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400247}
248
249// Get vertical display end
250u16
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500251stdvga_get_vde(void)
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400252{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500253 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500254 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
255 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
Kevin O'Connora0ecb052009-05-18 23:34:00 -0400256 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
257 return vde;
258}
259
260
261/****************************************************************
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400262 * Save/Restore/Set state
Kevin O'Connorc0c7df62009-05-17 18:11:33 -0400263 ****************************************************************/
264
265void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500266stdvga_save_state(u16 seg, struct saveVideoHardware *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400267{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500268 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connorca668642009-05-21 23:06:08 -0400269 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
270 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
271 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500272 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
Kevin O'Connorca668642009-05-21 23:06:08 -0400273 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
274
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500275 int i;
276 for (i=0; i<4; i++)
277 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
278 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
Kevin O'Connorca668642009-05-21 23:06:08 -0400279
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500280 for (i=0; i<25; i++)
281 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400282
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500283 for (i=0; i<20; i++)
284 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400285
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500286 for (i=0; i<9; i++)
287 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
Kevin O'Connorca668642009-05-21 23:06:08 -0400288
289 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
290
291 /* XXX: read plane latches */
292 for (i=0; i<4; i++)
293 SET_FARVAR(seg, info->plane_latch[i], 0);
294}
295
296void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500297stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
Kevin O'Connorca668642009-05-21 23:06:08 -0400298{
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500299 int i;
300 for (i=0; i<4; i++)
301 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
302 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
Kevin O'Connorca668642009-05-21 23:06:08 -0400303
304 // Disable CRTC write protection
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500305 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
306 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
Kevin O'Connorca668642009-05-21 23:06:08 -0400307 // Set CRTC regs
308 for (i=0; i<25; i++)
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500309 if (i != 0x11)
310 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400311 // select crtc base address
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500312 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
Kevin O'Connorca668642009-05-21 23:06:08 -0400313
314 // enable write protection if needed
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500315 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400316
317 // Set Attribute Ctl
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500318 for (i=0; i<20; i++)
319 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
320 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
Kevin O'Connorca668642009-05-21 23:06:08 -0400321
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500322 for (i=0; i<9; i++)
323 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
Kevin O'Connorca668642009-05-21 23:06:08 -0400324
325 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
326 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
327 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
328 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
329}
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400330
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500331static void
332clear_screen(struct vgamode_s *vmode_g)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400333{
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500334 switch (GET_GLOBAL(vmode_g->memmodel)) {
Kevin O'Connord4398ad2012-01-01 12:32:53 -0500335 case MM_TEXT:
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500336 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
337 break;
Kevin O'Connord4398ad2012-01-01 12:32:53 -0500338 case MM_CGA:
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500339 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
340 break;
341 default:
342 // XXX - old code gets/sets/restores sequ register 2 to 0xf -
343 // but it should always be 0xf anyway.
344 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
345 }
346}
347
Kevin O'Connor5108c692011-12-31 19:13:45 -0500348int
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500349stdvga_set_mode(int mode, int flags)
350{
351 // find the entry in the video modes
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500352 struct vgamode_s *vmode_g = stdvga_find_mode(mode);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500353 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
354 if (!vmode_g)
Kevin O'Connor5108c692011-12-31 19:13:45 -0500355 return VBE_RETURN_STATUS_FAILED;
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500356 struct stdvga_mode_s *stdmode_g = container_of(
357 vmode_g, struct stdvga_mode_s, info);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500358
359 // if palette loading (bit 3 of modeset ctl = 0)
360 if (!(flags & MF_NOPALETTE)) { // Set the PEL mask
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500361 stdvga_pelmask_write(GET_GLOBAL(stdmode_g->pelmask));
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500362
363 // From which palette
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500364 u8 *palette_g = GET_GLOBAL(stdmode_g->dac);
365 u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3;
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500366
367 // Always 256*3 values
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500368 stdvga_dac_write(get_global_seg(), palette_g, 0, palsize);
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500369 int i;
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500370 for (i = palsize; i < 0x0100; i++) {
371 static u8 rgb[3] VAR16;
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500372 stdvga_dac_write(get_global_seg(), rgb, i, 1);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500373 }
374
375 if (flags & MF_GRAYSUM)
376 stdvga_perform_gray_scale_summing(0x00, 0x100);
377 }
378
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400379 // Set Attribute Ctl
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500380 u8 *regs = GET_GLOBAL(stdmode_g->actl_regs);
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500381 int i;
382 for (i = 0; i <= 0x13; i++)
383 stdvga_attr_write(i, GET_GLOBAL(regs[i]));
384 stdvga_attr_write(0x14, 0x00);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400385
386 // Set Sequencer Ctl
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500387 stdvga_sequ_write(0x00, 0x03);
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500388 regs = GET_GLOBAL(stdmode_g->sequ_regs);
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500389 for (i = 1; i <= 4; i++)
390 stdvga_sequ_write(i, GET_GLOBAL(regs[i - 1]));
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400391
392 // Set Grafx Ctl
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500393 regs = GET_GLOBAL(stdmode_g->grdc_regs);
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500394 for (i = 0; i <= 8; i++)
395 stdvga_grdc_write(i, GET_GLOBAL(regs[i]));
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400396
397 // Set CRTC address VGA or MDA
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500398 u8 miscreg = GET_GLOBAL(stdmode_g->miscreg);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400399 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
400 if (!(miscreg & 1))
401 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
402
403 // Disable CRTC write protection
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500404 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400405 // Set CRTC regs
Kevin O'Connor10dff3d2012-01-09 19:19:44 -0500406 regs = GET_GLOBAL(stdmode_g->crtc_regs);
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500407 for (i = 0; i <= 0x18; i++)
408 stdvga_crtc_write(crtc_addr, i, GET_GLOBAL(regs[i]));
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400409
410 // Set the misc register
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500411 stdvga_misc_write(miscreg);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400412
413 // Enable video
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500414 stdvga_attrindex_write(0x20);
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500415
416 // Clear screen
417 if (!(flags & MF_NOCLEARMEM))
418 clear_screen(vmode_g);
419
420 // Write the fonts in memory
421 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
Kevin O'Connord4398ad2012-01-01 12:32:53 -0500422 if (memmodel == MM_TEXT)
Kevin O'Connor821d6b42011-12-31 18:19:22 -0500423 stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16);
424
425 // Setup BDA variables
426 modeswitch_set_bda(mode, flags, vmode_g);
Kevin O'Connor5108c692011-12-31 19:13:45 -0500427
428 return 0;
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400429}
430
431
432/****************************************************************
433 * Misc
434 ****************************************************************/
435
436void
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500437stdvga_list_modes(u16 seg, u16 *dest, u16 *last)
438{
439 SET_FARVAR(seg, *dest, 0xffff);
440}
441
442void
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500443stdvga_enable_video_addressing(u8 disable)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400444{
445 u8 v = (disable & 1) ? 0x00 : 0x02;
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500446 stdvga_misc_mask(0x02, v);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400447}
448
Kevin O'Connor161d2012011-12-31 19:42:21 -0500449int
Kevin O'Connor88ca7412011-12-31 04:24:20 -0500450stdvga_init(void)
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400451{
452 // switch to color mode and enable CPU access 480 lines
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500453 stdvga_misc_write(0xc3);
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400454 // more than 64k 3C4/04
Kevin O'Connor86d2e002012-01-14 22:17:07 -0500455 stdvga_sequ_write(0x04, 0x02);
Kevin O'Connor161d2012011-12-31 19:42:21 -0500456
457 return 0;
Kevin O'Connor124b6f72009-05-25 00:44:29 -0400458}