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Kevin O'Connor1f2c3072009-05-06 23:35:59 -04001// QEMU Cirrus CLGD 54xx VGABIOS Extension.
2//
3// Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4// Copyright (c) 2004 Makoto Suzuki (suzu)
5//
6// This file may be distributed under the terms of the GNU LGPLv3 license.
7
Kevin O'Connor6f775082011-12-31 18:39:59 -05008#include "clext.h" // clext_init
9#include "vgabios.h" // VBE_VENDOR_STRING
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040010#include "biosvar.h" // GET_GLOBAL
11#include "util.h" // dprintf
Kevin O'Connor3c065362011-12-27 21:34:33 -050012#include "bregs.h" // struct bregs
Kevin O'Connor8f4c0192011-12-31 03:00:59 -050013#include "vbe.h" // struct vbe_info
Kevin O'Connored68e5b2011-12-31 04:15:12 -050014#include "stdvga.h" // VGAREG_SEQU_ADDRESS
Kevin O'Connor97cc3542012-01-14 16:59:21 -050015#include "pci.h" // pci_config_readl
16#include "pci_regs.h" // PCI_BASE_ADDRESS_0
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040017
Kevin O'Connore48a5372011-12-20 23:56:14 -050018
19/****************************************************************
20 * tables
21 ****************************************************************/
22
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040023/* VGA */
24static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
25static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
26static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
27
28/* extensions */
29static u16 cgraph_svgacolor[] VAR16 = {
30 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
31 0x0009,0x000a,0x000b,
32 0xffff
33};
34/* 640x480x8 */
35static u16 cseq_640x480x8[] VAR16 = {
36 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
37 0x580b,0x580c,0x580d,0x580e,
38 0x0412,0x0013,0x2017,
39 0x331b,0x331c,0x331d,0x331e,
40 0xffff
41};
42static u16 ccrtc_640x480x8[] VAR16 = {
43 0x2c11,
44 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
45 0x4009,0x000c,0x000d,
46 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
47 0x001a,0x221b,0x001d,
48 0xffff
49};
50/* 640x480x16 */
51static u16 cseq_640x480x16[] VAR16 = {
52 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
53 0x580b,0x580c,0x580d,0x580e,
54 0x0412,0x0013,0x2017,
55 0x331b,0x331c,0x331d,0x331e,
56 0xffff
57};
58static u16 ccrtc_640x480x16[] VAR16 = {
59 0x2c11,
60 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
61 0x4009,0x000c,0x000d,
62 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
63 0x001a,0x221b,0x001d,
64 0xffff
65};
66/* 640x480x24 */
67static u16 cseq_640x480x24[] VAR16 = {
68 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
69 0x580b,0x580c,0x580d,0x580e,
70 0x0412,0x0013,0x2017,
71 0x331b,0x331c,0x331d,0x331e,
72 0xffff
73};
74static u16 ccrtc_640x480x24[] VAR16 = {
75 0x2c11,
76 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
77 0x4009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -050078 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
79 0x001a,0x221b,0x001d,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -040080 0xffff
81};
82/* 800x600x8 */
83static u16 cseq_800x600x8[] VAR16 = {
84 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
85 0x230b,0x230c,0x230d,0x230e,
86 0x0412,0x0013,0x2017,
87 0x141b,0x141c,0x141d,0x141e,
88 0xffff
89};
90static u16 ccrtc_800x600x8[] VAR16 = {
91 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
92 0x6009,0x000c,0x000d,
93 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
94 0x001a,0x221b,0x001d,
95 0xffff
96};
97/* 800x600x16 */
98static u16 cseq_800x600x16[] VAR16 = {
99 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
100 0x230b,0x230c,0x230d,0x230e,
101 0x0412,0x0013,0x2017,
102 0x141b,0x141c,0x141d,0x141e,
103 0xffff
104};
105static u16 ccrtc_800x600x16[] VAR16 = {
106 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
107 0x6009,0x000c,0x000d,
108 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
109 0x001a,0x221b,0x001d,
110 0xffff
111};
112/* 800x600x24 */
113static u16 cseq_800x600x24[] VAR16 = {
114 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
115 0x230b,0x230c,0x230d,0x230e,
116 0x0412,0x0013,0x2017,
117 0x141b,0x141c,0x141d,0x141e,
118 0xffff
119};
120static u16 ccrtc_800x600x24[] VAR16 = {
121 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
122 0x6009,0x000c,0x000d,
123 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
124 0x001a,0x321b,0x001d,
125 0xffff
126};
127/* 1024x768x8 */
128static u16 cseq_1024x768x8[] VAR16 = {
129 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
130 0x760b,0x760c,0x760d,0x760e,
131 0x0412,0x0013,0x2017,
132 0x341b,0x341c,0x341d,0x341e,
133 0xffff
134};
135static u16 ccrtc_1024x768x8[] VAR16 = {
136 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
137 0x6009,0x000c,0x000d,
138 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
139 0x001a,0x221b,0x001d,
140 0xffff
141};
142/* 1024x768x16 */
143static u16 cseq_1024x768x16[] VAR16 = {
144 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
145 0x760b,0x760c,0x760d,0x760e,
146 0x0412,0x0013,0x2017,
147 0x341b,0x341c,0x341d,0x341e,
148 0xffff
149};
150static u16 ccrtc_1024x768x16[] VAR16 = {
151 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
152 0x6009,0x000c,0x000d,
153 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
154 0x001a,0x321b,0x001d,
155 0xffff
156};
157/* 1024x768x24 */
158static u16 cseq_1024x768x24[] VAR16 = {
159 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
160 0x760b,0x760c,0x760d,0x760e,
161 0x0412,0x0013,0x2017,
162 0x341b,0x341c,0x341d,0x341e,
163 0xffff
164};
165static u16 ccrtc_1024x768x24[] VAR16 = {
166 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
167 0x6009,0x000c,0x000d,
168 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
169 0x001a,0x321b,0x001d,
170 0xffff
171};
172/* 1280x1024x8 */
173static u16 cseq_1280x1024x8[] VAR16 = {
174 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
175 0x760b,0x760c,0x760d,0x760e,
176 0x0412,0x0013,0x2017,
177 0x341b,0x341c,0x341d,0x341e,
178 0xffff
179};
180static u16 ccrtc_1280x1024x8[] VAR16 = {
181 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
182 0x6009,0x000c,0x000d,
183 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
184 0x001a,0x221b,0x001d,
185 0xffff
186};
187/* 1280x1024x16 */
188static u16 cseq_1280x1024x16[] VAR16 = {
189 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
190 0x760b,0x760c,0x760d,0x760e,
191 0x0412,0x0013,0x2017,
192 0x341b,0x341c,0x341d,0x341e,
193 0xffff
194};
195static u16 ccrtc_1280x1024x16[] VAR16 = {
196 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
197 0x6009,0x000c,0x000d,
198 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
199 0x001a,0x321b,0x001d,
200 0xffff
201};
202
203/* 1600x1200x8 */
204static u16 cseq_1600x1200x8[] VAR16 = {
205 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
206 0x760b,0x760c,0x760d,0x760e,
207 0x0412,0x0013,0x2017,
208 0x341b,0x341c,0x341d,0x341e,
209 0xffff
210};
211static u16 ccrtc_1600x1200x8[] VAR16 = {
212 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
213 0x6009,0x000c,0x000d,
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500214 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400215 0x001a,0x221b,0x001d,
216 0xffff
217};
218
Kevin O'Connor643290f2012-01-13 22:08:52 -0500219struct cirrus_mode_s {
220 u16 mode;
221 struct vgamode_s info;
222
223 u16 hidden_dac; /* 0x3c6 */
224 u16 *seq; /* 0x3c4 */
225 u16 *graph; /* 0x3ce */
226 u16 *crtc; /* 0x3d4 */
227};
228
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400229static struct cirrus_mode_s cirrus_modes[] VAR16 = {
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500230 {0x5f,{MM_PACKED,640,480,8},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500231 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500232 {0x64,{MM_DIRECT,640,480,16},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500233 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500234 {0x66,{MM_DIRECT,640,480,15},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500235 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500236 {0x71,{MM_DIRECT,640,480,24},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500237 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400238
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500239 {0x5c,{MM_PACKED,800,600,8},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500240 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500241 {0x65,{MM_DIRECT,800,600,16},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500242 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500243 {0x67,{MM_DIRECT,800,600,15},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500244 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400245
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500246 {0x60,{MM_PACKED,1024,768,8},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500247 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500248 {0x74,{MM_DIRECT,1024,768,16},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500249 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500250 {0x68,{MM_DIRECT,1024,768,15},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500251 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400252
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500253 {0x78,{MM_DIRECT,800,600,24},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500254 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500255 {0x79,{MM_DIRECT,1024,768,24},0xe5,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500256 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400257
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500258 {0x6d,{MM_PACKED,1280,1024,8},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500259 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500260 {0x69,{MM_DIRECT,1280,1024,15},0xf0,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500261 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500262 {0x75,{MM_DIRECT,1280,1024,16},0xe1,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500263 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400264
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500265 {0x7b,{MM_PACKED,1600,1200,8},0x00,
Kevin O'Connor643290f2012-01-13 22:08:52 -0500266 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400267};
268
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500269static struct cirrus_mode_s mode_switchback VAR16 =
Kevin O'Connor643290f2012-01-13 22:08:52 -0500270 {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
271
272static struct {
273 u16 vesamode, mode;
274} cirrus_vesa_modelist[] VAR16 = {
275 // 640x480x8
276 { 0x101, 0x5f },
277 // 640x480x15
278 { 0x110, 0x66 },
279 // 640x480x16
280 { 0x111, 0x64 },
281 // 640x480x24
282 { 0x112, 0x71 },
283 // 800x600x8
284 { 0x103, 0x5c },
285 // 800x600x15
286 { 0x113, 0x67 },
287 // 800x600x16
288 { 0x114, 0x65 },
289 // 800x600x24
290 { 0x115, 0x78 },
291 // 1024x768x8
292 { 0x105, 0x60 },
293 // 1024x768x15
294 { 0x116, 0x68 },
295 // 1024x768x16
296 { 0x117, 0x74 },
297 // 1024x768x24
298 { 0x118, 0x79 },
299 // 1280x1024x8
300 { 0x107, 0x6d },
301 // 1280x1024x15
302 { 0x119, 0x69 },
303 // 1280x1024x16
304 { 0x11a, 0x75 },
305};
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500306
Kevin O'Connore48a5372011-12-20 23:56:14 -0500307
308/****************************************************************
309 * helper functions
310 ****************************************************************/
311
Kevin O'Connor643290f2012-01-13 22:08:52 -0500312static u16
313cirrus_vesamode_to_mode(u16 vesamode)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400314{
Kevin O'Connor643290f2012-01-13 22:08:52 -0500315 int i;
316 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
317 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
318 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
319 return 0;
320}
321
322static struct cirrus_mode_s *
323cirrus_get_modeentry(int mode)
324{
325 int transmode = cirrus_vesamode_to_mode(mode);
326 if (transmode)
327 mode = transmode;
Kevin O'Connor4f792742009-05-16 14:55:01 -0400328 struct cirrus_mode_s *table_g = cirrus_modes;
329 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
330 u16 tmode = GET_GLOBAL(table_g->mode);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400331 if (tmode == mode)
Kevin O'Connor4f792742009-05-16 14:55:01 -0400332 return table_g;
333 table_g++;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400334 }
335 return NULL;
336}
337
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500338struct vgamode_s *
339clext_find_mode(int mode)
340{
341 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
342 if (table_g)
343 return &table_g->info;
344 return stdvga_find_mode(mode);
345}
346
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400347static void
348cirrus_switch_mode_setregs(u16 *data, u16 port)
349{
350 for (;;) {
351 u16 val = GET_GLOBAL(*data);
352 if (val == 0xffff)
353 return;
354 outw(val, port);
355 data++;
356 }
357}
358
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400359static void
360cirrus_switch_mode(struct cirrus_mode_s *table)
361{
362 // Unlock cirrus special
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400363 outw(0x1206, VGAREG_SEQU_ADDRESS);
364 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
365 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
Kevin O'Connorc990f272011-12-31 16:00:54 -0500366 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400367
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400368 outb(0x00, VGAREG_PEL_MASK);
369 inb(VGAREG_PEL_MASK);
370 inb(VGAREG_PEL_MASK);
371 inb(VGAREG_PEL_MASK);
372 inb(VGAREG_PEL_MASK);
373 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
374 outb(0xff, VGAREG_PEL_MASK);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400375
Kevin O'Connorc4a0b972012-01-09 20:21:31 -0500376 u8 memmodel = GET_GLOBAL(table->info.memmodel);
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500377 u8 on = 0;
Kevin O'Connorb451f182012-01-02 02:23:17 -0500378 if (memmodel == MM_PLANAR)
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500379 on = 0x41;
Kevin O'Connorb451f182012-01-02 02:23:17 -0500380 else if (memmodel != MM_TEXT)
Kevin O'Connor3471fdb2012-01-14 19:02:43 -0500381 on = 0x01;
382 stdvga_attr_mask(0x10, 0x01, on);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400383}
384
Kevin O'Connore48a5372011-12-20 23:56:14 -0500385static u8
386cirrus_get_memsize(void)
387{
388 // get DRAM band width
389 outb(0x0f, VGAREG_SEQU_ADDRESS);
390 u8 v = inb(VGAREG_SEQU_DATA);
391 u8 x = (v >> 3) & 0x03;
392 if (x == 0x03) {
393 if (v & 0x80)
394 // 4MB
395 return 0x40;
396 // 2MB
397 return 0x20;
398 }
399 return 0x04 << x;
400}
401
402static void
403cirrus_enable_16k_granularity(void)
404{
405 outb(0x0b, VGAREG_GRDC_ADDRESS);
406 u8 v = inb(VGAREG_GRDC_DATA);
407 outb(v | 0x20, VGAREG_GRDC_DATA);
408}
409
410static void
411cirrus_clear_vram(u16 param)
412{
413 cirrus_enable_16k_granularity();
414 u8 count = cirrus_get_memsize() * 4;
415 u8 i;
416 for (i=0; i<count; i++) {
417 outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
418 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
419 }
420 outw(0x0009, VGAREG_GRDC_ADDRESS);
421}
422
423int
Kevin O'Connor5108c692011-12-31 19:13:45 -0500424clext_set_mode(int mode, int flags)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400425{
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500426 dprintf(1, "cirrus mode %x\n", mode);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400427 SET_BDA(vbe_mode, 0);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500428 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
Kevin O'Connor4f792742009-05-16 14:55:01 -0400429 if (table_g) {
Kevin O'Connore48a5372011-12-20 23:56:14 -0500430 cirrus_switch_mode(table_g);
Kevin O'Connor643290f2012-01-13 22:08:52 -0500431 if (!(flags & MF_LINEARFB))
432 cirrus_enable_16k_granularity();
Kevin O'Connor5108c692011-12-31 19:13:45 -0500433 if (!(flags & MF_NOCLEARMEM))
Kevin O'Connor643290f2012-01-13 22:08:52 -0500434 cirrus_clear_vram(0);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500435 SET_BDA(video_mode, mode);
Kevin O'Connor643290f2012-01-13 22:08:52 -0500436 SET_BDA(vbe_mode, mode | flags);
Kevin O'Connor5108c692011-12-31 19:13:45 -0500437 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400438 }
Kevin O'Connor2c8ba892012-01-02 10:51:26 -0500439 cirrus_switch_mode(&mode_switchback);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400440 dprintf(1, "cirrus mode switch regular\n");
Kevin O'Connor5108c692011-12-31 19:13:45 -0500441 return stdvga_set_mode(mode, flags);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400442}
443
444static int
Kevin O'Connor1ca05b02010-01-03 17:43:37 -0500445cirrus_check(void)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400446{
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400447 outw(0x9206, VGAREG_SEQU_ADDRESS);
448 return inb(VGAREG_SEQU_DATA) == 0x12;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400449}
450
Kevin O'Connore48a5372011-12-20 23:56:14 -0500451
452/****************************************************************
453 * extbios
454 ****************************************************************/
455
456static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500457clext_101280(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500458{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500459 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connore48a5372011-12-20 23:56:14 -0500460 outb(0x27, crtc_addr);
461 u8 v = inb(crtc_addr + 1);
462 if (v == 0xa0)
463 // 5430
464 regs->ax = 0x0032;
465 else if (v == 0xb8)
466 // 5446
467 regs->ax = 0x0039;
468 else
469 regs->ax = 0x00ff;
470 regs->bx = 0x00;
471 return;
472}
473
474static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500475clext_101281(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500476{
477 // XXX
478 regs->ax = 0x0100;
479}
480
481static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500482clext_101282(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500483{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500484 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connore48a5372011-12-20 23:56:14 -0500485 outb(0x27, crtc_addr);
486 regs->al = inb(crtc_addr + 1) & 0x03;
487 regs->ah = 0xAF;
488}
489
490static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500491clext_101285(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500492{
493 regs->al = cirrus_get_memsize();
494}
495
496static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500497clext_10129a(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500498{
499 regs->ax = 0x4060;
500 regs->cx = 0x1132;
501}
502
503extern void a0h_callback(void);
504ASM16(
505 // fatal: not implemented yet
506 "a0h_callback:"
507 "cli\n"
508 "hlt\n"
509 "retf");
510
511static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500512clext_1012a0(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500513{
514 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
515 regs->ah = (table_g ? 1 : 0);
516 regs->si = 0xffff;
517 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
518}
519
520static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500521clext_1012a1(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500522{
523 regs->bx = 0x0e00; // IBM 8512/8513, color
524}
525
526static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500527clext_1012a2(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500528{
529 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
530}
531
532static void
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500533clext_1012ae(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500534{
535 regs->al = 0x01; // High Refresh 75Hz
536}
537
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500538static void
539clext_1012XX(struct bregs *regs)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500540{
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500541 debug_stub(regs);
542}
543
544void
545clext_1012(struct bregs *regs)
546{
Kevin O'Connore48a5372011-12-20 23:56:14 -0500547 switch (regs->bl) {
Kevin O'Connore91ec7c2012-01-14 16:30:49 -0500548 case 0x80: clext_101280(regs); break;
549 case 0x81: clext_101281(regs); break;
550 case 0x82: clext_101282(regs); break;
551 case 0x85: clext_101285(regs); break;
552 case 0x9a: clext_10129a(regs); break;
553 case 0xa0: clext_1012a0(regs); break;
554 case 0xa1: clext_1012a1(regs); break;
555 case 0xa2: clext_1012a2(regs); break;
556 case 0xae: clext_1012ae(regs); break;
557 default: clext_1012XX(regs); break;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500558 }
559}
560
561
562/****************************************************************
563 * vesa calls
564 ****************************************************************/
565
Kevin O'Connor34203cd2012-01-09 20:55:31 -0500566void
567clext_list_modes(u16 seg, u16 *dest, u16 *last)
568{
569 int i;
570 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
571 SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
572 dest++;
573 }
574 stdvga_list_modes(seg, dest, last);
575}
576
Kevin O'Connore48a5372011-12-20 23:56:14 -0500577static u8
578cirrus_get_bpp_bytes(void)
579{
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500580 outb(0x07, VGAREG_SEQU_ADDRESS);
581 u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
582 if (v == 0x06)
583 v &= 0x02;
584 v >>= 1;
585 if (v != 0x04)
586 v++;
587 return v;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500588}
589
590static void
591cirrus_set_line_offset(u16 new_line_offset)
592{
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500593 new_line_offset /= 8;
Kevin O'Connorc990f272011-12-31 16:00:54 -0500594 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500595 outb(0x13, crtc_addr);
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500596 outb(new_line_offset, crtc_addr + 1);
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500597
598 outb(0x1b, crtc_addr);
599 u8 v = inb(crtc_addr + 1);
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500600 outb(((new_line_offset & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500601}
602
603static u16
604cirrus_get_line_offset(void)
605{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500606 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500607 outb(0x13, crtc_addr);
608 u8 reg13 = inb(crtc_addr + 1);
609 outb(0x1b, crtc_addr);
610 u8 reg1b = inb(crtc_addr + 1);
611
Kevin O'Connore19a68f2012-01-14 14:52:01 -0500612 return (((reg1b & 0x10) << 4) + reg13) * 8;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500613}
614
615static void
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500616cirrus_set_start_addr(u32 addr)
Kevin O'Connore48a5372011-12-20 23:56:14 -0500617{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500618 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500619 outb(0x0d, crtc_addr);
620 outb(addr, crtc_addr + 1);
621
622 outb(0x0c, crtc_addr);
623 outb(addr>>8, crtc_addr + 1);
624
625 outb(0x1d, crtc_addr);
626 u8 v = inb(crtc_addr + 1);
627 outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
628
629 outb(0x1b, crtc_addr);
630 v = inb(crtc_addr + 1);
631 outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
632 , crtc_addr + 1);
Kevin O'Connore48a5372011-12-20 23:56:14 -0500633}
634
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500635static u32
Kevin O'Connore48a5372011-12-20 23:56:14 -0500636cirrus_get_start_addr(void)
637{
Kevin O'Connorc990f272011-12-31 16:00:54 -0500638 u16 crtc_addr = stdvga_get_crtc();
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500639 outb(0x0c, crtc_addr);
640 u8 b2 = inb(crtc_addr + 1);
641
642 outb(0x0d, crtc_addr);
643 u8 b1 = inb(crtc_addr + 1);
644
645 outb(0x1b, crtc_addr);
646 u8 b3 = inb(crtc_addr + 1);
647
648 outb(0x1d, crtc_addr);
649 u8 b4 = inb(crtc_addr + 1);
650
651 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
652 | ((b4 & 0x80) << 12));
Kevin O'Connore48a5372011-12-20 23:56:14 -0500653}
Kevin O'Connore48a5372011-12-20 23:56:14 -0500654
655static void
Kevin O'Connore48a5372011-12-20 23:56:14 -0500656cirrus_vesa_05h(struct bregs *regs)
657{
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500658 if (regs->bl > 1)
659 goto fail;
660 if (regs->bh == 0) {
661 // set mempage
662 if (regs->dx >= 0x100)
663 goto fail;
664 outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
665 } else if (regs->bh == 1) {
666 // get mempage
667 outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
668 regs->dx = inb(VGAREG_GRDC_DATA);
669 } else
670 goto fail;
671
672 regs->ax = 0x004f;
673 return;
674fail:
675 regs->ax = 0x014f;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500676}
677
678static void
679cirrus_vesa_06h(struct bregs *regs)
680{
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500681 if (regs->bl > 2) {
682 regs->ax = 0x0100;
683 return;
684 }
685
686 if (regs->bl == 0x00) {
687 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
688 } else if (regs->bl == 0x02) {
689 cirrus_set_line_offset(regs->cx);
690 }
691
692 u32 v = cirrus_get_line_offset();
693 regs->cx = v / cirrus_get_bpp_bytes();
694 regs->bx = v;
695 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
696 regs->ax = 0x004f;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500697}
698
699static void
700cirrus_vesa_07h(struct bregs *regs)
701{
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500702 if (regs->bl == 0x80 || regs->bl == 0x00) {
703 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
704 + cirrus_get_line_offset() * regs->dx);
705 cirrus_set_start_addr(addr / 4);
706 } else if (regs->bl == 0x01) {
707 u32 addr = cirrus_get_start_addr() * 4;
708 u32 linelength = cirrus_get_line_offset();
709 regs->dx = addr / linelength;
710 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
711 } else {
712 regs->ax = 0x0100;
713 return;
714 }
715
716 regs->ax = 0x004f;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500717}
718
719static void
720cirrus_vesa_10h(struct bregs *regs)
721{
Kevin O'Connor8f4c0192011-12-31 03:00:59 -0500722 if (regs->bl == 0x00) {
723 regs->bx = 0x0f30;
724 regs->ax = 0x004f;
725 return;
726 }
727 if (regs->bl == 0x01) {
728 SET_BDA(vbe_flag, regs->bh);
729 regs->ax = 0x004f;
730 return;
731 }
732 if (regs->bl == 0x02) {
733 regs->bh = GET_BDA(vbe_flag);
734 regs->ax = 0x004f;
735 return;
736 }
737 regs->ax = 0x014f;
Kevin O'Connore48a5372011-12-20 23:56:14 -0500738}
739
740static void
741cirrus_vesa_not_handled(struct bregs *regs)
742{
743 debug_stub(regs);
744 regs->ax = 0x014f;
745}
746
747void
748cirrus_vesa(struct bregs *regs)
749{
750 switch (regs->al) {
Kevin O'Connore48a5372011-12-20 23:56:14 -0500751 case 0x05: cirrus_vesa_05h(regs); break;
752 case 0x06: cirrus_vesa_06h(regs); break;
753 case 0x07: cirrus_vesa_07h(regs); break;
754 case 0x10: cirrus_vesa_10h(regs); break;
755 default: cirrus_vesa_not_handled(regs); break;
756 }
757}
758
759
760/****************************************************************
761 * init
762 ****************************************************************/
763
Kevin O'Connor161d2012011-12-31 19:42:21 -0500764int
Kevin O'Connor6f775082011-12-31 18:39:59 -0500765clext_init(void)
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400766{
Kevin O'Connor161d2012011-12-31 19:42:21 -0500767 int ret = stdvga_init();
768 if (ret)
769 return ret;
770
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400771 dprintf(1, "cirrus init\n");
772 if (! cirrus_check())
Kevin O'Connor161d2012011-12-31 19:42:21 -0500773 return -1;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400774 dprintf(1, "cirrus init 2\n");
775
Kevin O'Connor97cc3542012-01-14 16:59:21 -0500776 SET_VGA(VBE_enabled, 1);
777 u32 lfb_addr = 0;
778 if (CONFIG_VGA_PCI)
779 lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
780 & PCI_BASE_ADDRESS_MEM_MASK);
781 SET_VGA(VBE_framebuffer, lfb_addr);
Kevin O'Connor643290f2012-01-13 22:08:52 -0500782 u16 totalmem = cirrus_get_memsize();
783 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
784 SET_VGA(VBE_win_granularity, 16);
785
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400786 // memory setup
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400787 outb(0x0f, VGAREG_SEQU_ADDRESS);
788 u8 v = inb(VGAREG_SEQU_DATA);
789 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400790 // set vga mode
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400791 outw(0x0007, VGAREG_SEQU_ADDRESS);
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400792 // reset bitblt
Kevin O'Connord9fc0a02009-05-07 22:00:25 -0400793 outw(0x0431, VGAREG_GRDC_ADDRESS);
794 outw(0x0031, VGAREG_GRDC_ADDRESS);
Kevin O'Connor161d2012011-12-31 19:42:21 -0500795
796 return 0;
Kevin O'Connor1f2c3072009-05-06 23:35:59 -0400797}