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Gerd Hoffmannd52fdf62010-11-29 09:42:13 +01001#ifndef __AHCI_H
2#define __AHCI_H
3
Kevin O'Connor135f3f62013-09-14 23:57:26 -04004#include "block.h" // struct drive_s
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04005#include "types.h" // u32
Kevin O'Connor2d2fa312013-09-14 21:55:26 -04006
Gerd Hoffmannd52fdf62010-11-29 09:42:13 +01007struct sata_cmd_fis {
8 u8 reg;
9 u8 pmp_type;
10 u8 command;
11 u8 feature;
12
13 u8 lba_low;
14 u8 lba_mid;
15 u8 lba_high;
16 u8 device;
17
18 u8 lba_low2;
19 u8 lba_mid2;
20 u8 lba_high2;
21 u8 feature2;
22
23 u8 sector_count;
24 u8 sector_count2;
25 u8 res_1;
26 u8 control;
27
28 u8 res_2[64 - 16];
29};
30
31struct ahci_ctrl_s {
Gerd Hoffmann9c869922011-07-14 16:24:05 +020032 struct pci_device *pci_tmp;
33 u16 pci_bdf;
Gerd Hoffmannd52fdf62010-11-29 09:42:13 +010034 u8 irq;
35 u32 iobase;
36 u32 caps;
37 u32 ports;
38};
39
40struct ahci_cmd_s {
41 struct sata_cmd_fis fis;
42 u8 atapi[0x20];
43 u8 res[0x20];
44 struct {
45 u32 base;
46 u32 baseu;
47 u32 res;
48 u32 flags;
49 } prdt[];
50};
51
52/* command list */
53struct ahci_list_s {
54 u32 flags;
55 u32 bytes;
56 u32 base;
57 u32 baseu;
58 u32 res[4];
59};
60
61struct ahci_fis_s {
62 u8 dsfis[0x1c]; /* dma setup */
63 u8 res_1[0x04];
64 u8 psfis[0x14]; /* pio setup */
65 u8 res_2[0x0c];
66 u8 rfis[0x14]; /* d2h register */
67 u8 res_3[0x04];
68 u8 sdbfis[0x08]; /* set device bits */
69 u8 ufis[0x40]; /* unknown */
70 u8 res_4[0x60];
71};
72
73struct ahci_port_s {
74 struct drive_s drive;
75 struct ahci_ctrl_s *ctrl;
76 struct ahci_list_s *list;
77 struct ahci_fis_s *fis;
78 struct ahci_cmd_s *cmd;
79 u32 pnr;
80 u32 atapi;
Gerd Hoffmann2dcbf7f2011-08-04 19:36:30 +020081 char *desc;
82 int prio;
Gerd Hoffmannd52fdf62010-11-29 09:42:13 +010083};
84
85void ahci_setup(void);
86int process_ahci_op(struct disk_op_s *op);
Kevin O'Connor0e5c7702015-07-07 11:24:27 -040087int ahci_atapi_process_op(struct disk_op_s *op);
Gerd Hoffmannd52fdf62010-11-29 09:42:13 +010088
89#define AHCI_IRQ_ON_SG (1 << 31)
90#define AHCI_CMD_ATAPI (1 << 5)
91#define AHCI_CMD_WRITE (1 << 6)
92#define AHCI_CMD_PREFETCH (1 << 7)
93#define AHCI_CMD_RESET (1 << 8)
94#define AHCI_CMD_CLR_BUSY (1 << 10)
95
96#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
97#define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
98#define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
99
100/* global controller registers */
101#define HOST_CAP 0x00 /* host capabilities */
102#define HOST_CTL 0x04 /* global host control */
103#define HOST_IRQ_STAT 0x08 /* interrupt status */
104#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
105#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
106
107/* HOST_CTL bits */
108#define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
109#define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
110#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
111
112/* HOST_CAP bits */
113#define HOST_CAP_SSC (1 << 14) /* Slumber capable */
114#define HOST_CAP_AHCI (1 << 18) /* AHCI only */
115#define HOST_CAP_CLO (1 << 24) /* Command List Override support */
116#define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
117#define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
118#define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
119
120/* registers for each SATA port */
121#define PORT_LST_ADDR 0x00 /* command list DMA addr */
122#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
123#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
124#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
125#define PORT_IRQ_STAT 0x10 /* interrupt status */
126#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
127#define PORT_CMD 0x18 /* port command */
128#define PORT_TFDATA 0x20 /* taskfile data */
129#define PORT_SIG 0x24 /* device TF signature */
130#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
131#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
132#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
133#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
134#define PORT_CMD_ISSUE 0x38 /* command issue */
135#define PORT_RESERVED 0x3c /* reserved */
136
137/* PORT_IRQ_{STAT,MASK} bits */
138#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
139#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
140#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
141#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
142#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
143#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
144#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
145#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
146
147#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
148#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
149#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
150#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
151#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
152#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
153#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
154#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
155#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
156
157#define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
158 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
159 PORT_IRQ_UNK_FIS)
160#define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
161 PORT_IRQ_HBUS_DATA_ERR)
162#define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
163 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
164 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
165
166/* PORT_CMD bits */
167#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
168#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
169#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
170#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
171#define PORT_CMD_CLO (1 << 3) /* Command list override */
172#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
173#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
174#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
175
176#define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
177#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
178#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
179#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
180
181#define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */
182#define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */
183#define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */
184#define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */
185#define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */
186#define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */
187#define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */
188#define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence
189 Status */
190#define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */
191#define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier
192 Status */
193#define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */
194#define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error
195 Status */
196#define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */
197#define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
198#define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
199#define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
200#define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */
201
202#endif // ahci.h