diff --git a/vgasrc/clext.c b/vgasrc/clext.c
index 4be70c1..32584ee 100644
--- a/vgasrc/clext.c
+++ b/vgasrc/clext.c
@@ -317,25 +317,27 @@
 static u16
 cirrus_get_crtc()
 {
-    return 0x3b4 + ((inb(0x3cc) & 1) << 5);
+    if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
+        return VGAREG_VGA_CRTC_ADDRESS;
+    return VGAREG_MDA_CRTC_ADDRESS;
 }
 
 static void
 cirrus_switch_mode(struct cirrus_mode_s *table)
 {
     // Unlock cirrus special
-    outw(0x1206, 0x3c4);
-    cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), 0x3c4);
-    cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), 0x3ce);
+    outw(0x1206, VGAREG_SEQU_ADDRESS);
+    cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
+    cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
 
-    outb(0x00, 0x3c6);
-    inb(0x3c6);
-    inb(0x3c6);
-    inb(0x3c6);
-    inb(0x3c6);
-    outb(GET_GLOBAL(table->hidden_dac), 0x3c6);
-    outb(0xff, 0x3c6);
+    outb(0x00, VGAREG_PEL_MASK);
+    inb(VGAREG_PEL_MASK);
+    inb(VGAREG_PEL_MASK);
+    inb(VGAREG_PEL_MASK);
+    inb(VGAREG_PEL_MASK);
+    outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
+    outb(0xff, VGAREG_PEL_MASK);
 
     u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
     u8 v = biosfn_get_single_palette_reg(0x10) & 0xfe;
@@ -364,8 +366,8 @@
 static int
 cirrus_check()
 {
-    outw(0x9206, 0x3c4);
-    return inb(0x3c5) == 0x12;
+    outw(0x9206, VGAREG_SEQU_ADDRESS);
+    return inb(VGAREG_SEQU_DATA) == 0x12;
 }
 
 void
@@ -377,12 +379,12 @@
     dprintf(1, "cirrus init 2\n");
 
     // memory setup
-    outb(0x0f, 0x3c4);
-    u8 v = inb(0x3c5);
-    outb(((v & 0x18) << 8) | 0x0a, 0x3c4);
+    outb(0x0f, VGAREG_SEQU_ADDRESS);
+    u8 v = inb(VGAREG_SEQU_DATA);
+    outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
     // set vga mode
-    outw(0x0007, 0x3c4);
+    outw(0x0007, VGAREG_SEQU_ADDRESS);
     // reset bitblt
-    outw(0x0431, 0x3ce);
-    outw(0x0031, 0x3ce);
+    outw(0x0431, VGAREG_GRDC_ADDRESS);
+    outw(0x0031, VGAREG_GRDC_ADDRESS);
 }
diff --git a/vgasrc/vga.c b/vgasrc/vga.c
index 9fc7afd..516bbc3 100644
--- a/vgasrc/vga.c
+++ b/vgasrc/vga.c
@@ -961,7 +961,7 @@
     u8 al = regs->bl & 0x0f;
     if (al & 0x08)
         al += 0x08;
-    outb(al, VGAREG_ACTL_ADDRESS);
+    outb(al, VGAREG_ACTL_WRITE_DATA);
     u8 bl = regs->bl & 0x10;
 
     int i;
@@ -971,7 +971,7 @@
         al = inb(VGAREG_ACTL_READ_DATA);
         al &= 0xef;
         al |= bl;
-        outb(al, VGAREG_ACTL_ADDRESS);
+        outb(al, VGAREG_ACTL_WRITE_DATA);
     }
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
@@ -988,7 +988,7 @@
         u8 al = inb(VGAREG_ACTL_READ_DATA);
         al &= 0xfe;
         al |= bl;
-        outb(al, VGAREG_ACTL_ADDRESS);
+        outb(al, VGAREG_ACTL_WRITE_DATA);
     }
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
@@ -1234,7 +1234,7 @@
 {
     inb(VGAREG_ACTL_RESET);
     outb(0x11, VGAREG_ACTL_ADDRESS);
-    outb(regs->bh, VGAREG_ACTL_ADDRESS);
+    outb(regs->bh, VGAREG_ACTL_WRITE_DATA);
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
 
@@ -1249,11 +1249,11 @@
     for (i = 0; i < 0x10; i++) {
         outb(i, VGAREG_ACTL_ADDRESS);
         u8 val = GET_FARVAR(regs->es, *data);
-        outb(val, VGAREG_ACTL_ADDRESS);
+        outb(val, VGAREG_ACTL_WRITE_DATA);
         data++;
     }
     outb(0x11, VGAREG_ACTL_ADDRESS);
-    outb(GET_FARVAR(regs->es, *data), VGAREG_ACTL_ADDRESS);
+    outb(GET_FARVAR(regs->es, *data), VGAREG_ACTL_WRITE_DATA);
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
 
@@ -1264,7 +1264,7 @@
     inb(VGAREG_ACTL_RESET);
     outb(0x10, VGAREG_ACTL_ADDRESS);
     u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0x7f) | ((regs->bl & 0x01) << 3);
-    outb(val, VGAREG_ACTL_ADDRESS);
+    outb(val, VGAREG_ACTL_WRITE_DATA);
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
 
@@ -1274,7 +1274,7 @@
 {
     inb(VGAREG_ACTL_RESET);
     outb(reg, VGAREG_ACTL_ADDRESS);
-    outb(val, VGAREG_ACTL_ADDRESS);
+    outb(val, VGAREG_ACTL_WRITE_DATA);
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
 
@@ -1357,7 +1357,7 @@
     u8 val = inb(VGAREG_ACTL_READ_DATA);
     if (!(regs->bl & 0x01)) {
         val = (val & 0x7f) | (regs->bh << 7);
-        outb(val, VGAREG_ACTL_ADDRESS);
+        outb(val, VGAREG_ACTL_WRITE_DATA);
         outb(0x20, VGAREG_ACTL_ADDRESS);
         return;
     }
@@ -1367,7 +1367,7 @@
     if (!(val & 0x80))
         bh <<= 2;
     bh &= 0x0f;
-    outb(bh, VGAREG_ACTL_ADDRESS);
+    outb(bh, VGAREG_ACTL_WRITE_DATA);
     outb(0x20, VGAREG_ACTL_ADDRESS);
 }
 
@@ -1950,7 +1950,7 @@
         }
         // select crtc base address
         v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
-        if (crtc_addr == 0x3d4)
+        if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
             v |= 0x01;
         outb(v, VGAREG_WRITE_MISC_OUTPUT);