Minor - improve formatting of src/acpi.c.
diff --git a/src/acpi.c b/src/acpi.c
index 79276a2..6a50971 100644
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -21,20 +21,20 @@
    BSD license) */
 
 #define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
-	u32                            signature;          /* ACPI signature (4 ASCII characters) */\
-	u32                             length;                 /* Length of table, in bytes, including header */\
-	u8                              revision;               /* ACPI Specification minor version # */\
-	u8                              checksum;               /* To make sum of entire table == 0 */\
-	u8                            oem_id [6];             /* OEM identification */\
-	u8                            oem_table_id [8];       /* OEM table identification */\
-	u32                             oem_revision;           /* OEM revision number */\
-	u8                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
-	u32                             asl_compiler_revision;  /* ASL compiler revision number */
+    u32 signature;          /* ACPI signature (4 ASCII characters) */ \
+    u32 length;                 /* Length of table, in bytes, including header */ \
+    u8  revision;               /* ACPI Specification minor version # */ \
+    u8  checksum;               /* To make sum of entire table == 0 */ \
+    u8  oem_id [6];             /* OEM identification */ \
+    u8  oem_table_id [8];       /* OEM table identification */ \
+    u32 oem_revision;           /* OEM revision number */ \
+    u8  asl_compiler_id [4];    /* ASL compiler vendor ID */ \
+    u32 asl_compiler_revision;  /* ASL compiler revision number */
 
 
 struct acpi_table_header         /* ACPI common table header */
 {
-	ACPI_TABLE_HEADER_DEF
+    ACPI_TABLE_HEADER_DEF
 };
 
 /*
@@ -43,9 +43,9 @@
 #define RSDT_SIGNATURE 0x54445352 // RSDT
 struct rsdt_descriptor_rev1
 {
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             table_offset_entry [3]; /* Array of pointers to other */
-			 /* ACPI tables */
+    ACPI_TABLE_HEADER_DEF       /* ACPI common table header */
+    u32 table_offset_entry [3]; /* Array of pointers to other */
+    /* ACPI tables */
 };
 
 /*
@@ -54,14 +54,14 @@
 #define FACS_SIGNATURE 0x53434146 // FACS
 struct facs_descriptor_rev1
 {
-	u32                            signature;           /* ACPI Signature */
-	u32                             length;                 /* Length of structure, in bytes */
-	u32                             hardware_signature;     /* Hardware configuration signature */
-	u32                             firmware_waking_vector; /* ACPI OS waking vector */
-	u32                             global_lock;            /* Global Lock */
-	u32                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
-	u32                             reserved1       : 31;   /* Must be 0 */
-	u8                              resverved3 [40];        /* Reserved - must be zero */
+    u32 signature;           /* ACPI Signature */
+    u32 length;                 /* Length of structure, in bytes */
+    u32 hardware_signature;     /* Hardware configuration signature */
+    u32 firmware_waking_vector; /* ACPI OS waking vector */
+    u32 global_lock;            /* Global Lock */
+    u32 S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
+    u32 reserved1       : 31;   /* Must be 0 */
+    u8  resverved3 [40];        /* Reserved - must be zero */
 };
 
 
@@ -71,58 +71,58 @@
 #define FACP_SIGNATURE 0x50434146 // FACP
 struct fadt_descriptor_rev1
 {
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             firmware_ctrl;          /* Physical address of FACS */
-	u32                             dsdt;                   /* Physical address of DSDT */
-	u8                              model;                  /* System Interrupt Model */
-	u8                              reserved1;              /* Reserved */
-	u16                             sci_int;                /* System vector of SCI interrupt */
-	u32                             smi_cmd;                /* Port address of SMI command port */
-	u8                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
-	u8                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
-	u8                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
-	u8                              reserved2;              /* Reserved - must be zero */
-	u32                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
-	u32                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
-	u32                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
-	u32                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
-	u32                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
-	u32                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
-	u32                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
-	u32                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
-	u8                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
-	u8                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
-	u8                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
-	u8                              pm_tmr_len;              /* Byte Length of ports at pm_tm_blk */
-	u8                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
-	u8                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
-	u8                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
-	u8                              reserved3;              /* Reserved */
-	u16                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
-	u16                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
-	u16                             flush_size;             /* Size of area read to flush caches */
-	u16                             flush_stride;           /* Stride used in flushing caches */
-	u8                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
-	u8                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
-	u8                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
-	u8                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
-	u8                              century;                /* Index to century in RTC CMOS RAM */
-	u8                              reserved4;              /* Reserved */
-	u8                              reserved4a;             /* Reserved */
-	u8                              reserved4b;             /* Reserved */
+    ACPI_TABLE_HEADER_DEF     /* ACPI common table header */
+    u32 firmware_ctrl;          /* Physical address of FACS */
+    u32 dsdt;                   /* Physical address of DSDT */
+    u8  model;                  /* System Interrupt Model */
+    u8  reserved1;              /* Reserved */
+    u16 sci_int;                /* System vector of SCI interrupt */
+    u32 smi_cmd;                /* Port address of SMI command port */
+    u8  acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+    u8  acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
+    u8  S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
+    u8  reserved2;              /* Reserved - must be zero */
+    u32 pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
+    u32 pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
+    u32 pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
+    u32 pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
+    u32 pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
+    u32 pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
+    u32 gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
+    u32 gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
+    u8  pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
+    u8  pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
+    u8  pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
+    u8  pm_tmr_len;             /* Byte Length of ports at pm_tm_blk */
+    u8  gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
+    u8  gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
+    u8  gpe1_base;              /* Offset in gpe model where gpe1 events start */
+    u8  reserved3;              /* Reserved */
+    u16 plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+    u16 plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
+    u16 flush_size;             /* Size of area read to flush caches */
+    u16 flush_stride;           /* Stride used in flushing caches */
+    u8  duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+    u8  duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+    u8  day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+    u8  mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+    u8  century;                /* Index to century in RTC CMOS RAM */
+    u8  reserved4;              /* Reserved */
+    u8  reserved4a;             /* Reserved */
+    u8  reserved4b;             /* Reserved */
 #if 0
-	u32                             wb_invd         : 1;    /* The wbinvd instruction works properly */
-	u32                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
-	u32                             proc_c1         : 1;    /* All processors support C1 state */
-	u32                             plvl2_up        : 1;    /* C2 state works on MP system */
-	u32                             pwr_button      : 1;    /* Power button is handled as a generic feature */
-	u32                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
-	u32                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
-	u32                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
-	u32                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
-	u32                             reserved5       : 23;   /* Reserved - must be zero */
+    u32 wb_invd         : 1;    /* The wbinvd instruction works properly */
+    u32 wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
+    u32 proc_c1         : 1;    /* All processors support C1 state */
+    u32 plvl2_up        : 1;    /* C2 state works on MP system */
+    u32 pwr_button      : 1;    /* Power button is handled as a generic feature */
+    u32 sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
+    u32 fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
+    u32 rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
+    u32 tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
+    u32 reserved5       : 23;   /* Reserved - must be zero */
 #else
-        u32 flags;
+    u32 flags;
 #endif
 };
 
@@ -141,13 +141,13 @@
 #define APIC_SIGNATURE 0x43495041 // APIC
 struct multiple_apic_table
 {
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             local_apic_address;     /* Physical address of local APIC */
+    ACPI_TABLE_HEADER_DEF     /* ACPI common table header */
+    u32 local_apic_address;     /* Physical address of local APIC */
 #if 0
-	u32                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
-	u32                             reserved1       : 31;
+    u32 PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
+    u32 reserved1       : 31;
 #else
-        u32                             flags;
+    u32 flags;
 #endif
 };
 
@@ -168,33 +168,33 @@
 /*
  * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
  */
-#define APIC_HEADER_DEF                     /* Common APIC sub-structure header */\
-	u8                              type; \
-	u8                              length;
+#define APIC_HEADER_DEF   /* Common APIC sub-structure header */\
+    u8  type;                               \
+    u8  length;
 
 /* Sub-structures for MADT */
 
 struct madt_processor_apic
 {
-	APIC_HEADER_DEF
-	u8                              processor_id;           /* ACPI processor id */
-	u8                              local_apic_id;          /* Processor's local APIC id */
+    APIC_HEADER_DEF
+    u8  processor_id;           /* ACPI processor id */
+    u8  local_apic_id;          /* Processor's local APIC id */
 #if 0
-	u32                             processor_enabled: 1;   /* Processor is usable if set */
-	u32                             reserved2       : 31;   /* Reserved, must be zero */
+    u32 processor_enabled: 1;   /* Processor is usable if set */
+    u32 reserved2       : 31;   /* Reserved, must be zero */
 #else
-        u32 flags;
+    u32 flags;
 #endif
 };
 
 struct madt_io_apic
 {
-	APIC_HEADER_DEF
-	u8                              io_apic_id;             /* I/O APIC ID */
-	u8                              reserved;               /* Reserved - must be zero */
-	u32                             address;                /* APIC physical address */
-	u32                             interrupt;              /* Global system interrupt where INTI
-			  * lines start */
+    APIC_HEADER_DEF
+    u8  io_apic_id;             /* I/O APIC ID */
+    u8  reserved;               /* Reserved - must be zero */
+    u32 address;                /* APIC physical address */
+    u32 interrupt;              /* Global system interrupt where INTI
+                                 * lines start */
 };
 
 #if CONFIG_KVM
@@ -322,7 +322,7 @@
 
     /* reserve memory space for tables */
     bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
-    rsdp = (void *)(bios_table_cur_addr);
+    rsdp = (void *)bios_table_cur_addr;
     bios_table_cur_addr += sizeof(*rsdp);
 
     addr = base_addr = RamSize - CONFIG_ACPI_DATA_SIZE;
@@ -416,7 +416,7 @@
     memset(madt, 0, madt_size);
     madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
     madt->flags = cpu_to_le32(1);
-    struct madt_processor_apic *apic = (void *)(madt + 1);
+    struct madt_processor_apic *apic = (void *)&madt[1];
     for(i=0;i<smp_cpus;i++) {
         apic->type = APIC_PROCESSOR;
         apic->length = sizeof(*apic);
@@ -432,19 +432,17 @@
     io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
     io_apic->interrupt = cpu_to_le32(0);
 
-    struct madt_intsrcovr *intsrcovr = (struct madt_intsrcovr*)(io_apic + 1);
+    struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
     for (i = 0; i < 16; i++) {
-        if (PCI_ISA_IRQ_MASK & (1 << i)) {
-            memset(intsrcovr, 0, sizeof(*intsrcovr));
-            intsrcovr->type   = APIC_XRUPT_OVERRIDE;
-            intsrcovr->length = sizeof(*intsrcovr);
-            intsrcovr->source = i;
-            intsrcovr->gsi    = i;
-            intsrcovr->flags  = 0xd; /* active high, level triggered */
-        } else {
+        if (!(PCI_ISA_IRQ_MASK & (1 << i)))
             /* No need for a INT source override structure. */
             continue;
-        }
+        memset(intsrcovr, 0, sizeof(*intsrcovr));
+        intsrcovr->type   = APIC_XRUPT_OVERRIDE;
+        intsrcovr->length = sizeof(*intsrcovr);
+        intsrcovr->source = i;
+        intsrcovr->gsi    = i;
+        intsrcovr->flags  = 0xd; /* active high, level triggered */
         intsrcovr++;
         madt_size += sizeof(struct madt_intsrcovr);
     }