diff --git a/Makefile b/Makefile
index bb078f4..50a29d5 100644
--- a/Makefile
+++ b/Makefile
@@ -9,8 +9,8 @@
 
 # Source files
 SRC16=floppy.c disk.c system.c clock.c serial.c kbd.c mouse.c output.c \
-      boot.c ata.c cdrom.c apm.c
-SRC32=post.c output.c
+      boot.c ata.c cdrom.c apm.c util.c
+SRC32=post.c output.c rombios32.c util.c
 TABLESRC=font.c cbt.c floppy_dbt.c
 
 cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \
diff --git a/src/acpi-dsdt.dsl b/src/acpi-dsdt.dsl
new file mode 100644
index 0000000..07b277e
--- /dev/null
+++ b/src/acpi-dsdt.dsl
@@ -0,0 +1,570 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+DefinitionBlock (
+    "acpi-dsdt.aml",    // Output Filename
+    "DSDT",             // Signature
+    0x01,               // DSDT Compliance Revision
+    "BXPC",             // OEMID
+    "BXDSDT",           // TABLE ID
+    0x1                 // OEM Revision
+    )
+{
+    Scope (\)
+    {
+        /* CMOS memory access */
+        OperationRegion (CMS, SystemIO, 0x70, 0x02)
+        Field (CMS, ByteAcc, NoLock, Preserve)
+        {
+            CMSI,   8,
+            CMSD,   8
+        }
+        Method (CMRD, 1, NotSerialized)
+        {
+            Store (Arg0, CMSI)
+            Store (CMSD, Local0)
+            Return (Local0)
+        }
+
+        /* Debug Output */
+        OperationRegion (DBG, SystemIO, 0xb044, 0x04)
+        Field (DBG, DWordAcc, NoLock, Preserve)
+        {
+            DBGL,   32,
+        }
+    }
+
+
+    /* PCI Bus definition */
+    Scope(\_SB) {
+        Device(PCI0) {
+            Name (_HID, EisaId ("PNP0A03"))
+            Name (_ADR, 0x00)
+            Name (_UID, 1)
+            Name(_PRT, Package() {
+                /* PCI IRQ routing table, example from ACPI 2.0a specification,
+                   section 6.2.8.1 */
+                /* Note: we provide the same info as the PCI routing
+                   table of the Bochs BIOS */
+
+                // PCI Slot 0
+                Package() {0x0000ffff, 0, LNKD, 0},
+                Package() {0x0000ffff, 1, LNKA, 0},
+                Package() {0x0000ffff, 2, LNKB, 0},
+                Package() {0x0000ffff, 3, LNKC, 0},
+
+                // PCI Slot 1
+                Package() {0x0001ffff, 0, LNKA, 0},
+                Package() {0x0001ffff, 1, LNKB, 0},
+                Package() {0x0001ffff, 2, LNKC, 0},
+                Package() {0x0001ffff, 3, LNKD, 0},
+
+                // PCI Slot 2
+                Package() {0x0002ffff, 0, LNKB, 0},
+                Package() {0x0002ffff, 1, LNKC, 0},
+                Package() {0x0002ffff, 2, LNKD, 0},
+                Package() {0x0002ffff, 3, LNKA, 0},
+
+                // PCI Slot 3
+                Package() {0x0003ffff, 0, LNKC, 0},
+                Package() {0x0003ffff, 1, LNKD, 0},
+                Package() {0x0003ffff, 2, LNKA, 0},
+                Package() {0x0003ffff, 3, LNKB, 0},
+
+                // PCI Slot 4
+                Package() {0x0004ffff, 0, LNKD, 0},
+                Package() {0x0004ffff, 1, LNKA, 0},
+                Package() {0x0004ffff, 2, LNKB, 0},
+                Package() {0x0004ffff, 3, LNKC, 0},
+
+                // PCI Slot 5
+                Package() {0x0005ffff, 0, LNKA, 0},
+                Package() {0x0005ffff, 1, LNKB, 0},
+                Package() {0x0005ffff, 2, LNKC, 0},
+                Package() {0x0005ffff, 3, LNKD, 0},
+            })
+
+            Method (_CRS, 0, NotSerialized)
+            {
+            Name (MEMP, ResourceTemplate ()
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x00FF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0100,             // Address Length
+                    ,, )
+                IO (Decode16,
+                    0x0CF8,             // Address Range Minimum
+                    0x0CF8,             // Address Range Maximum
+                    0x01,               // Address Alignment
+                    0x08,               // Address Length
+                    )
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0000,             // Address Range Minimum
+                    0x0CF7,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0x0CF8,             // Address Length
+                    ,, , TypeStatic)
+                WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x0000,             // Address Space Granularity
+                    0x0D00,             // Address Range Minimum
+                    0xFFFF,             // Address Range Maximum
+                    0x0000,             // Address Translation Offset
+                    0xF300,             // Address Length
+                    ,, , TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0x000A0000,         // Address Range Minimum
+                    0x000BFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x00020000,         // Address Length
+                    ,, , AddressRangeMemory, TypeStatic)
+                DWordMemory (ResourceProducer, PosDecode, MinNotFixed, MaxFixed, NonCacheable, ReadWrite,
+                    0x00000000,         // Address Space Granularity
+                    0x00000000,         // Address Range Minimum
+                    0xFEBFFFFF,         // Address Range Maximum
+                    0x00000000,         // Address Translation Offset
+                    0x00000000,         // Address Length
+                    ,, MEMF, AddressRangeMemory, TypeStatic)
+            })
+                CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MIN, PMIN)
+                CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MAX, PMAX)
+                CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._LEN, PLEN)
+                /* compute available RAM */
+                Add(CMRD(0x34), ShiftLeft(CMRD(0x35), 8), Local0)
+                ShiftLeft(Local0, 16, Local0)
+                Add(Local0, 0x1000000, Local0)
+                /* update field of last region */
+                Store(Local0, PMIN)
+                Subtract (PMAX, PMIN, PLEN)
+                Increment (PLEN)
+                Return (MEMP)
+            }
+        }
+    }
+
+    Scope(\_SB.PCI0) {
+
+	/* PIIX3 ISA bridge */
+        Device (ISA) {
+            Name (_ADR, 0x00010000)
+
+            /* PIIX PCI to ISA irq remapping */
+            OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+
+            /* Real-time clock */
+            Device (RTC)
+            {
+                Name (_HID, EisaId ("PNP0B00"))
+                Name (_CRS, ResourceTemplate ()
+                {
+                    IO (Decode16, 0x0070, 0x0070, 0x10, 0x02)
+                    IRQNoFlags () {8}
+                    IO (Decode16, 0x0072, 0x0072, 0x02, 0x06)
+                })
+            }
+
+            /* Keyboard seems to be important for WinXP install */
+            Device (KBD)
+            {
+                Name (_HID, EisaId ("PNP0303"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                     Name (TMP, ResourceTemplate ()
+                     {
+                    IO (Decode16,
+                        0x0060,             // Address Range Minimum
+                        0x0060,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IO (Decode16,
+                        0x0064,             // Address Range Minimum
+                        0x0064,             // Address Range Maximum
+                        0x01,               // Address Alignment
+                        0x01,               // Address Length
+                        )
+                    IRQNoFlags ()
+                        {1}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 mouse */
+            Device (MOU)
+            {
+                Name (_HID, EisaId ("PNP0F13"))
+                Method (_STA, 0, NotSerialized)
+                {
+                    Return (0x0f)
+                }
+
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (TMP, ResourceTemplate ()
+                    {
+                         IRQNoFlags () {12}
+                    })
+                    Return (TMP)
+                }
+            }
+
+	    /* PS/2 floppy controller */
+	    Device (FDC0)
+	    {
+	        Name (_HID, EisaId ("PNP0700"))
+		Method (_STA, 0, NotSerialized)
+		{
+		    Return (0x0F)
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+                        IRQNoFlags () {6}
+                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
+                    })
+		    Return (BUF0)
+		}
+	    }
+
+	    /* Parallel port */
+	    Device (LPT)
+	    {
+	        Name (_HID, EisaId ("PNP0400"))
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (\_SB.PCI0.PX13.DRSA, Local0)
+		    And (Local0, 0x80000000, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x0378, 0x0378, 0x08, 0x08)
+			IRQNoFlags () {7}
+		    })
+		    Return (BUF0)
+		}
+	    }
+
+	    /* Serial Ports */
+	    Device (COM1)
+	    {
+	        Name (_HID, EisaId ("PNP0501"))
+		Name (_UID, 0x01)
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (\_SB.PCI0.PX13.DRSC, Local0)
+		    And (Local0, 0x08000000, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+                	IRQNoFlags () {4}
+		    })
+		    Return (BUF0)
+		}
+	    }
+
+	    Device (COM2)
+	    {
+	        Name (_HID, EisaId ("PNP0501"))
+		Name (_UID, 0x02)
+		Method (_STA, 0, NotSerialized)
+		{
+		    Store (\_SB.PCI0.PX13.DRSC, Local0)
+		    And (Local0, 0x80000000, Local0)
+		    If (LEqual (Local0, 0))
+		    {
+			Return (0x00)
+		    }
+		    Else
+		    {
+			Return (0x0F)
+		    }
+		}
+		Method (_CRS, 0, NotSerialized)
+		{
+		    Name (BUF0, ResourceTemplate ()
+                    {
+			IO (Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+                	IRQNoFlags () {3}
+		    })
+		    Return (BUF0)
+		}
+	    }
+        }
+
+	/* PIIX4 PM */
+        Device (PX13) {
+	    Name (_ADR, 0x00010003)
+
+	    OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
+	    Field (P13C, DWordAcc, NoLock, Preserve)
+	    {
+		DRSA, 32,
+		DRSB, 32,
+		DRSC, 32,
+		DRSE, 32,
+		DRSF, 32,
+		DRSG, 32,
+		DRSH, 32,
+		DRSI, 32,
+		DRSJ, 32
+	    }
+	}
+    }
+
+    /* PCI IRQs */
+    Scope(\_SB) {
+         Field (\_SB.PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+         {
+             PRQ0,   8,
+             PRQ1,   8,
+             PRQ2,   8,
+             PRQ3,   8
+         }
+
+        Device(LNKA){
+                Name(_HID, EISAID("PNP0C0F"))     // PCI interrupt link
+                Name(_UID, 1)
+                Name(_PRS, ResourceTemplate(){
+                    IRQ (Level, ActiveLow, Shared)
+                        {3,4,5,6,7,9,10,11,12}
+                })
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (0x0B, Local0)
+                    If (And (0x80, PRQ0, Local1))
+                    {
+                         Store (0x09, Local0)
+                    }
+                    Return (Local0)
+                }
+                Method (_DIS, 0, NotSerialized)
+                {
+                    Or (PRQ0, 0x80, PRQ0)
+                }
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (PRR0, ResourceTemplate ()
+                    {
+                        IRQ (Level, ActiveLow, Shared)
+                            {1}
+                    })
+                    CreateWordField (PRR0, 0x01, TMP)
+                    Store (PRQ0, Local0)
+                    If (LLess (Local0, 0x80))
+                    {
+                        ShiftLeft (One, Local0, TMP)
+                    }
+                    Else
+                    {
+                        Store (Zero, TMP)
+                    }
+                    Return (PRR0)
+                }
+                Method (_SRS, 1, NotSerialized)
+                {
+                    CreateWordField (Arg0, 0x01, TMP)
+                    FindSetRightBit (TMP, Local0)
+                    Decrement (Local0)
+                    Store (Local0, PRQ0)
+                }
+        }
+        Device(LNKB){
+                Name(_HID, EISAID("PNP0C0F"))     // PCI interrupt link
+                Name(_UID, 2)
+                Name(_PRS, ResourceTemplate(){
+                    IRQ (Level, ActiveLow, Shared)
+                        {3,4,5,6,7,9,10,11,12}
+                })
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (0x0B, Local0)
+                    If (And (0x80, PRQ1, Local1))
+                    {
+                         Store (0x09, Local0)
+                    }
+                    Return (Local0)
+                }
+                Method (_DIS, 0, NotSerialized)
+                {
+                    Or (PRQ1, 0x80, PRQ1)
+                }
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (PRR0, ResourceTemplate ()
+                    {
+                        IRQ (Level, ActiveLow, Shared)
+                            {1}
+                    })
+                    CreateWordField (PRR0, 0x01, TMP)
+                    Store (PRQ1, Local0)
+                    If (LLess (Local0, 0x80))
+                    {
+                        ShiftLeft (One, Local0, TMP)
+                    }
+                    Else
+                    {
+                        Store (Zero, TMP)
+                    }
+                    Return (PRR0)
+                }
+                Method (_SRS, 1, NotSerialized)
+                {
+                    CreateWordField (Arg0, 0x01, TMP)
+                    FindSetRightBit (TMP, Local0)
+                    Decrement (Local0)
+                    Store (Local0, PRQ1)
+                }
+        }
+        Device(LNKC){
+                Name(_HID, EISAID("PNP0C0F"))     // PCI interrupt link
+                Name(_UID, 3)
+                Name(_PRS, ResourceTemplate(){
+                    IRQ (Level, ActiveLow, Shared)
+                        {3,4,5,6,7,9,10,11,12}
+                })
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (0x0B, Local0)
+                    If (And (0x80, PRQ2, Local1))
+                    {
+                         Store (0x09, Local0)
+                    }
+                    Return (Local0)
+                }
+                Method (_DIS, 0, NotSerialized)
+                {
+                    Or (PRQ2, 0x80, PRQ2)
+                }
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (PRR0, ResourceTemplate ()
+                    {
+                        IRQ (Level, ActiveLow, Shared)
+                            {1}
+                    })
+                    CreateWordField (PRR0, 0x01, TMP)
+                    Store (PRQ2, Local0)
+                    If (LLess (Local0, 0x80))
+                    {
+                        ShiftLeft (One, Local0, TMP)
+                    }
+                    Else
+                    {
+                        Store (Zero, TMP)
+                    }
+                    Return (PRR0)
+                }
+                Method (_SRS, 1, NotSerialized)
+                {
+                    CreateWordField (Arg0, 0x01, TMP)
+                    FindSetRightBit (TMP, Local0)
+                    Decrement (Local0)
+                    Store (Local0, PRQ2)
+                }
+        }
+        Device(LNKD){
+                Name(_HID, EISAID("PNP0C0F"))     // PCI interrupt link
+                Name(_UID, 4)
+                Name(_PRS, ResourceTemplate(){
+                    IRQ (Level, ActiveLow, Shared)
+                        {3,4,5,6,7,9,10,11,12}
+                })
+                Method (_STA, 0, NotSerialized)
+                {
+                    Store (0x0B, Local0)
+                    If (And (0x80, PRQ3, Local1))
+                    {
+                         Store (0x09, Local0)
+                    }
+                    Return (Local0)
+                }
+                Method (_DIS, 0, NotSerialized)
+                {
+                    Or (PRQ3, 0x80, PRQ3)
+                }
+                Method (_CRS, 0, NotSerialized)
+                {
+                    Name (PRR0, ResourceTemplate ()
+                    {
+                        IRQ (Level, ActiveLow, Shared)
+                            {1}
+                    })
+                    CreateWordField (PRR0, 0x01, TMP)
+                    Store (PRQ3, Local0)
+                    If (LLess (Local0, 0x80))
+                    {
+                        ShiftLeft (One, Local0, TMP)
+                    }
+                    Else
+                    {
+                        Store (Zero, TMP)
+                    }
+                    Return (PRR0)
+                }
+                Method (_SRS, 1, NotSerialized)
+                {
+                    CreateWordField (Arg0, 0x01, TMP)
+                    FindSetRightBit (TMP, Local0)
+                    Decrement (Local0)
+                    Store (Local0, PRQ3)
+                }
+        }
+    }
+
+    /* S5 = power off state */
+    Name (_S5, Package (4) {
+        0x00, // PM1a_CNT.SLP_TYP
+        0x00, // PM2a_CNT.SLP_TYP
+        0x00, // reserved
+        0x00, // reserved
+    })
+}
diff --git a/src/acpi-dsdt.hex b/src/acpi-dsdt.hex
new file mode 100644
index 0000000..e1fd7f5
--- /dev/null
+++ b/src/acpi-dsdt.hex
@@ -0,0 +1,284 @@
+/*
+ * 
+ * Intel ACPI Component Architecture
+ * ASL Optimizing Compiler version 20060912 [Nov 25 2006]
+ * Copyright (C) 2000 - 2006 Intel Corporation
+ * Supports ACPI Specification Revision 3.0a
+ * 
+ * Compilation of "acpi-dsdt.dsl" - Mon Jan 21 21:59:14 2008
+ * 
+ * C source code output
+ *
+ */
+unsigned char AmlCode[] =
+{
+    0x44,0x53,0x44,0x54,0x61,0x08,0x00,0x00,  /* 00000000    "DSDTa..." */
+    0x01,0x84,0x42,0x58,0x50,0x43,0x00,0x00,  /* 00000008    "..BXPC.." */
+    0x42,0x58,0x44,0x53,0x44,0x54,0x00,0x00,  /* 00000010    "BXDSDT.." */
+    0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,  /* 00000018    "....INTL" */
+    0x12,0x09,0x06,0x20,0x10,0x4F,0x04,0x5C,  /* 00000020    "... .O.\" */
+    0x00,0x5B,0x80,0x43,0x4D,0x53,0x5F,0x01,  /* 00000028    ".[.CMS_." */
+    0x0A,0x70,0x0A,0x02,0x5B,0x81,0x10,0x43,  /* 00000030    ".p..[..C" */
+    0x4D,0x53,0x5F,0x01,0x43,0x4D,0x53,0x49,  /* 00000038    "MS_.CMSI" */
+    0x08,0x43,0x4D,0x53,0x44,0x08,0x14,0x14,  /* 00000040    ".CMSD..." */
+    0x43,0x4D,0x52,0x44,0x01,0x70,0x68,0x43,  /* 00000048    "CMRD.phC" */
+    0x4D,0x53,0x49,0x70,0x43,0x4D,0x53,0x44,  /* 00000050    "MSIpCMSD" */
+    0x60,0xA4,0x60,0x5B,0x80,0x44,0x42,0x47,  /* 00000058    "`.`[.DBG" */
+    0x5F,0x01,0x0B,0x44,0xB0,0x0A,0x04,0x5B,  /* 00000060    "_..D...[" */
+    0x81,0x0B,0x44,0x42,0x47,0x5F,0x03,0x44,  /* 00000068    "..DBG_.D" */
+    0x42,0x47,0x4C,0x20,0x10,0x4E,0x25,0x5F,  /* 00000070    "BGL .N%_" */
+    0x53,0x42,0x5F,0x5B,0x82,0x46,0x25,0x50,  /* 00000078    "SB_[.F%P" */
+    0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44,  /* 00000080    "CI0._HID" */
+    0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41,  /* 00000088    ".A...._A" */
+    0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44,  /* 00000090    "DR.._UID" */
+    0x01,0x08,0x5F,0x50,0x52,0x54,0x12,0x47,  /* 00000098    ".._PRT.G" */
+    0x15,0x18,0x12,0x0B,0x04,0x0B,0xFF,0xFF,  /* 000000A0    "........" */
+    0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0B,  /* 000000A8    ".LNKD..." */
+    0x04,0x0B,0xFF,0xFF,0x01,0x4C,0x4E,0x4B,  /* 000000B0    ".....LNK" */
+    0x41,0x00,0x12,0x0C,0x04,0x0B,0xFF,0xFF,  /* 000000B8    "A......." */
+    0x0A,0x02,0x4C,0x4E,0x4B,0x42,0x00,0x12,  /* 000000C0    "..LNKB.." */
+    0x0C,0x04,0x0B,0xFF,0xFF,0x0A,0x03,0x4C,  /* 000000C8    ".......L" */
+    0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C,  /* 000000D0    "NKC....." */
+    0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B,  /* 000000D8    ".....LNK" */
+    0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 000000E0    "A......." */
+    0x01,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00,  /* 000000E8    "...LNKB." */
+    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,  /* 000000F0    "........" */
+    0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12,  /* 000000F8    "..LNKC.." */
+    0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,  /* 00000100    "........" */
+    0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D,  /* 00000108    ".LNKD..." */
+    0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00,0x4C,  /* 00000110    ".......L" */
+    0x4E,0x4B,0x42,0x00,0x12,0x0D,0x04,0x0C,  /* 00000118    "NKB....." */
+    0xFF,0xFF,0x02,0x00,0x01,0x4C,0x4E,0x4B,  /* 00000120    ".....LNK" */
+    0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,  /* 00000128    "C......." */
+    0x02,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x44,  /* 00000130    "....LNKD" */
+    0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x02,  /* 00000138    "........" */
+    0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x41,0x00,  /* 00000140    "...LNKA." */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x03,0x00,  /* 00000148    "........" */
+    0x00,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0D,  /* 00000150    ".LNKC..." */
+    0x04,0x0C,0xFF,0xFF,0x03,0x00,0x01,0x4C,  /* 00000158    ".......L" */
+    0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04,0x0C,  /* 00000160    "NKD....." */
+    0xFF,0xFF,0x03,0x00,0x0A,0x02,0x4C,0x4E,  /* 00000168    "......LN" */
+    0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C,0xFF,  /* 00000170    "KA......" */
+    0xFF,0x03,0x00,0x0A,0x03,0x4C,0x4E,0x4B,  /* 00000178    ".....LNK" */
+    0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 00000180    "B......." */
+    0x04,0x00,0x00,0x4C,0x4E,0x4B,0x44,0x00,  /* 00000188    "...LNKD." */
+    0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x04,0x00,  /* 00000190    "........" */
+    0x01,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0E,  /* 00000198    ".LNKA..." */
+    0x04,0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x02,  /* 000001A0    "........" */
+    0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,  /* 000001A8    "LNKB...." */
+    0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x03,0x4C,  /* 000001B0    ".......L" */
+    0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C,  /* 000001B8    "NKC....." */
+    0xFF,0xFF,0x05,0x00,0x00,0x4C,0x4E,0x4B,  /* 000001C0    ".....LNK" */
+    0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,  /* 000001C8    "A......." */
+    0x05,0x00,0x01,0x4C,0x4E,0x4B,0x42,0x00,  /* 000001D0    "...LNKB." */
+    0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00,  /* 000001D8    "........" */
+    0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12,  /* 000001E0    "..LNKC.." */
+    0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00,0x0A,  /* 000001E8    "........" */
+    0x03,0x4C,0x4E,0x4B,0x44,0x00,0x14,0x4C,  /* 000001F0    ".LNKD..L" */
+    0x0D,0x5F,0x43,0x52,0x53,0x00,0x08,0x4D,  /* 000001F8    "._CRS..M" */
+    0x45,0x4D,0x50,0x11,0x42,0x07,0x0A,0x6E,  /* 00000200    "EMP.B..n" */
+    0x88,0x0D,0x00,0x02,0x0C,0x00,0x00,0x00,  /* 00000208    "........" */
+    0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x01,  /* 00000210    "........" */
+    0x47,0x01,0xF8,0x0C,0xF8,0x0C,0x01,0x08,  /* 00000218    "G......." */
+    0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00,  /* 00000220    "........" */
+    0x00,0x00,0xF7,0x0C,0x00,0x00,0xF8,0x0C,  /* 00000228    "........" */
+    0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00,  /* 00000230    "........" */
+    0x00,0x0D,0xFF,0xFF,0x00,0x00,0x00,0xF3,  /* 00000238    "........" */
+    0x87,0x17,0x00,0x00,0x0C,0x03,0x00,0x00,  /* 00000240    "........" */
+    0x00,0x00,0x00,0x00,0x0A,0x00,0xFF,0xFF,  /* 00000248    "........" */
+    0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 00000250    "........" */
+    0x02,0x00,0x87,0x17,0x00,0x00,0x08,0x01,  /* 00000258    "........" */
+    0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 00000260    "........" */
+    0xFF,0xFF,0xBF,0xFE,0x00,0x00,0x00,0x00,  /* 00000268    "........" */
+    0x00,0x00,0x00,0x00,0x79,0x00,0x8A,0x4D,  /* 00000270    "....y..M" */
+    0x45,0x4D,0x50,0x0A,0x5C,0x50,0x4D,0x49,  /* 00000278    "EMP.\PMI" */
+    0x4E,0x8A,0x4D,0x45,0x4D,0x50,0x0A,0x60,  /* 00000280    "N.MEMP.`" */
+    0x50,0x4D,0x41,0x58,0x8A,0x4D,0x45,0x4D,  /* 00000288    "PMAX.MEM" */
+    0x50,0x0A,0x68,0x50,0x4C,0x45,0x4E,0x72,  /* 00000290    "P.hPLENr" */
+    0x43,0x4D,0x52,0x44,0x0A,0x34,0x79,0x43,  /* 00000298    "CMRD.4yC" */
+    0x4D,0x52,0x44,0x0A,0x35,0x0A,0x08,0x00,  /* 000002A0    "MRD.5..." */
+    0x60,0x79,0x60,0x0A,0x10,0x60,0x72,0x60,  /* 000002A8    "`y`..`r`" */
+    0x0C,0x00,0x00,0x00,0x01,0x60,0x70,0x60,  /* 000002B0    ".....`p`" */
+    0x50,0x4D,0x49,0x4E,0x74,0x50,0x4D,0x41,  /* 000002B8    "PMINtPMA" */
+    0x58,0x50,0x4D,0x49,0x4E,0x50,0x4C,0x45,  /* 000002C0    "XPMINPLE" */
+    0x4E,0x75,0x50,0x4C,0x45,0x4E,0xA4,0x4D,  /* 000002C8    "NuPLEN.M" */
+    0x45,0x4D,0x50,0x10,0x41,0x29,0x2E,0x5F,  /* 000002D0    "EMP.A)._" */
+    0x53,0x42,0x5F,0x50,0x43,0x49,0x30,0x5B,  /* 000002D8    "SB_PCI0[" */
+    0x82,0x42,0x23,0x49,0x53,0x41,0x5F,0x08,  /* 000002E0    ".B#ISA_." */
+    0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,0x01,  /* 000002E8    "_ADR...." */
+    0x00,0x5B,0x80,0x50,0x34,0x30,0x43,0x02,  /* 000002F0    ".[.P40C." */
+    0x0A,0x60,0x0A,0x04,0x5B,0x82,0x2D,0x52,  /* 000002F8    ".`..[.-R" */
+    0x54,0x43,0x5F,0x08,0x5F,0x48,0x49,0x44,  /* 00000300    "TC_._HID" */
+    0x0C,0x41,0xD0,0x0B,0x00,0x08,0x5F,0x43,  /* 00000308    ".A...._C" */
+    0x52,0x53,0x11,0x18,0x0A,0x15,0x47,0x01,  /* 00000310    "RS....G." */
+    0x70,0x00,0x70,0x00,0x10,0x02,0x22,0x00,  /* 00000318    "p.p..."." */
+    0x01,0x47,0x01,0x72,0x00,0x72,0x00,0x02,  /* 00000320    ".G.r.r.." */
+    0x06,0x79,0x00,0x5B,0x82,0x44,0x04,0x4B,  /* 00000328    ".y.[.D.K" */
+    0x42,0x44,0x5F,0x08,0x5F,0x48,0x49,0x44,  /* 00000330    "BD_._HID" */
+    0x0C,0x41,0xD0,0x03,0x03,0x14,0x09,0x5F,  /* 00000338    ".A....._" */
+    0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F,0x14,  /* 00000340    "STA....." */
+    0x29,0x5F,0x43,0x52,0x53,0x00,0x08,0x54,  /* 00000348    ")_CRS..T" */
+    0x4D,0x50,0x5F,0x11,0x18,0x0A,0x15,0x47,  /* 00000350    "MP_....G" */
+    0x01,0x60,0x00,0x60,0x00,0x01,0x01,0x47,  /* 00000358    ".`.`...G" */
+    0x01,0x64,0x00,0x64,0x00,0x01,0x01,0x22,  /* 00000360    ".d.d..."" */
+    0x02,0x00,0x79,0x00,0xA4,0x54,0x4D,0x50,  /* 00000368    "..y..TMP" */
+    0x5F,0x5B,0x82,0x33,0x4D,0x4F,0x55,0x5F,  /* 00000370    "_[.3MOU_" */
+    0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,  /* 00000378    "._HID.A." */
+    0x0F,0x13,0x14,0x09,0x5F,0x53,0x54,0x41,  /* 00000380    "...._STA" */
+    0x00,0xA4,0x0A,0x0F,0x14,0x19,0x5F,0x43,  /* 00000388    "......_C" */
+    0x52,0x53,0x00,0x08,0x54,0x4D,0x50,0x5F,  /* 00000390    "RS..TMP_" */
+    0x11,0x08,0x0A,0x05,0x22,0x00,0x10,0x79,  /* 00000398    "...."..y" */
+    0x00,0xA4,0x54,0x4D,0x50,0x5F,0x5B,0x82,  /* 000003A0    "..TMP_[." */
+    0x47,0x04,0x46,0x44,0x43,0x30,0x08,0x5F,  /* 000003A8    "G.FDC0._" */
+    0x48,0x49,0x44,0x0C,0x41,0xD0,0x07,0x00,  /* 000003B0    "HID.A..." */
+    0x14,0x09,0x5F,0x53,0x54,0x41,0x00,0xA4,  /* 000003B8    ".._STA.." */
+    0x0A,0x0F,0x14,0x2C,0x5F,0x43,0x52,0x53,  /* 000003C0    "...,_CRS" */
+    0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x1B,  /* 000003C8    "..BUF0.." */
+    0x0A,0x18,0x47,0x01,0xF2,0x03,0xF2,0x03,  /* 000003D0    "..G....." */
+    0x00,0x04,0x47,0x01,0xF7,0x03,0xF7,0x03,  /* 000003D8    "..G....." */
+    0x00,0x01,0x22,0x40,0x00,0x2A,0x04,0x00,  /* 000003E0    ".."@.*.." */
+    0x79,0x00,0xA4,0x42,0x55,0x46,0x30,0x5B,  /* 000003E8    "y..BUF0[" */
+    0x82,0x4B,0x05,0x4C,0x50,0x54,0x5F,0x08,  /* 000003F0    ".K.LPT_." */
+    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x04,  /* 000003F8    "_HID.A.." */
+    0x00,0x14,0x28,0x5F,0x53,0x54,0x41,0x00,  /* 00000400    "..(_STA." */
+    0x70,0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31,  /* 00000408    "p^^^.PX1" */
+    0x33,0x44,0x52,0x53,0x41,0x60,0x7B,0x60,  /* 00000410    "3DRSA`{`" */
+    0x0C,0x00,0x00,0x00,0x80,0x60,0xA0,0x06,  /* 00000418    ".....`.." */
+    0x93,0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4,  /* 00000420    ".`......" */
+    0x0A,0x0F,0x14,0x21,0x5F,0x43,0x52,0x53,  /* 00000428    "...!_CRS" */
+    0x00,0x08,0x42,0x55,0x46,0x30,0x11,0x10,  /* 00000430    "..BUF0.." */
+    0x0A,0x0D,0x47,0x01,0x78,0x03,0x78,0x03,  /* 00000438    "..G.x.x." */
+    0x08,0x08,0x22,0x80,0x00,0x79,0x00,0xA4,  /* 00000440    ".."..y.." */
+    0x42,0x55,0x46,0x30,0x5B,0x82,0x41,0x06,  /* 00000448    "BUF0[.A." */
+    0x43,0x4F,0x4D,0x31,0x08,0x5F,0x48,0x49,  /* 00000450    "COM1._HI" */
+    0x44,0x0C,0x41,0xD0,0x05,0x01,0x08,0x5F,  /* 00000458    "D.A...._" */
+    0x55,0x49,0x44,0x01,0x14,0x28,0x5F,0x53,  /* 00000460    "UID..(_S" */
+    0x54,0x41,0x00,0x70,0x5E,0x5E,0x5E,0x2E,  /* 00000468    "TA.p^^^." */
+    0x50,0x58,0x31,0x33,0x44,0x52,0x53,0x43,  /* 00000470    "PX13DRSC" */
+    0x60,0x7B,0x60,0x0C,0x00,0x00,0x00,0x08,  /* 00000478    "`{`....." */
+    0x60,0xA0,0x06,0x93,0x60,0x00,0xA4,0x00,  /* 00000480    "`...`..." */
+    0xA1,0x04,0xA4,0x0A,0x0F,0x14,0x21,0x5F,  /* 00000488    "......!_" */
+    0x43,0x52,0x53,0x00,0x08,0x42,0x55,0x46,  /* 00000490    "CRS..BUF" */
+    0x30,0x11,0x10,0x0A,0x0D,0x47,0x01,0xF8,  /* 00000498    "0....G.." */
+    0x03,0xF8,0x03,0x00,0x08,0x22,0x10,0x00,  /* 000004A0    ".....".." */
+    0x79,0x00,0xA4,0x42,0x55,0x46,0x30,0x5B,  /* 000004A8    "y..BUF0[" */
+    0x82,0x42,0x06,0x43,0x4F,0x4D,0x32,0x08,  /* 000004B0    ".B.COM2." */
+    0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,0x05,  /* 000004B8    "_HID.A.." */
+    0x01,0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,  /* 000004C0    ".._UID.." */
+    0x14,0x28,0x5F,0x53,0x54,0x41,0x00,0x70,  /* 000004C8    ".(_STA.p" */
+    0x5E,0x5E,0x5E,0x2E,0x50,0x58,0x31,0x33,  /* 000004D0    "^^^.PX13" */
+    0x44,0x52,0x53,0x43,0x60,0x7B,0x60,0x0C,  /* 000004D8    "DRSC`{`." */
+    0x00,0x00,0x00,0x80,0x60,0xA0,0x06,0x93,  /* 000004E0    "....`..." */
+    0x60,0x00,0xA4,0x00,0xA1,0x04,0xA4,0x0A,  /* 000004E8    "`......." */
+    0x0F,0x14,0x21,0x5F,0x43,0x52,0x53,0x00,  /* 000004F0    "..!_CRS." */
+    0x08,0x42,0x55,0x46,0x30,0x11,0x10,0x0A,  /* 000004F8    ".BUF0..." */
+    0x0D,0x47,0x01,0xF8,0x02,0xF8,0x02,0x00,  /* 00000500    ".G......" */
+    0x08,0x22,0x08,0x00,0x79,0x00,0xA4,0x42,  /* 00000508    "."..y..B" */
+    0x55,0x46,0x30,0x5B,0x82,0x40,0x05,0x50,  /* 00000510    "UF0[.@.P" */
+    0x58,0x31,0x33,0x08,0x5F,0x41,0x44,0x52,  /* 00000518    "X13._ADR" */
+    0x0C,0x03,0x00,0x01,0x00,0x5B,0x80,0x50,  /* 00000520    ".....[.P" */
+    0x31,0x33,0x43,0x02,0x0A,0x5C,0x0A,0x24,  /* 00000528    "13C..\.$" */
+    0x5B,0x81,0x33,0x50,0x31,0x33,0x43,0x03,  /* 00000530    "[.3P13C." */
+    0x44,0x52,0x53,0x41,0x20,0x44,0x52,0x53,  /* 00000538    "DRSA DRS" */
+    0x42,0x20,0x44,0x52,0x53,0x43,0x20,0x44,  /* 00000540    "B DRSC D" */
+    0x52,0x53,0x45,0x20,0x44,0x52,0x53,0x46,  /* 00000548    "RSE DRSF" */
+    0x20,0x44,0x52,0x53,0x47,0x20,0x44,0x52,  /* 00000550    " DRSG DR" */
+    0x53,0x48,0x20,0x44,0x52,0x53,0x49,0x20,  /* 00000558    "SH DRSI " */
+    0x44,0x52,0x53,0x4A,0x20,0x10,0x4F,0x2E,  /* 00000560    "DRSJ .O." */
+    0x5F,0x53,0x42,0x5F,0x5B,0x81,0x24,0x2F,  /* 00000568    "_SB_[.$/" */
+    0x03,0x50,0x43,0x49,0x30,0x49,0x53,0x41,  /* 00000570    ".PCI0ISA" */
+    0x5F,0x50,0x34,0x30,0x43,0x01,0x50,0x52,  /* 00000578    "_P40C.PR" */
+    0x51,0x30,0x08,0x50,0x52,0x51,0x31,0x08,  /* 00000580    "Q0.PRQ1." */
+    0x50,0x52,0x51,0x32,0x08,0x50,0x52,0x51,  /* 00000588    "PRQ2.PRQ" */
+    0x33,0x08,0x5B,0x82,0x4E,0x0A,0x4C,0x4E,  /* 00000590    "3.[.N.LN" */
+    0x4B,0x41,0x08,0x5F,0x48,0x49,0x44,0x0C,  /* 00000598    "KA._HID." */
+    0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,0x49,  /* 000005A0    "A...._UI" */
+    0x44,0x01,0x08,0x5F,0x50,0x52,0x53,0x11,  /* 000005A8    "D.._PRS." */
+    0x09,0x0A,0x06,0x23,0xF8,0x1E,0x18,0x79,  /* 000005B0    "...#...y" */
+    0x00,0x14,0x1A,0x5F,0x53,0x54,0x41,0x00,  /* 000005B8    "..._STA." */
+    0x70,0x0A,0x0B,0x60,0xA0,0x0D,0x7B,0x0A,  /* 000005C0    "p..`..{." */
+    0x80,0x50,0x52,0x51,0x30,0x61,0x70,0x0A,  /* 000005C8    ".PRQ0ap." */
+    0x09,0x60,0xA4,0x60,0x14,0x11,0x5F,0x44,  /* 000005D0    ".`.`.._D" */
+    0x49,0x53,0x00,0x7D,0x50,0x52,0x51,0x30,  /* 000005D8    "IS.}PRQ0" */
+    0x0A,0x80,0x50,0x52,0x51,0x30,0x14,0x3F,  /* 000005E0    "..PRQ0.?" */
+    0x5F,0x43,0x52,0x53,0x00,0x08,0x50,0x52,  /* 000005E8    "_CRS..PR" */
+    0x52,0x30,0x11,0x09,0x0A,0x06,0x23,0x02,  /* 000005F0    "R0....#." */
+    0x00,0x18,0x79,0x00,0x8B,0x50,0x52,0x52,  /* 000005F8    "..y..PRR" */
+    0x30,0x01,0x54,0x4D,0x50,0x5F,0x70,0x50,  /* 00000600    "0.TMP_pP" */
+    0x52,0x51,0x30,0x60,0xA0,0x0C,0x95,0x60,  /* 00000608    "RQ0`...`" */
+    0x0A,0x80,0x79,0x01,0x60,0x54,0x4D,0x50,  /* 00000610    "..y.`TMP" */
+    0x5F,0xA1,0x07,0x70,0x00,0x54,0x4D,0x50,  /* 00000618    "_..p.TMP" */
+    0x5F,0xA4,0x50,0x52,0x52,0x30,0x14,0x1B,  /* 00000620    "_.PRR0.." */
+    0x5F,0x53,0x52,0x53,0x01,0x8B,0x68,0x01,  /* 00000628    "_SRS..h." */
+    0x54,0x4D,0x50,0x5F,0x82,0x54,0x4D,0x50,  /* 00000630    "TMP_.TMP" */
+    0x5F,0x60,0x76,0x60,0x70,0x60,0x50,0x52,  /* 00000638    "_`v`p`PR" */
+    0x51,0x30,0x5B,0x82,0x4F,0x0A,0x4C,0x4E,  /* 00000640    "Q0[.O.LN" */
+    0x4B,0x42,0x08,0x5F,0x48,0x49,0x44,0x0C,  /* 00000648    "KB._HID." */
+    0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,0x49,  /* 00000650    "A...._UI" */
+    0x44,0x0A,0x02,0x08,0x5F,0x50,0x52,0x53,  /* 00000658    "D..._PRS" */
+    0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E,0x18,  /* 00000660    "....#..." */
+    0x79,0x00,0x14,0x1A,0x5F,0x53,0x54,0x41,  /* 00000668    "y..._STA" */
+    0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D,0x7B,  /* 00000670    ".p..`..{" */
+    0x0A,0x80,0x50,0x52,0x51,0x31,0x61,0x70,  /* 00000678    "..PRQ1ap" */
+    0x0A,0x09,0x60,0xA4,0x60,0x14,0x11,0x5F,  /* 00000680    "..`.`.._" */
+    0x44,0x49,0x53,0x00,0x7D,0x50,0x52,0x51,  /* 00000688    "DIS.}PRQ" */
+    0x31,0x0A,0x80,0x50,0x52,0x51,0x31,0x14,  /* 00000690    "1..PRQ1." */
+    0x3F,0x5F,0x43,0x52,0x53,0x00,0x08,0x50,  /* 00000698    "?_CRS..P" */
+    0x52,0x52,0x30,0x11,0x09,0x0A,0x06,0x23,  /* 000006A0    "RR0....#" */
+    0x02,0x00,0x18,0x79,0x00,0x8B,0x50,0x52,  /* 000006A8    "...y..PR" */
+    0x52,0x30,0x01,0x54,0x4D,0x50,0x5F,0x70,  /* 000006B0    "R0.TMP_p" */
+    0x50,0x52,0x51,0x31,0x60,0xA0,0x0C,0x95,  /* 000006B8    "PRQ1`..." */
+    0x60,0x0A,0x80,0x79,0x01,0x60,0x54,0x4D,  /* 000006C0    "`..y.`TM" */
+    0x50,0x5F,0xA1,0x07,0x70,0x00,0x54,0x4D,  /* 000006C8    "P_..p.TM" */
+    0x50,0x5F,0xA4,0x50,0x52,0x52,0x30,0x14,  /* 000006D0    "P_.PRR0." */
+    0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B,0x68,  /* 000006D8    "._SRS..h" */
+    0x01,0x54,0x4D,0x50,0x5F,0x82,0x54,0x4D,  /* 000006E0    ".TMP_.TM" */
+    0x50,0x5F,0x60,0x76,0x60,0x70,0x60,0x50,  /* 000006E8    "P_`v`p`P" */
+    0x52,0x51,0x31,0x5B,0x82,0x4F,0x0A,0x4C,  /* 000006F0    "RQ1[.O.L" */
+    0x4E,0x4B,0x43,0x08,0x5F,0x48,0x49,0x44,  /* 000006F8    "NKC._HID" */
+    0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,0x55,  /* 00000700    ".A...._U" */
+    0x49,0x44,0x0A,0x03,0x08,0x5F,0x50,0x52,  /* 00000708    "ID..._PR" */
+    0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E,  /* 00000710    "S....#.." */
+    0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,0x54,  /* 00000718    ".y..._ST" */
+    0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D,  /* 00000720    "A.p..`.." */
+    0x7B,0x0A,0x80,0x50,0x52,0x51,0x32,0x61,  /* 00000728    "{..PRQ2a" */
+    0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,0x11,  /* 00000730    "p..`.`.." */
+    0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,0x52,  /* 00000738    "_DIS.}PR" */
+    0x51,0x32,0x0A,0x80,0x50,0x52,0x51,0x32,  /* 00000740    "Q2..PRQ2" */
+    0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,0x08,  /* 00000748    ".?_CRS.." */
+    0x50,0x52,0x52,0x30,0x11,0x09,0x0A,0x06,  /* 00000750    "PRR0...." */
+    0x23,0x02,0x00,0x18,0x79,0x00,0x8B,0x50,  /* 00000758    "#...y..P" */
+    0x52,0x52,0x30,0x01,0x54,0x4D,0x50,0x5F,  /* 00000760    "RR0.TMP_" */
+    0x70,0x50,0x52,0x51,0x32,0x60,0xA0,0x0C,  /* 00000768    "pPRQ2`.." */
+    0x95,0x60,0x0A,0x80,0x79,0x01,0x60,0x54,  /* 00000770    ".`..y.`T" */
+    0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,0x54,  /* 00000778    "MP_..p.T" */
+    0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,0x30,  /* 00000780    "MP_.PRR0" */
+    0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B,  /* 00000788    ".._SRS.." */
+    0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,0x54,  /* 00000790    "h.TMP_.T" */
+    0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,0x60,  /* 00000798    "MP_`v`p`" */
+    0x50,0x52,0x51,0x32,0x5B,0x82,0x4F,0x0A,  /* 000007A0    "PRQ2[.O." */
+    0x4C,0x4E,0x4B,0x44,0x08,0x5F,0x48,0x49,  /* 000007A8    "LNKD._HI" */
+    0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F,  /* 000007B0    "D.A...._" */
+    0x55,0x49,0x44,0x0A,0x04,0x08,0x5F,0x50,  /* 000007B8    "UID..._P" */
+    0x52,0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,  /* 000007C0    "RS....#." */
+    0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,  /* 000007C8    "..y..._S" */
+    0x54,0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,  /* 000007D0    "TA.p..`." */
+    0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51,0x33,  /* 000007D8    ".{..PRQ3" */
+    0x61,0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,  /* 000007E0    "ap..`.`." */
+    0x11,0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,  /* 000007E8    "._DIS.}P" */
+    0x52,0x51,0x33,0x0A,0x80,0x50,0x52,0x51,  /* 000007F0    "RQ3..PRQ" */
+    0x33,0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,  /* 000007F8    "3.?_CRS." */
+    0x08,0x50,0x52,0x52,0x30,0x11,0x09,0x0A,  /* 00000800    ".PRR0..." */
+    0x06,0x23,0x02,0x00,0x18,0x79,0x00,0x8B,  /* 00000808    ".#...y.." */
+    0x50,0x52,0x52,0x30,0x01,0x54,0x4D,0x50,  /* 00000810    "PRR0.TMP" */
+    0x5F,0x70,0x50,0x52,0x51,0x33,0x60,0xA0,  /* 00000818    "_pPRQ3`." */
+    0x0C,0x95,0x60,0x0A,0x80,0x79,0x01,0x60,  /* 00000820    "..`..y.`" */
+    0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,  /* 00000828    "TMP_..p." */
+    0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,  /* 00000830    "TMP_.PRR" */
+    0x30,0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,  /* 00000838    "0.._SRS." */
+    0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,  /* 00000840    ".h.TMP_." */
+    0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,  /* 00000848    "TMP_`v`p" */
+    0x60,0x50,0x52,0x51,0x33,0x08,0x5F,0x53,  /* 00000850    "`PRQ3._S" */
+    0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00,  /* 00000858    "5_......" */
+    0x00,
+};
diff --git a/src/post.c b/src/post.c
index aecb2e3..eeb96e7 100644
--- a/src/post.c
+++ b/src/post.c
@@ -523,8 +523,8 @@
 
     printf("BIOS - begin\n\n");
 
-    // XXX - need to do pci stuff
-    //pci_setup();
+    rombios32_init();
+
     init_boot_vectors();
 
     floppy_drive_post();
@@ -533,6 +533,8 @@
         ata_init();
 
     init_boot_vectors();
+
+    // XXX - original bios calls ata_detect before rom scan.
     rom_scan(0xc8000, 0xe0000);
 
     callrom(SEG_BIOS, OFFSET_begin_boot);
diff --git a/src/rombios32.c b/src/rombios32.c
new file mode 100644
index 0000000..68bc8c7
--- /dev/null
+++ b/src/rombios32.c
@@ -0,0 +1,1793 @@
+/////////////////////////////////////////////////////////////////////////
+// $Id: rombios32.c,v 1.22 2008/01/27 17:57:26 sshwarts Exp $
+/////////////////////////////////////////////////////////////////////////
+//
+//  32 bit Bochs BIOS init code
+//  Copyright (C) 2006 Fabrice Bellard
+//
+//  This library is free software; you can redistribute it and/or
+//  modify it under the terms of the GNU Lesser General Public
+//  License as published by the Free Software Foundation; either
+//  version 2 of the License, or (at your option) any later version.
+//
+//  This library is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+//  Lesser General Public License for more details.
+//
+//  You should have received a copy of the GNU Lesser General Public
+//  License along with this library; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301 USA
+
+#include "util.h" // BX_INFO
+#include "cmos.h" // inb_cmos
+
+#define BX_APPNAME "Bochs"
+
+#define ACPI_DATA_SIZE    0x00010000L
+#define PM_IO_BASE        0xb000
+#define SMB_IO_BASE       0xb100
+#define CPU_COUNT_ADDR    0xf000
+
+typedef signed char  int8_t;
+typedef short int16_t;
+typedef int   int32_t;
+typedef long long int64_t;
+typedef unsigned char  uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int   uint32_t;
+typedef unsigned long long uint64_t;
+
+/* if true, put the MP float table and ACPI RSDT in EBDA and the MP
+   table in RAM. Unfortunately, Linux has bugs with that, so we prefer
+   to modify the BIOS in shadow RAM */
+//#define BX_USE_EBDA_TABLES
+
+/* define it if the (emulated) hardware supports SMM mode */
+#define BX_USE_SMM
+
+#define cpuid(index, eax, ebx, ecx, edx) \
+  asm volatile ("cpuid" \
+                : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
+                : "0" (index))
+
+#define wbinvd() asm volatile("wbinvd")
+
+#define CPUID_APIC (1 << 9)
+
+#define APIC_BASE    ((uint8_t *)0xfee00000)
+#define APIC_ICR_LOW 0x300
+#define APIC_SVR     0x0F0
+#define APIC_ID      0x020
+#define APIC_LVT3    0x370
+
+#define APIC_ENABLED 0x0100
+
+#define AP_BOOT_ADDR 0x10000
+
+#define MPTABLE_MAX_SIZE  0x00002000
+#define SMI_CMD_IO_ADDR   0xb2
+
+#define BIOS_TMP_STORAGE  0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
+
+static inline void writel(void *addr, uint32_t val)
+{
+    *(volatile uint32_t *)addr = val;
+}
+
+static inline void writew(void *addr, uint16_t val)
+{
+    *(volatile uint16_t *)addr = val;
+}
+
+static inline void writeb(void *addr, uint8_t val)
+{
+    *(volatile uint8_t *)addr = val;
+}
+
+static inline uint32_t readl(const void *addr)
+{
+    return *(volatile const uint32_t *)addr;
+}
+
+static inline uint16_t readw(const void *addr)
+{
+    return *(volatile const uint16_t *)addr;
+}
+
+static inline uint8_t readb(const void *addr)
+{
+    return *(volatile const uint8_t *)addr;
+}
+
+int smp_cpus;
+uint32_t cpuid_signature;
+uint32_t cpuid_features;
+uint32_t cpuid_ext_features;
+unsigned long ram_size;
+uint8_t bios_uuid[16];
+#ifdef BX_USE_EBDA_TABLES
+unsigned long ebda_cur_addr;
+#endif
+int acpi_enabled;
+uint32_t pm_io_base, smb_io_base;
+int pm_sci_int;
+unsigned long bios_table_cur_addr;
+unsigned long bios_table_end_addr;
+
+void uuid_probe(void)
+{
+#ifdef BX_QEMU
+    uint32_t eax, ebx, ecx, edx;
+
+    // check if backdoor port exists
+    asm volatile ("outl %%eax, %%dx"
+        : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+        : "a" (0x564d5868), "c" (0xa), "d" (0x5658));
+    if (ebx == 0x564d5868) {
+        uint32_t *uuid_ptr = (uint32_t *)bios_uuid;
+        // get uuid
+        asm volatile ("outl %%eax, %%dx"
+            : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+            : "a" (0x564d5868), "c" (0x13), "d" (0x5658));
+        uuid_ptr[0] = eax;
+        uuid_ptr[1] = ebx;
+        uuid_ptr[2] = ecx;
+        uuid_ptr[3] = edx;
+    } else
+#endif
+    {
+        // UUID not set
+        memset(bios_uuid, 0, 16);
+    }
+}
+
+void cpu_probe(void)
+{
+    uint32_t eax, ebx, ecx, edx;
+    cpuid(1, eax, ebx, ecx, edx);
+    cpuid_signature = eax;
+    cpuid_features = edx;
+    cpuid_ext_features = ecx;
+}
+
+void ram_probe(void)
+{
+  if (inb_cmos(0x34) | inb_cmos(0x35))
+    ram_size = (inb_cmos(0x34) | (inb_cmos(0x35) << 8)) * 65536 +
+        16 * 1024 * 1024;
+  else
+    ram_size = (inb_cmos(0x17) | (inb_cmos(0x18) << 8)) * 1024;
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
+#endif
+    BX_INFO("ram_size=0x%08lx\n", ram_size);
+}
+
+/****************************************************/
+/* SMP probe */
+
+extern uint8_t smp_ap_boot_code_start;
+extern uint8_t smp_ap_boot_code_end;
+
+/* find the number of CPUs by launching a SIPI to them */
+void smp_probe(void)
+{
+    uint32_t val, sipi_vector;
+
+    smp_cpus = 1;
+    if (cpuid_features & CPUID_APIC) {
+
+        /* enable local APIC */
+        val = readl(APIC_BASE + APIC_SVR);
+        val |= APIC_ENABLED;
+        writel(APIC_BASE + APIC_SVR, val);
+
+        writew((void *)CPU_COUNT_ADDR, 1);
+        /* copy AP boot code */
+        memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
+               &smp_ap_boot_code_end - &smp_ap_boot_code_start);
+
+        /* broadcast SIPI */
+        writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
+        sipi_vector = AP_BOOT_ADDR >> 12;
+        writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
+
+        usleep(10*1000);
+
+        smp_cpus = readw((void *)CPU_COUNT_ADDR);
+    }
+    BX_INFO("Found %d cpu(s)\n", smp_cpus);
+}
+
+/****************************************************/
+/* PCI init */
+
+#define PCI_ADDRESS_SPACE_MEM		0x00
+#define PCI_ADDRESS_SPACE_IO		0x01
+#define PCI_ADDRESS_SPACE_MEM_PREFETCH	0x08
+
+#define PCI_ROM_SLOT 6
+#define PCI_NUM_REGIONS 7
+
+#define PCI_DEVICES_MAX 64
+
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_DEVICE_ID		0x02	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define PCI_CLASS_DEVICE        0x0a    /* Device class */
+#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
+#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
+#define PCI_MIN_GNT		0x3e	/* 8 bits */
+#define PCI_MAX_LAT		0x3f	/* 8 bits */
+
+typedef struct PCIDevice {
+    int bus;
+    int devfn;
+} PCIDevice;
+
+static uint32_t pci_bios_io_addr;
+static uint32_t pci_bios_mem_addr;
+static uint32_t pci_bios_bigmem_addr;
+/* host irqs corresponding to PCI irqs A-D */
+static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
+static PCIDevice i440_pcidev;
+
+static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    outl(val, 0xcfc);
+}
+
+static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    outw(val, 0xcfc + (addr & 2));
+}
+
+static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    outb(val, 0xcfc + (addr & 3));
+}
+
+static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    return inl(0xcfc);
+}
+
+static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    return inw(0xcfc + (addr & 2));
+}
+
+static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
+{
+    outl(0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc), 0xcf8);
+    return inb(0xcfc + (addr & 3));
+}
+
+static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
+{
+    uint16_t cmd;
+    uint32_t ofs, old_addr;
+
+    if ( region_num == PCI_ROM_SLOT ) {
+        ofs = 0x30;
+    }else{
+        ofs = 0x10 + region_num * 4;
+    }
+
+    old_addr = pci_config_readl(d, ofs);
+
+    pci_config_writel(d, ofs, addr);
+    BX_INFO("region %d: 0x%08x\n", region_num, addr);
+
+    /* enable memory mappings */
+    cmd = pci_config_readw(d, PCI_COMMAND);
+    if ( region_num == PCI_ROM_SLOT )
+        cmd |= 2;
+    else if (old_addr & PCI_ADDRESS_SPACE_IO)
+        cmd |= 1;
+    else
+        cmd |= 2;
+    pci_config_writew(d, PCI_COMMAND, cmd);
+}
+
+/* return the global irq number corresponding to a given device irq
+   pin. We could also use the bus number to have a more precise
+   mapping. */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+{
+    int slot_addend;
+    slot_addend = (pci_dev->devfn >> 3) - 1;
+    return (irq_num + slot_addend) & 3;
+}
+
+static void
+copy_bios(PCIDevice *d, int v)
+{
+    pci_config_writeb(d, 0x59, v);
+    memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
+}
+
+// Test if 'addr' is in the range from 'start'..'start+size'
+#define IN_RANGE(addr, start, size) ({   \
+            u32 __addr = (addr);         \
+            u32 __start = (start);       \
+            u32 __size = (size);         \
+            (__addr - __start < __size); \
+        })
+
+static void bios_shadow_init(PCIDevice *d)
+{
+    bios_table_cur_addr = 0xf0000 | OFFSET_freespace2_start;
+    bios_table_end_addr = 0xf0000 | OFFSET_freespace2_end;
+    BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
+            bios_table_cur_addr, bios_table_end_addr);
+
+    /* remap the BIOS to shadow RAM an keep it read/write while we
+       are writing tables */
+    int v = pci_config_readb(d, 0x59);
+    v &= 0xcf;
+    pci_config_writeb(d, 0x59, v);
+    memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
+    v |= 0x30;
+
+    if (IN_RANGE((u32)copy_bios, 0xf0000, 0x10000)) {
+        // Current code is in shadowed area.  Perform the copy from
+        // the code that is in the temporary location.
+        u32 pos = (u32)copy_bios - 0xf0000 + BIOS_TMP_STORAGE;
+        void (*func)(PCIDevice *, int) = (void*)pos;
+        func(d, v);
+    } else {
+        copy_bios(d, v);
+    }
+
+    i440_pcidev = *d;
+}
+
+static void bios_lock_shadow_ram(void)
+{
+    PCIDevice *d = &i440_pcidev;
+    int v;
+
+    wbinvd();
+    v = pci_config_readb(d, 0x59);
+    v = (v & 0x0f) | (0x10);
+    pci_config_writeb(d, 0x59, v);
+}
+
+static void pci_bios_init_bridges(PCIDevice *d)
+{
+    uint16_t vendor_id, device_id;
+
+    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+    device_id = pci_config_readw(d, PCI_DEVICE_ID);
+
+    if (vendor_id == 0x8086 && device_id == 0x7000) {
+        int i, irq;
+        uint8_t elcr[2];
+
+        /* PIIX3 bridge */
+
+        elcr[0] = 0x00;
+        elcr[1] = 0x00;
+        for(i = 0; i < 4; i++) {
+            irq = pci_irqs[i];
+            /* set to trigger level */
+            elcr[irq >> 3] |= (1 << (irq & 7));
+            /* activate irq remapping in PIIX */
+            pci_config_writeb(d, 0x60 + i, irq);
+        }
+        outb(elcr[0], 0x4d0);
+        outb(elcr[1], 0x4d1);
+        BX_INFO("PIIX3 init: elcr=%02x %02x\n",
+                elcr[0], elcr[1]);
+    } else if (vendor_id == 0x8086 && device_id == 0x1237) {
+        /* i440 PCI bridge */
+        bios_shadow_init(d);
+    }
+}
+
+asm(
+    ".globl smp_ap_boot_code_start\n"
+    ".globl smp_ap_boot_code_end\n"
+    ".global smm_relocation_start\n"
+    ".global smm_relocation_end\n"
+    ".global smm_code_start\n"
+    ".global smm_code_end\n"
+
+    "  .code16\n"
+    "smp_ap_boot_code_start:\n"
+    "  xor %ax, %ax\n"
+    "  mov %ax, %ds\n"
+    "  incw " __stringify(CPU_COUNT_ADDR) "\n"
+    "1:\n"
+    "  hlt\n"
+    "  jmp 1b\n"
+    "smp_ap_boot_code_end:\n"
+
+    /* code to relocate SMBASE to 0xa0000 */
+    "smm_relocation_start:\n"
+    "  mov $0x38000 + 0x7efc, %ebx\n"
+    "  addr32 mov (%ebx), %al\n"  /* revision ID to see if x86_64 or x86 */
+    "  cmp $0x64, %al\n"
+    "  je 1f\n"
+    "  mov $0x38000 + 0x7ef8, %ebx\n"
+    "  jmp 2f\n"
+    "1:\n"
+    "  mov $0x38000 + 0x7f00, %ebx\n"
+    "2:\n"
+    "  movl $0xa0000, %eax\n"
+    "  addr32 movl %eax, (%ebx)\n"
+    /* indicate to the BIOS that the SMM code was executed */
+    "  mov $0x00, %al\n"
+    "  movw $0xb3, %dx\n"
+    "  outb %al, %dx\n"
+    "  rsm\n"
+    "smm_relocation_end:\n"
+
+    /* minimal SMM code to enable or disable ACPI */
+    "smm_code_start:\n"
+    "  movw $0xb2, %dx\n"
+    "  inb %dx, %al\n"
+    "  cmp $0xf0, %al\n"
+    "  jne 1f\n"
+
+    /* ACPI disable */
+    "  mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+    "  inw %dx, %ax\n"
+    "  andw $~1, %ax\n"
+    "  outw %ax, %dx\n"
+
+    "  jmp 2f\n"
+
+    "1:\n"
+    "  cmp $0xf1, %al\n"
+    "  jne 2f\n"
+
+    /* ACPI enable */
+    "  mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+    "  inw %dx, %ax\n"
+    "  orw $1, %ax\n"
+    "  outw %ax, %dx\n"
+
+    "2:\n"
+    "  rsm\n"
+    "smm_code_end:\n"
+    "  .code32\n"
+    );
+
+extern uint8_t smm_relocation_start, smm_relocation_end;
+extern uint8_t smm_code_start, smm_code_end;
+
+#ifdef BX_USE_SMM
+static void smm_init(PCIDevice *d)
+{
+    uint32_t value;
+
+    /* check if SMM init is already done */
+    value = pci_config_readl(d, 0x58);
+    if ((value & (1 << 25)) == 0) {
+
+        /* copy the SMM relocation code */
+        memcpy((void *)0x38000, &smm_relocation_start,
+               &smm_relocation_end - &smm_relocation_start);
+
+        /* enable SMI generation when writing to the APMC register */
+        pci_config_writel(d, 0x58, value | (1 << 25));
+
+        /* init APM status port */
+        outb(0x01, 0xb3);
+
+        /* raise an SMI interrupt */
+        outb(0x00, 0xb2);
+
+        /* wait until SMM code executed */
+        while (inb(0xb3) != 0x00);
+
+        /* enable the SMM memory window */
+        pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
+
+        /* copy the SMM code */
+        memcpy((void *)0xa8000, &smm_code_start,
+               &smm_code_end - &smm_code_start);
+        wbinvd();
+
+        /* close the SMM memory window and enable normal SMM */
+        pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
+    }
+}
+#endif
+
+static void pci_bios_init_device(PCIDevice *d)
+{
+    int class;
+    uint32_t *paddr;
+    int i, pin, pic_irq, vendor_id, device_id;
+
+    class = pci_config_readw(d, PCI_CLASS_DEVICE);
+    vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+    device_id = pci_config_readw(d, PCI_DEVICE_ID);
+    BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n",
+            d->bus, d->devfn, vendor_id, device_id);
+    switch(class) {
+    case 0x0101:
+        if (vendor_id == 0x8086 && device_id == 0x7010) {
+            /* PIIX3 IDE */
+            pci_config_writew(d, 0x40, 0x8000); // enable IDE0
+            pci_config_writew(d, 0x42, 0x8000); // enable IDE1
+            goto default_map;
+        } else {
+            /* IDE: we map it as in ISA mode */
+            pci_set_io_region_addr(d, 0, 0x1f0);
+            pci_set_io_region_addr(d, 1, 0x3f4);
+            pci_set_io_region_addr(d, 2, 0x170);
+            pci_set_io_region_addr(d, 3, 0x374);
+        }
+        break;
+    case 0x0300:
+        if (vendor_id != 0x1234)
+            goto default_map;
+        /* VGA: map frame buffer to default Bochs VBE address */
+        pci_set_io_region_addr(d, 0, 0xE0000000);
+        break;
+    case 0x0800:
+        /* PIC */
+        if (vendor_id == 0x1014) {
+            /* IBM */
+            if (device_id == 0x0046 || device_id == 0xFFFF) {
+                /* MPIC & MPIC2 */
+                pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
+            }
+        }
+        break;
+    case 0xff00:
+        if (vendor_id == 0x0106b &&
+            (device_id == 0x0017 || device_id == 0x0022)) {
+            /* macio bridge */
+            pci_set_io_region_addr(d, 0, 0x80800000);
+        }
+        break;
+    default:
+    default_map:
+        /* default memory mappings */
+        for(i = 0; i < PCI_NUM_REGIONS; i++) {
+            int ofs;
+            uint32_t val, size ;
+
+            if (i == PCI_ROM_SLOT)
+                ofs = 0x30;
+            else
+                ofs = 0x10 + i * 4;
+            pci_config_writel(d, ofs, 0xffffffff);
+            val = pci_config_readl(d, ofs);
+            if (val != 0) {
+                size = (~(val & ~0xf)) + 1;
+                if (val & PCI_ADDRESS_SPACE_IO)
+                    paddr = &pci_bios_io_addr;
+                else if (size >= 0x04000000)
+                    paddr = &pci_bios_bigmem_addr;
+                else
+                    paddr = &pci_bios_mem_addr;
+                *paddr = (*paddr + size - 1) & ~(size - 1);
+                pci_set_io_region_addr(d, i, *paddr);
+                *paddr += size;
+            }
+        }
+        break;
+    }
+
+    /* map the interrupt */
+    pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
+    if (pin != 0) {
+        pin = pci_slot_get_pirq(d, pin - 1);
+        pic_irq = pci_irqs[pin];
+        pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
+    }
+
+    if (vendor_id == 0x8086 && device_id == 0x7113) {
+        /* PIIX4 Power Management device (for ACPI) */
+        pm_io_base = PM_IO_BASE;
+        pci_config_writel(d, 0x40, pm_io_base | 1);
+        pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
+        smb_io_base = SMB_IO_BASE;
+        pci_config_writel(d, 0x90, smb_io_base | 1);
+        pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
+        pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
+#ifdef BX_USE_SMM
+        smm_init(d);
+#endif
+        acpi_enabled = 1;
+    }
+}
+
+void pci_for_each_device(void (*init_func)(PCIDevice *d))
+{
+    PCIDevice d1, *d = &d1;
+    int bus, devfn;
+    uint16_t vendor_id, device_id;
+
+    for(bus = 0; bus < 1; bus++) {
+        for(devfn = 0; devfn < 256; devfn++) {
+            d->bus = bus;
+            d->devfn = devfn;
+            vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
+            device_id = pci_config_readw(d, PCI_DEVICE_ID);
+            if (vendor_id != 0xffff || device_id != 0xffff) {
+                init_func(d);
+            }
+        }
+    }
+}
+
+void pci_bios_init(void)
+{
+    pci_bios_io_addr = 0xc000;
+    pci_bios_mem_addr = 0xf0000000;
+    pci_bios_bigmem_addr = ram_size;
+    if (pci_bios_bigmem_addr < 0x90000000)
+        pci_bios_bigmem_addr = 0x90000000;
+
+    pci_for_each_device(pci_bios_init_bridges);
+
+    pci_for_each_device(pci_bios_init_device);
+}
+
+/****************************************************/
+/* Multi Processor table init */
+
+static void putb(uint8_t **pp, int val)
+{
+    uint8_t *q;
+    q = *pp;
+    *q++ = val;
+    *pp = q;
+}
+
+static void putstr(uint8_t **pp, const char *str)
+{
+    uint8_t *q;
+    q = *pp;
+    while (*str)
+        *q++ = *str++;
+    *pp = q;
+}
+
+static void putle16(uint8_t **pp, int val)
+{
+    uint8_t *q;
+    q = *pp;
+    *q++ = val;
+    *q++ = val >> 8;
+    *pp = q;
+}
+
+static void putle32(uint8_t **pp, int val)
+{
+    uint8_t *q;
+    q = *pp;
+    *q++ = val;
+    *q++ = val >> 8;
+    *q++ = val >> 16;
+    *q++ = val >> 24;
+    *pp = q;
+}
+
+static int mpf_checksum(const uint8_t *data, int len)
+{
+    int sum, i;
+    sum = 0;
+    for(i = 0; i < len; i++)
+        sum += data[i];
+    return sum & 0xff;
+}
+
+static unsigned long align(unsigned long addr, unsigned long v)
+{
+    return (addr + v - 1) & ~(v - 1);
+}
+
+static void mptable_init(void)
+{
+    uint8_t *mp_config_table, *q, *float_pointer_struct;
+    int ioapic_id, i, len;
+    int mp_config_table_size;
+
+#ifdef BX_QEMU
+    if (smp_cpus <= 1)
+        return;
+#endif
+
+#ifdef BX_USE_EBDA_TABLES
+    mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
+#else
+    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    mp_config_table = (uint8_t *)bios_table_cur_addr;
+#endif
+    q = mp_config_table;
+    putstr(&q, "PCMP"); /* "PCMP signature */
+    putle16(&q, 0); /* table length (patched later) */
+    putb(&q, 4); /* spec rev */
+    putb(&q, 0); /* checksum (patched later) */
+#ifdef BX_QEMU
+    putstr(&q, "QEMUCPU "); /* OEM id */
+#else
+    putstr(&q, "BOCHSCPU");
+#endif
+    putstr(&q, "0.1         "); /* vendor id */
+    putle32(&q, 0); /* OEM table ptr */
+    putle16(&q, 0); /* OEM table size */
+    putle16(&q, smp_cpus + 18); /* entry count */
+    putle32(&q, 0xfee00000); /* local APIC addr */
+    putle16(&q, 0); /* ext table length */
+    putb(&q, 0); /* ext table checksum */
+    putb(&q, 0); /* reserved */
+
+    for(i = 0; i < smp_cpus; i++) {
+        putb(&q, 0); /* entry type = processor */
+        putb(&q, i); /* APIC id */
+        putb(&q, 0x11); /* local APIC version number */
+        if (i == 0)
+            putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
+        else
+            putb(&q, 1); /* cpu flags: enabled */
+        putb(&q, 0); /* cpu signature */
+        putb(&q, 6);
+        putb(&q, 0);
+        putb(&q, 0);
+        putle16(&q, 0x201); /* feature flags */
+        putle16(&q, 0);
+
+        putle16(&q, 0); /* reserved */
+        putle16(&q, 0);
+        putle16(&q, 0);
+        putle16(&q, 0);
+    }
+
+    /* isa bus */
+    putb(&q, 1); /* entry type = bus */
+    putb(&q, 0); /* bus ID */
+    putstr(&q, "ISA   ");
+
+    /* ioapic */
+    ioapic_id = smp_cpus;
+    putb(&q, 2); /* entry type = I/O APIC */
+    putb(&q, ioapic_id); /* apic ID */
+    putb(&q, 0x11); /* I/O APIC version number */
+    putb(&q, 1); /* enable */
+    putle32(&q, 0xfec00000); /* I/O APIC addr */
+
+    /* irqs */
+    for(i = 0; i < 16; i++) {
+        putb(&q, 3); /* entry type = I/O interrupt */
+        putb(&q, 0); /* interrupt type = vectored interrupt */
+        putb(&q, 0); /* flags: po=0, el=0 */
+        putb(&q, 0);
+        putb(&q, 0); /* source bus ID = ISA */
+        putb(&q, i); /* source bus IRQ */
+        putb(&q, ioapic_id); /* dest I/O APIC ID */
+        putb(&q, i); /* dest I/O APIC interrupt in */
+    }
+    /* patch length */
+    len = q - mp_config_table;
+    mp_config_table[4] = len;
+    mp_config_table[5] = len >> 8;
+
+    mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
+
+    mp_config_table_size = q - mp_config_table;
+
+#ifndef BX_USE_EBDA_TABLES
+    bios_table_cur_addr += mp_config_table_size;
+#endif
+
+    /* floating pointer structure */
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr = align(ebda_cur_addr, 16);
+    float_pointer_struct = (uint8_t *)ebda_cur_addr;
+#else
+    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    float_pointer_struct = (uint8_t *)bios_table_cur_addr;
+#endif
+    q = float_pointer_struct;
+    putstr(&q, "_MP_");
+    /* pointer to MP config table */
+    putle32(&q, (unsigned long)mp_config_table);
+
+    putb(&q, 1); /* length in 16 byte units */
+    putb(&q, 4); /* MP spec revision */
+    putb(&q, 0); /* checksum (patched later) */
+    putb(&q, 0); /* MP feature byte 1 */
+
+    putb(&q, 0);
+    putb(&q, 0);
+    putb(&q, 0);
+    putb(&q, 0);
+    float_pointer_struct[10] =
+        -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr += (q - float_pointer_struct);
+#else
+    bios_table_cur_addr += (q - float_pointer_struct);
+#endif
+    BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
+            (unsigned long)float_pointer_struct,
+            (unsigned long)mp_config_table,
+            mp_config_table_size);
+}
+
+/****************************************************/
+/* ACPI tables init */
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+   BSD license) */
+
+#define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
+	uint8_t                            signature [4];          /* ACPI signature (4 ASCII characters) */\
+	uint32_t                             length;                 /* Length of table, in bytes, including header */\
+	uint8_t                              revision;               /* ACPI Specification minor version # */\
+	uint8_t                              checksum;               /* To make sum of entire table == 0 */\
+	uint8_t                            oem_id [6];             /* OEM identification */\
+	uint8_t                            oem_table_id [8];       /* OEM table identification */\
+	uint32_t                             oem_revision;           /* OEM revision number */\
+	uint8_t                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
+	uint32_t                             asl_compiler_revision;  /* ASL compiler revision number */
+
+
+struct acpi_table_header         /* ACPI common table header */
+{
+	ACPI_TABLE_HEADER_DEF
+};
+
+struct rsdp_descriptor         /* Root System Descriptor Pointer */
+{
+	uint8_t                            signature [8];          /* ACPI signature, contains "RSD PTR " */
+	uint8_t                              checksum;               /* To make sum of struct == 0 */
+	uint8_t                            oem_id [6];             /* OEM identification */
+	uint8_t                              revision;               /* Must be 0 for 1.0, 2 for 2.0 */
+	uint32_t                             rsdt_physical_address;  /* 32-bit physical address of RSDT */
+	uint32_t                             length;                 /* XSDT Length in bytes including hdr */
+	uint64_t                             xsdt_physical_address;  /* 64-bit physical address of XSDT */
+	uint8_t                              extended_checksum;      /* Checksum of entire table */
+	uint8_t                            reserved [3];           /* Reserved field must be 0 */
+};
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+struct rsdt_descriptor_rev1
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	uint32_t                             table_offset_entry [3]; /* Array of pointers to other */
+			 /* ACPI tables */
+};
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+struct facs_descriptor_rev1
+{
+	uint8_t                            signature[4];           /* ACPI Signature */
+	uint32_t                             length;                 /* Length of structure, in bytes */
+	uint32_t                             hardware_signature;     /* Hardware configuration signature */
+	uint32_t                             firmware_waking_vector; /* ACPI OS waking vector */
+	uint32_t                             global_lock;            /* Global Lock */
+	uint32_t                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
+	uint32_t                             reserved1       : 31;   /* Must be 0 */
+	uint8_t                              resverved3 [40];        /* Reserved - must be zero */
+};
+
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+struct fadt_descriptor_rev1
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	uint32_t                             firmware_ctrl;          /* Physical address of FACS */
+	uint32_t                             dsdt;                   /* Physical address of DSDT */
+	uint8_t                              model;                  /* System Interrupt Model */
+	uint8_t                              reserved1;              /* Reserved */
+	uint16_t                             sci_int;                /* System vector of SCI interrupt */
+	uint32_t                             smi_cmd;                /* Port address of SMI command port */
+	uint8_t                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+	uint8_t                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
+	uint8_t                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
+	uint8_t                              reserved2;              /* Reserved - must be zero */
+	uint32_t                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
+	uint32_t                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
+	uint32_t                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
+	uint32_t                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
+	uint32_t                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
+	uint32_t                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
+	uint32_t                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
+	uint32_t                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
+	uint8_t                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
+	uint8_t                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
+	uint8_t                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
+	uint8_t                              pm_tmr_len;              /* Byte Length of ports at pm_tm_blk */
+	uint8_t                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
+	uint8_t                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
+	uint8_t                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
+	uint8_t                              reserved3;              /* Reserved */
+	uint16_t                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+	uint16_t                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
+	uint16_t                             flush_size;             /* Size of area read to flush caches */
+	uint16_t                             flush_stride;           /* Stride used in flushing caches */
+	uint8_t                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+	uint8_t                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+	uint8_t                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+	uint8_t                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+	uint8_t                              century;                /* Index to century in RTC CMOS RAM */
+	uint8_t                              reserved4;              /* Reserved */
+	uint8_t                              reserved4a;             /* Reserved */
+	uint8_t                              reserved4b;             /* Reserved */
+#if 0
+	uint32_t                             wb_invd         : 1;    /* The wbinvd instruction works properly */
+	uint32_t                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
+	uint32_t                             proc_c1         : 1;    /* All processors support C1 state */
+	uint32_t                             plvl2_up        : 1;    /* C2 state works on MP system */
+	uint32_t                             pwr_button      : 1;    /* Power button is handled as a generic feature */
+	uint32_t                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
+	uint32_t                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
+	uint32_t                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
+	uint32_t                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
+	uint32_t                             reserved5       : 23;   /* Reserved - must be zero */
+#else
+        uint32_t flags;
+#endif
+};
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define DUAL_PIC                0
+#define MULTIPLE_APIC           1
+
+
+/* Master MADT */
+
+struct multiple_apic_table
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	uint32_t                             local_apic_address;     /* Physical address of local APIC */
+#if 0
+	uint32_t                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
+	uint32_t                             reserved1       : 31;
+#else
+        uint32_t                             flags;
+#endif
+};
+
+
+/* Values for Type in APIC_HEADER_DEF */
+
+#define APIC_PROCESSOR          0
+#define APIC_IO                 1
+#define APIC_XRUPT_OVERRIDE     2
+#define APIC_NMI                3
+#define APIC_LOCAL_NMI          4
+#define APIC_ADDRESS_OVERRIDE   5
+#define APIC_IO_SAPIC           6
+#define APIC_LOCAL_SAPIC        7
+#define APIC_XRUPT_SOURCE       8
+#define APIC_RESERVED           9           /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define APIC_HEADER_DEF                     /* Common APIC sub-structure header */\
+	uint8_t                              type; \
+	uint8_t                              length;
+
+/* Sub-structures for MADT */
+
+struct madt_processor_apic
+{
+	APIC_HEADER_DEF
+	uint8_t                              processor_id;           /* ACPI processor id */
+	uint8_t                              local_apic_id;          /* Processor's local APIC id */
+#if 0
+	uint32_t                             processor_enabled: 1;   /* Processor is usable if set */
+	uint32_t                             reserved2       : 31;   /* Reserved, must be zero */
+#else
+        uint32_t flags;
+#endif
+};
+
+struct madt_io_apic
+{
+	APIC_HEADER_DEF
+	uint8_t                              io_apic_id;             /* I/O APIC ID */
+	uint8_t                              reserved;               /* Reserved - must be zero */
+	uint32_t                             address;                /* APIC physical address */
+	uint32_t                             interrupt;              /* Global system interrupt where INTI
+			  * lines start */
+};
+
+#include "acpi-dsdt.hex"
+
+static inline uint16_t cpu_to_le16(uint16_t x)
+{
+    return x;
+}
+
+static inline uint32_t cpu_to_le32(uint32_t x)
+{
+    return x;
+}
+
+static int acpi_checksum(const uint8_t *data, int len)
+{
+    int sum, i;
+    sum = 0;
+    for(i = 0; i < len; i++)
+        sum += data[i];
+    return (-sum) & 0xff;
+}
+
+static void acpi_build_table_header(struct acpi_table_header *h,
+                                    char *sig, int len, uint8_t rev)
+{
+    memcpy(h->signature, sig, 4);
+    h->length = cpu_to_le32(len);
+    h->revision = rev;
+#ifdef BX_QEMU
+    memcpy(h->oem_id, "QEMU  ", 6);
+    memcpy(h->oem_table_id, "QEMU", 4);
+#else
+    memcpy(h->oem_id, "BOCHS ", 6);
+    memcpy(h->oem_table_id, "BXPC", 4);
+#endif
+    memcpy(h->oem_table_id + 4, sig, 4);
+    h->oem_revision = cpu_to_le32(1);
+#ifdef BX_QEMU
+    memcpy(h->asl_compiler_id, "QEMU", 4);
+#else
+    memcpy(h->asl_compiler_id, "BXPC", 4);
+#endif
+    h->asl_compiler_revision = cpu_to_le32(1);
+    h->checksum = acpi_checksum((void *)h, len);
+}
+
+int acpi_build_processor_ssdt(uint8_t *ssdt)
+{
+    uint8_t *ssdt_ptr = ssdt;
+    int i, length;
+    int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
+
+    ssdt_ptr[9] = 0; // checksum;
+    ssdt_ptr += sizeof(struct acpi_table_header);
+
+    // caluculate the length of processor block and scope block excluding PkgLength
+    length = 0x0d * acpi_cpus + 4;
+
+    // build processor scope header
+    *(ssdt_ptr++) = 0x10; // ScopeOp
+    if (length <= 0x3e) {
+        *(ssdt_ptr++) = length + 1;
+    } else {
+        *(ssdt_ptr++) = 0x7F;
+        *(ssdt_ptr++) = (length + 2) >> 6;
+    }
+    *(ssdt_ptr++) = '_'; // Name
+    *(ssdt_ptr++) = 'P';
+    *(ssdt_ptr++) = 'R';
+    *(ssdt_ptr++) = '_';
+
+    // build object for each processor
+    for(i=0;i<acpi_cpus;i++) {
+        *(ssdt_ptr++) = 0x5B; // ProcessorOp
+        *(ssdt_ptr++) = 0x83;
+        *(ssdt_ptr++) = 0x0B; // Length
+        *(ssdt_ptr++) = 'C';  // Name (CPUxx)
+        *(ssdt_ptr++) = 'P';
+        if ((i & 0xf0) != 0)
+            *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
+        else
+            *(ssdt_ptr++) = 'U';
+        *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
+        *(ssdt_ptr++) = i;
+        *(ssdt_ptr++) = 0x10; // Processor block address
+        *(ssdt_ptr++) = 0xb0;
+        *(ssdt_ptr++) = 0;
+        *(ssdt_ptr++) = 0;
+        *(ssdt_ptr++) = 6;    // Processor block length
+    }
+
+    acpi_build_table_header((struct acpi_table_header *)ssdt,
+                            "SSDT", ssdt_ptr - ssdt, 1);
+
+    return ssdt_ptr - ssdt;
+}
+
+/* base_addr must be a multiple of 4KB */
+void acpi_bios_init(void)
+{
+    struct rsdp_descriptor *rsdp;
+    struct rsdt_descriptor_rev1 *rsdt;
+    struct fadt_descriptor_rev1 *fadt;
+    struct facs_descriptor_rev1 *facs;
+    struct multiple_apic_table *madt;
+    uint8_t *dsdt, *ssdt;
+    uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
+    uint32_t acpi_tables_size, madt_addr, madt_size;
+    int i;
+
+    /* reserve memory space for tables */
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr = align(ebda_cur_addr, 16);
+    rsdp = (void *)(ebda_cur_addr);
+    ebda_cur_addr += sizeof(*rsdp);
+#else
+    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    rsdp = (void *)(bios_table_cur_addr);
+    bios_table_cur_addr += sizeof(*rsdp);
+#endif
+
+    addr = base_addr = ram_size - ACPI_DATA_SIZE;
+    rsdt_addr = addr;
+    rsdt = (void *)(addr);
+    addr += sizeof(*rsdt);
+
+    fadt_addr = addr;
+    fadt = (void *)(addr);
+    addr += sizeof(*fadt);
+
+    /* XXX: FACS should be in RAM */
+    addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
+    facs_addr = addr;
+    facs = (void *)(addr);
+    addr += sizeof(*facs);
+
+    dsdt_addr = addr;
+    dsdt = (void *)(addr);
+    addr += sizeof(AmlCode);
+
+    ssdt_addr = addr;
+    ssdt = (void *)(addr);
+    addr += acpi_build_processor_ssdt(ssdt);
+
+    addr = (addr + 7) & ~7;
+    madt_addr = addr;
+    madt_size = sizeof(*madt) +
+        sizeof(struct madt_processor_apic) * smp_cpus +
+        sizeof(struct madt_io_apic);
+    madt = (void *)(addr);
+    addr += madt_size;
+
+    acpi_tables_size = addr - base_addr;
+
+    BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
+            (unsigned long)rsdp,
+            (unsigned long)rsdt, acpi_tables_size);
+
+    /* RSDP */
+    memset(rsdp, 0, sizeof(*rsdp));
+    memcpy(rsdp->signature, "RSD PTR ", 8);
+#ifdef BX_QEMU
+    memcpy(rsdp->oem_id, "QEMU  ", 6);
+#else
+    memcpy(rsdp->oem_id, "BOCHS ", 6);
+#endif
+    rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
+    rsdp->checksum = acpi_checksum((void *)rsdp, 20);
+
+    /* RSDT */
+    memset(rsdt, 0, sizeof(*rsdt));
+    rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
+    rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
+    rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
+    acpi_build_table_header((struct acpi_table_header *)rsdt,
+                            "RSDT", sizeof(*rsdt), 1);
+
+    /* FADT */
+    memset(fadt, 0, sizeof(*fadt));
+    fadt->firmware_ctrl = cpu_to_le32(facs_addr);
+    fadt->dsdt = cpu_to_le32(dsdt_addr);
+    fadt->model = 1;
+    fadt->reserved1 = 0;
+    fadt->sci_int = cpu_to_le16(pm_sci_int);
+    fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
+    fadt->acpi_enable = 0xf1;
+    fadt->acpi_disable = 0xf0;
+    fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
+    fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
+    fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
+    fadt->pm1_evt_len = 4;
+    fadt->pm1_cnt_len = 2;
+    fadt->pm_tmr_len = 4;
+    fadt->plvl2_lat = cpu_to_le16(50);
+    fadt->plvl3_lat = cpu_to_le16(50);
+    fadt->plvl3_lat = cpu_to_le16(50);
+    /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
+    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
+    acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
+                            sizeof(*fadt), 1);
+
+    /* FACS */
+    memset(facs, 0, sizeof(*facs));
+    memcpy(facs->signature, "FACS", 4);
+    facs->length = cpu_to_le32(sizeof(*facs));
+
+    /* DSDT */
+    memcpy(dsdt, AmlCode, sizeof(AmlCode));
+
+    /* MADT */
+    {
+        struct madt_processor_apic *apic;
+        struct madt_io_apic *io_apic;
+
+        memset(madt, 0, madt_size);
+        madt->local_apic_address = cpu_to_le32(0xfee00000);
+        madt->flags = cpu_to_le32(1);
+        apic = (void *)(madt + 1);
+        for(i=0;i<smp_cpus;i++) {
+            apic->type = APIC_PROCESSOR;
+            apic->length = sizeof(*apic);
+            apic->processor_id = i;
+            apic->local_apic_id = i;
+            apic->flags = cpu_to_le32(1);
+            apic++;
+        }
+        io_apic = (void *)apic;
+        io_apic->type = APIC_IO;
+        io_apic->length = sizeof(*io_apic);
+        io_apic->io_apic_id = smp_cpus;
+        io_apic->address = cpu_to_le32(0xfec00000);
+        io_apic->interrupt = cpu_to_le32(0);
+
+        acpi_build_table_header((struct acpi_table_header *)madt,
+                                "APIC", madt_size, 1);
+    }
+}
+
+/* SMBIOS entry point -- must be written to a 16-bit aligned address
+   between 0xf0000 and 0xfffff.
+ */
+struct smbios_entry_point {
+	char anchor_string[4];
+	uint8_t checksum;
+	uint8_t length;
+	uint8_t smbios_major_version;
+	uint8_t smbios_minor_version;
+	uint16_t max_structure_size;
+	uint8_t entry_point_revision;
+	uint8_t formatted_area[5];
+	char intermediate_anchor_string[5];
+	uint8_t intermediate_checksum;
+	uint16_t structure_table_length;
+	uint32_t structure_table_address;
+	uint16_t number_of_structures;
+	uint8_t smbios_bcd_revision;
+} __attribute__((__packed__));
+
+/* This goes at the beginning of every SMBIOS structure. */
+struct smbios_structure_header {
+	uint8_t type;
+	uint8_t length;
+	uint16_t handle;
+} __attribute__((__packed__));
+
+/* SMBIOS type 0 - BIOS Information */
+struct smbios_type_0 {
+	struct smbios_structure_header header;
+	uint8_t vendor_str;
+	uint8_t bios_version_str;
+	uint16_t bios_starting_address_segment;
+	uint8_t bios_release_date_str;
+	uint8_t bios_rom_size;
+	uint8_t bios_characteristics[8];
+	uint8_t bios_characteristics_extension_bytes[2];
+	uint8_t system_bios_major_release;
+	uint8_t system_bios_minor_release;
+	uint8_t embedded_controller_major_release;
+	uint8_t embedded_controller_minor_release;
+} __attribute__((__packed__));
+
+/* SMBIOS type 1 - System Information */
+struct smbios_type_1 {
+	struct smbios_structure_header header;
+	uint8_t manufacturer_str;
+	uint8_t product_name_str;
+	uint8_t version_str;
+	uint8_t serial_number_str;
+	uint8_t uuid[16];
+	uint8_t wake_up_type;
+	uint8_t sku_number_str;
+	uint8_t family_str;
+} __attribute__((__packed__));
+
+/* SMBIOS type 3 - System Enclosure (v2.3) */
+struct smbios_type_3 {
+	struct smbios_structure_header header;
+	uint8_t manufacturer_str;
+	uint8_t type;
+	uint8_t version_str;
+	uint8_t serial_number_str;
+	uint8_t asset_tag_number_str;
+	uint8_t boot_up_state;
+	uint8_t power_supply_state;
+	uint8_t thermal_state;
+	uint8_t security_status;
+    uint32_t oem_defined;
+    uint8_t height;
+    uint8_t number_of_power_cords;
+    uint8_t contained_element_count;
+    // contained elements follow
+} __attribute__((__packed__));
+
+/* SMBIOS type 4 - Processor Information (v2.0) */
+struct smbios_type_4 {
+	struct smbios_structure_header header;
+	uint8_t socket_designation_str;
+	uint8_t processor_type;
+	uint8_t processor_family;
+	uint8_t processor_manufacturer_str;
+	uint32_t processor_id[2];
+	uint8_t processor_version_str;
+	uint8_t voltage;
+	uint16_t external_clock;
+	uint16_t max_speed;
+	uint16_t current_speed;
+	uint8_t status;
+	uint8_t processor_upgrade;
+} __attribute__((__packed__));
+
+/* SMBIOS type 16 - Physical Memory Array
+ *   Associated with one type 17 (Memory Device).
+ */
+struct smbios_type_16 {
+	struct smbios_structure_header header;
+	uint8_t location;
+	uint8_t use;
+	uint8_t error_correction;
+	uint32_t maximum_capacity;
+	uint16_t memory_error_information_handle;
+	uint16_t number_of_memory_devices;
+} __attribute__((__packed__));
+
+/* SMBIOS type 17 - Memory Device
+ *   Associated with one type 19
+ */
+struct smbios_type_17 {
+	struct smbios_structure_header header;
+	uint16_t physical_memory_array_handle;
+	uint16_t memory_error_information_handle;
+	uint16_t total_width;
+	uint16_t data_width;
+	uint16_t size;
+	uint8_t form_factor;
+	uint8_t device_set;
+	uint8_t device_locator_str;
+	uint8_t bank_locator_str;
+	uint8_t memory_type;
+	uint16_t type_detail;
+} __attribute__((__packed__));
+
+/* SMBIOS type 19 - Memory Array Mapped Address */
+struct smbios_type_19 {
+	struct smbios_structure_header header;
+	uint32_t starting_address;
+	uint32_t ending_address;
+	uint16_t memory_array_handle;
+	uint8_t partition_width;
+} __attribute__((__packed__));
+
+/* SMBIOS type 20 - Memory Device Mapped Address */
+struct smbios_type_20 {
+	struct smbios_structure_header header;
+	uint32_t starting_address;
+	uint32_t ending_address;
+	uint16_t memory_device_handle;
+	uint16_t memory_array_mapped_address_handle;
+	uint8_t partition_row_position;
+	uint8_t interleave_position;
+	uint8_t interleaved_data_depth;
+} __attribute__((__packed__));
+
+/* SMBIOS type 32 - System Boot Information */
+struct smbios_type_32 {
+	struct smbios_structure_header header;
+	uint8_t reserved[6];
+	uint8_t boot_status;
+} __attribute__((__packed__));
+
+/* SMBIOS type 127 -- End-of-table */
+struct smbios_type_127 {
+	struct smbios_structure_header header;
+} __attribute__((__packed__));
+
+static void
+smbios_entry_point_init(void *start,
+                        uint16_t max_structure_size,
+                        uint16_t structure_table_length,
+                        uint32_t structure_table_address,
+                        uint16_t number_of_structures)
+{
+    uint8_t sum;
+    int i;
+    struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
+
+    memcpy(ep->anchor_string, "_SM_", 4);
+    ep->length = 0x1f;
+    ep->smbios_major_version = 2;
+    ep->smbios_minor_version = 4;
+    ep->max_structure_size = max_structure_size;
+    ep->entry_point_revision = 0;
+    memset(ep->formatted_area, 0, 5);
+    memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
+
+    ep->structure_table_length = structure_table_length;
+    ep->structure_table_address = structure_table_address;
+    ep->number_of_structures = number_of_structures;
+    ep->smbios_bcd_revision = 0x24;
+
+    ep->checksum = 0;
+    ep->intermediate_checksum = 0;
+
+    sum = 0;
+    for (i = 0; i < 0x10; i++)
+        sum += ((int8_t *)start)[i];
+    ep->checksum = -sum;
+
+    sum = 0;
+    for (i = 0x10; i < ep->length; i++)
+        sum += ((int8_t *)start)[i];
+    ep->intermediate_checksum = -sum;
+    }
+
+/* Type 0 -- BIOS Information */
+#define RELEASE_DATE_STR "01/01/2007"
+static void *
+smbios_type_0_init(void *start)
+{
+    struct smbios_type_0 *p = (struct smbios_type_0 *)start;
+
+    p->header.type = 0;
+    p->header.length = sizeof(struct smbios_type_0);
+    p->header.handle = 0;
+
+    p->vendor_str = 1;
+    p->bios_version_str = 1;
+    p->bios_starting_address_segment = 0xe800;
+    p->bios_release_date_str = 2;
+    p->bios_rom_size = 0; /* FIXME */
+
+    memset(p->bios_characteristics, 0, 7);
+    p->bios_characteristics[7] = 0x08; /* BIOS characteristics not supported */
+    p->bios_characteristics_extension_bytes[0] = 0;
+    p->bios_characteristics_extension_bytes[1] = 0;
+
+    p->system_bios_major_release = 1;
+    p->system_bios_minor_release = 0;
+    p->embedded_controller_major_release = 0xff;
+    p->embedded_controller_minor_release = 0xff;
+
+    start += sizeof(struct smbios_type_0);
+    memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
+    start += sizeof(BX_APPNAME);
+    memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
+    start += sizeof(RELEASE_DATE_STR);
+    *((uint8_t *)start) = 0;
+
+    return start+1;
+}
+
+/* Type 1 -- System Information */
+static void *
+smbios_type_1_init(void *start)
+{
+    struct smbios_type_1 *p = (struct smbios_type_1 *)start;
+    p->header.type = 1;
+    p->header.length = sizeof(struct smbios_type_1);
+    p->header.handle = 0x100;
+
+    p->manufacturer_str = 0;
+    p->product_name_str = 0;
+    p->version_str = 0;
+    p->serial_number_str = 0;
+
+    memcpy(p->uuid, bios_uuid, 16);
+
+    p->wake_up_type = 0x06; /* power switch */
+    p->sku_number_str = 0;
+    p->family_str = 0;
+
+    start += sizeof(struct smbios_type_1);
+    *((uint16_t *)start) = 0;
+
+    return start+2;
+}
+
+/* Type 3 -- System Enclosure */
+static void *
+smbios_type_3_init(void *start)
+{
+    struct smbios_type_3 *p = (struct smbios_type_3 *)start;
+
+    p->header.type = 3;
+    p->header.length = sizeof(struct smbios_type_3);
+    p->header.handle = 0x300;
+
+    p->manufacturer_str = 0;
+    p->type = 0x01; /* other */
+    p->version_str = 0;
+    p->serial_number_str = 0;
+    p->asset_tag_number_str = 0;
+    p->boot_up_state = 0x03; /* safe */
+    p->power_supply_state = 0x03; /* safe */
+    p->thermal_state = 0x03; /* safe */
+    p->security_status = 0x02; /* unknown */
+    p->oem_defined = 0;
+    p->height = 0;
+    p->number_of_power_cords = 0;
+    p->contained_element_count = 0;
+
+    start += sizeof(struct smbios_type_3);
+    *((uint16_t *)start) = 0;
+
+    return start+2;
+}
+
+/* Type 4 -- Processor Information */
+static void *
+smbios_type_4_init(void *start, unsigned int cpu_number)
+{
+    struct smbios_type_4 *p = (struct smbios_type_4 *)start;
+
+    p->header.type = 4;
+    p->header.length = sizeof(struct smbios_type_4);
+    p->header.handle = 0x400 + cpu_number;
+
+    p->socket_designation_str = 1;
+    p->processor_type = 0x03; /* CPU */
+    p->processor_family = 0x01; /* other */
+    p->processor_manufacturer_str = 0;
+
+    p->processor_id[0] = cpuid_signature;
+    p->processor_id[1] = cpuid_features;
+
+    p->processor_version_str = 0;
+    p->voltage = 0;
+    p->external_clock = 0;
+
+    p->max_speed = 0; /* unknown */
+    p->current_speed = 0; /* unknown */
+
+    p->status = 0x41; /* socket populated, CPU enabled */
+    p->processor_upgrade = 0x01; /* other */
+
+    start += sizeof(struct smbios_type_4);
+
+    memcpy((char *)start, "CPU  " "\0" "" "\0" "", 7);
+	((char *)start)[4] = cpu_number + '0';
+
+    return start+7;
+}
+
+/* Type 16 -- Physical Memory Array */
+static void *
+smbios_type_16_init(void *start, uint32_t memsize)
+{
+    struct smbios_type_16 *p = (struct smbios_type_16*)start;
+
+    p->header.type = 16;
+    p->header.length = sizeof(struct smbios_type_16);
+    p->header.handle = 0x1000;
+
+    p->location = 0x01; /* other */
+    p->use = 0x03; /* system memory */
+    p->error_correction = 0x01; /* other */
+    p->maximum_capacity = memsize * 1024;
+    p->memory_error_information_handle = 0xfffe; /* none provided */
+    p->number_of_memory_devices = 1;
+
+    start += sizeof(struct smbios_type_16);
+    *((uint16_t *)start) = 0;
+
+    return start + 2;
+}
+
+/* Type 17 -- Memory Device */
+static void *
+smbios_type_17_init(void *start, uint32_t memory_size_mb)
+{
+    struct smbios_type_17 *p = (struct smbios_type_17 *)start;
+
+    p->header.type = 17;
+    p->header.length = sizeof(struct smbios_type_17);
+    p->header.handle = 0x1100;
+
+    p->physical_memory_array_handle = 0x1000;
+    p->total_width = 64;
+    p->data_width = 64;
+    /* truncate memory_size_mb to 16 bits and clear most significant
+       bit [indicates size in MB] */
+    p->size = (uint16_t) memory_size_mb & 0x7fff;
+    p->form_factor = 0x09; /* DIMM */
+    p->device_set = 0;
+    p->device_locator_str = 1;
+    p->bank_locator_str = 0;
+    p->memory_type = 0x07; /* RAM */
+    p->type_detail = 0;
+
+    start += sizeof(struct smbios_type_17);
+    memcpy((char *)start, "DIMM 1", 7);
+    start += 7;
+    *((uint8_t *)start) = 0;
+
+    return start+1;
+}
+
+/* Type 19 -- Memory Array Mapped Address */
+static void *
+smbios_type_19_init(void *start, uint32_t memory_size_mb)
+{
+    struct smbios_type_19 *p = (struct smbios_type_19 *)start;
+
+    p->header.type = 19;
+    p->header.length = sizeof(struct smbios_type_19);
+    p->header.handle = 0x1300;
+
+    p->starting_address = 0;
+    p->ending_address = (memory_size_mb-1) * 1024;
+    p->memory_array_handle = 0x1000;
+    p->partition_width = 1;
+
+    start += sizeof(struct smbios_type_19);
+    *((uint16_t *)start) = 0;
+
+    return start + 2;
+}
+
+/* Type 20 -- Memory Device Mapped Address */
+static void *
+smbios_type_20_init(void *start, uint32_t memory_size_mb)
+{
+    struct smbios_type_20 *p = (struct smbios_type_20 *)start;
+
+    p->header.type = 20;
+    p->header.length = sizeof(struct smbios_type_20);
+    p->header.handle = 0x1400;
+
+    p->starting_address = 0;
+    p->ending_address = (memory_size_mb-1)*1024;
+    p->memory_device_handle = 0x1100;
+    p->memory_array_mapped_address_handle = 0x1300;
+    p->partition_row_position = 1;
+    p->interleave_position = 0;
+    p->interleaved_data_depth = 0;
+
+    start += sizeof(struct smbios_type_20);
+
+    *((uint16_t *)start) = 0;
+    return start+2;
+}
+
+/* Type 32 -- System Boot Information */
+static void *
+smbios_type_32_init(void *start)
+{
+    struct smbios_type_32 *p = (struct smbios_type_32 *)start;
+
+    p->header.type = 32;
+    p->header.length = sizeof(struct smbios_type_32);
+    p->header.handle = 0x2000;
+    memset(p->reserved, 0, 6);
+    p->boot_status = 0; /* no errors detected */
+
+    start += sizeof(struct smbios_type_32);
+    *((uint16_t *)start) = 0;
+
+    return start+2;
+}
+
+/* Type 127 -- End of Table */
+static void *
+smbios_type_127_init(void *start)
+{
+    struct smbios_type_127 *p = (struct smbios_type_127 *)start;
+
+    p->header.type = 127;
+    p->header.length = sizeof(struct smbios_type_127);
+    p->header.handle = 0x7f00;
+
+    start += sizeof(struct smbios_type_127);
+    *((uint16_t *)start) = 0;
+
+    return start + 2;
+}
+
+void smbios_init(void)
+{
+    unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
+    char *start, *p, *q;
+    int memsize = ram_size / (1024 * 1024);
+
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr = align(ebda_cur_addr, 16);
+    start = (void *)(ebda_cur_addr);
+#else
+    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    start = (void *)(bios_table_cur_addr);
+#endif
+
+	p = (char *)start + sizeof(struct smbios_entry_point);
+
+#define add_struct(fn) { \
+    q = (fn); \
+    nr_structs++; \
+    if ((q - p) > max_struct_size) \
+        max_struct_size = q - p; \
+    p = q; \
+}
+
+    add_struct(smbios_type_0_init(p));
+    add_struct(smbios_type_1_init(p));
+    add_struct(smbios_type_3_init(p));
+    for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
+        add_struct(smbios_type_4_init(p, cpu_num));
+    add_struct(smbios_type_16_init(p, memsize));
+    add_struct(smbios_type_17_init(p, memsize));
+    add_struct(smbios_type_19_init(p, memsize));
+    add_struct(smbios_type_20_init(p, memsize));
+    add_struct(smbios_type_32_init(p));
+    add_struct(smbios_type_127_init(p));
+
+#undef add_struct
+
+    smbios_entry_point_init(
+        start, max_struct_size,
+        (p - (char *)start) - sizeof(struct smbios_entry_point),
+        (uint32_t)(start + sizeof(struct smbios_entry_point)),
+        nr_structs);
+
+#ifdef BX_USE_EBDA_TABLES
+    ebda_cur_addr += (p - (char *)start);
+#else
+    bios_table_cur_addr += (p - (char *)start);
+#endif
+
+    BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
+}
+
+void rombios32_init(void)
+{
+    BX_INFO("Starting rombios32\n");
+
+    ram_probe();
+
+    cpu_probe();
+
+    smp_probe();
+
+    uuid_probe();
+
+    pci_bios_init();
+
+    if (bios_table_cur_addr != 0) {
+
+        mptable_init();
+
+        smbios_init();
+
+        if (acpi_enabled)
+            acpi_bios_init();
+
+        bios_lock_shadow_ram();
+
+        BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
+        if (bios_table_cur_addr > bios_table_end_addr)
+            BX_PANIC("bios_table_end_addr overflow!\n");
+    }
+}
diff --git a/src/rombios32.lds.S b/src/rombios32.lds.S
index 78546cf..bb17cf0 100644
--- a/src/rombios32.lds.S
+++ b/src/rombios32.lds.S
@@ -18,8 +18,9 @@
         _text32_start = . ;
         .text     : { *(.text)    }
         .rodata    : { *(.rodata) }
-        . = ALIGN(16);
         .data     : { *(.data)    }
+        // XXX - should change code so it doesn't require global variables.
+        . = 0x00040000;
         __bss_start = . ;
         .bss      : { *(.bss) *(COMMON) }
         _end = . ;
diff --git a/src/system.c b/src/system.c
index f4b13f8..70f9bcd 100644
--- a/src/system.c
+++ b/src/system.c
@@ -84,18 +84,6 @@
     handle_ret(regs, 0);
 }
 
-// Sleep for n microseconds. currently using the
-// refresh request port 0x61 bit4, toggling every 15usec
-static void
-usleep(u32 count)
-{
-    count = count / 15;
-    u8 kbd = inb(PORT_PS2_CTRLB);
-    while (count)
-        if ((inb(PORT_PS2_CTRLB) ^ kbd) & KBD_REFRESH)
-            count--;
-}
-
 // Wait for CX:DX microseconds. currently using the
 // refresh request port 0x61 bit4, toggling every 15usec
 static void
diff --git a/src/types.h b/src/types.h
index 3bd76c5..b1bf2ef 100644
--- a/src/types.h
+++ b/src/types.h
@@ -32,4 +32,9 @@
 
 #define PACKED __attribute__((packed))
 
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+#define __stringify_1(x)        #x
+#define __stringify(x)          __stringify_1(x)
+
 #endif // types.h
diff --git a/src/util.c b/src/util.c
new file mode 100644
index 0000000..b9d641f
--- /dev/null
+++ b/src/util.c
@@ -0,0 +1,13 @@
+#include "util.h" // usleep
+
+// Sleep for n microseconds. currently using the
+// refresh request port 0x61 bit4, toggling every 15usec
+void
+usleep(u32 count)
+{
+    count = count / 15;
+    u8 kbd = inb(PORT_PS2_CTRLB);
+    while (count)
+        if ((inb(PORT_PS2_CTRLB) ^ kbd) & KBD_REFRESH)
+            count--;
+}
diff --git a/src/util.h b/src/util.h
index 2b35721..82d3b6c 100644
--- a/src/util.h
+++ b/src/util.h
@@ -52,6 +52,18 @@
         ((char *)s)[--n] = c;
 }
 
+static inline void *
+memcpy(void *d1, const void *s1, size_t len)
+{
+    u8 *d = d1;
+    const u8 *s = s1;
+
+    while (len--) {
+        *d++ = *s++;
+    }
+    return d1;
+}
+
 static inline void
 eoi_master_pic()
 {
@@ -138,4 +150,10 @@
     set_cf(regs, code);
 }
 
+// util.c
+void usleep(u32 count);
+
+// rombios32.c
+void rombios32_init(void);
+
 #endif // util.h