fix low bits in ROM and I/O sizing
This cleans up handling of low bits during BAR sizing,
to match PCI spec requirements, and to use symbolic
constants from pci_regs.h
For ROM BARs, bit 0 is writeable (enable bit), which we not
only don't want to set, but it will stick and make us think
it's an I/O port resource.
Further, PCI spec defines the following bits as reserved:
- bit 1 in I/O BAR
- bits 10:1 in ROM BAR
and we should be careful and preserve any values there,
and should ignore anything we read from these registers.
Bits 3:2 in I/O BAR might be writeable, so it
is wrong to mask them when calculating BAR size.
See 220.127.116.11 for I/O and memory, and 18.104.22.168 for ROM,
6.1 for reserved bit handling;
pages 225, 228 and 214 in PCI spec revision 3.0.
See also Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806
Signed-off-by: Gleb Natapov <email@example.com>
Signed-off-by: Michael S. Tsirkin <firstname.lastname@example.org>
1 file changed