Move acpi code out of rombios32.c; clean up use of fixed memory addresses.

Move acpi code from rombios32.c to acpi.c.
Move all fixed memory addresses used by the code to config.h and
    consistently use a "BUILD_" prefix on the definitions.
Move some pci defs to pci.h - allows access from acpi.c and rombios32.c.
Introduce ALIGN() macro - remove old align function.
diff --git a/Makefile b/Makefile
index ccf0385..1392108 100644
--- a/Makefile
+++ b/Makefile
@@ -10,7 +10,8 @@
 # Source files
 SRCBOTH=output.c util.c floppy.c ata.c kbd.c pci.c boot.c serial.c clock.c
 SRC16=$(SRCBOTH) disk.c system.c mouse.c cdrom.c apm.c pcibios.c
-SRC32=$(SRCBOTH) post.c shadow.c rombios32.c post_menu.c memmap.c coreboot.c
+SRC32=$(SRCBOTH) post.c shadow.c rombios32.c post_menu.c memmap.c coreboot.c \
+      acpi.c
 TABLESRC=font.c cbt.c floppy_dbt.c
 
 cc-option = $(shell if test -z "`$(1) $(2) -S -o /dev/null -xc \
diff --git a/src/acpi.c b/src/acpi.c
new file mode 100644
index 0000000..a47be64
--- /dev/null
+++ b/src/acpi.c
@@ -0,0 +1,429 @@
+// Support for enabling/disabling BIOS ram shadowing.
+//
+// Copyright (C) 2008  Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2006 Fabrice Bellard
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "acpi.h" // struct rsdp_descriptor
+#include "util.h" // memcpy
+#include "memmap.h" // bios_table_cur_addr
+#include "pci.h" // pci_find_device
+
+
+/****************************************************/
+/* ACPI tables init */
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+   BSD license) */
+
+#define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
+	u8                            signature [4];          /* ACPI signature (4 ASCII characters) */\
+	u32                             length;                 /* Length of table, in bytes, including header */\
+	u8                              revision;               /* ACPI Specification minor version # */\
+	u8                              checksum;               /* To make sum of entire table == 0 */\
+	u8                            oem_id [6];             /* OEM identification */\
+	u8                            oem_table_id [8];       /* OEM table identification */\
+	u32                             oem_revision;           /* OEM revision number */\
+	u8                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
+	u32                             asl_compiler_revision;  /* ASL compiler revision number */
+
+
+struct acpi_table_header         /* ACPI common table header */
+{
+	ACPI_TABLE_HEADER_DEF
+};
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+struct rsdt_descriptor_rev1
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	u32                             table_offset_entry [3]; /* Array of pointers to other */
+			 /* ACPI tables */
+};
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+struct facs_descriptor_rev1
+{
+	u8                            signature[4];           /* ACPI Signature */
+	u32                             length;                 /* Length of structure, in bytes */
+	u32                             hardware_signature;     /* Hardware configuration signature */
+	u32                             firmware_waking_vector; /* ACPI OS waking vector */
+	u32                             global_lock;            /* Global Lock */
+	u32                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
+	u32                             reserved1       : 31;   /* Must be 0 */
+	u8                              resverved3 [40];        /* Reserved - must be zero */
+};
+
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+struct fadt_descriptor_rev1
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	u32                             firmware_ctrl;          /* Physical address of FACS */
+	u32                             dsdt;                   /* Physical address of DSDT */
+	u8                              model;                  /* System Interrupt Model */
+	u8                              reserved1;              /* Reserved */
+	u16                             sci_int;                /* System vector of SCI interrupt */
+	u32                             smi_cmd;                /* Port address of SMI command port */
+	u8                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+	u8                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
+	u8                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
+	u8                              reserved2;              /* Reserved - must be zero */
+	u32                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
+	u32                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
+	u32                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
+	u32                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
+	u32                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
+	u32                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
+	u32                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
+	u32                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
+	u8                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
+	u8                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
+	u8                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
+	u8                              pm_tmr_len;              /* Byte Length of ports at pm_tm_blk */
+	u8                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
+	u8                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
+	u8                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
+	u8                              reserved3;              /* Reserved */
+	u16                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+	u16                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
+	u16                             flush_size;             /* Size of area read to flush caches */
+	u16                             flush_stride;           /* Stride used in flushing caches */
+	u8                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+	u8                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+	u8                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+	u8                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+	u8                              century;                /* Index to century in RTC CMOS RAM */
+	u8                              reserved4;              /* Reserved */
+	u8                              reserved4a;             /* Reserved */
+	u8                              reserved4b;             /* Reserved */
+#if 0
+	u32                             wb_invd         : 1;    /* The wbinvd instruction works properly */
+	u32                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
+	u32                             proc_c1         : 1;    /* All processors support C1 state */
+	u32                             plvl2_up        : 1;    /* C2 state works on MP system */
+	u32                             pwr_button      : 1;    /* Power button is handled as a generic feature */
+	u32                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
+	u32                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
+	u32                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
+	u32                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
+	u32                             reserved5       : 23;   /* Reserved - must be zero */
+#else
+        u32 flags;
+#endif
+};
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define DUAL_PIC                0
+#define MULTIPLE_APIC           1
+
+
+/* Master MADT */
+
+struct multiple_apic_table
+{
+	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+	u32                             local_apic_address;     /* Physical address of local APIC */
+#if 0
+	u32                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
+	u32                             reserved1       : 31;
+#else
+        u32                             flags;
+#endif
+};
+
+
+/* Values for Type in APIC_HEADER_DEF */
+
+#define APIC_PROCESSOR          0
+#define APIC_IO                 1
+#define APIC_XRUPT_OVERRIDE     2
+#define APIC_NMI                3
+#define APIC_LOCAL_NMI          4
+#define APIC_ADDRESS_OVERRIDE   5
+#define APIC_IO_SAPIC           6
+#define APIC_LOCAL_SAPIC        7
+#define APIC_XRUPT_SOURCE       8
+#define APIC_RESERVED           9           /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define APIC_HEADER_DEF                     /* Common APIC sub-structure header */\
+	u8                              type; \
+	u8                              length;
+
+/* Sub-structures for MADT */
+
+struct madt_processor_apic
+{
+	APIC_HEADER_DEF
+	u8                              processor_id;           /* ACPI processor id */
+	u8                              local_apic_id;          /* Processor's local APIC id */
+#if 0
+	u32                             processor_enabled: 1;   /* Processor is usable if set */
+	u32                             reserved2       : 31;   /* Reserved, must be zero */
+#else
+        u32 flags;
+#endif
+};
+
+struct madt_io_apic
+{
+	APIC_HEADER_DEF
+	u8                              io_apic_id;             /* I/O APIC ID */
+	u8                              reserved;               /* Reserved - must be zero */
+	u32                             address;                /* APIC physical address */
+	u32                             interrupt;              /* Global system interrupt where INTI
+			  * lines start */
+};
+
+#include "acpi-dsdt.hex"
+
+static inline u16 cpu_to_le16(u16 x)
+{
+    return x;
+}
+
+static inline u32 cpu_to_le32(u32 x)
+{
+    return x;
+}
+
+static void acpi_build_table_header(struct acpi_table_header *h,
+                                    char *sig, int len, u8 rev)
+{
+    memcpy(h->signature, sig, 4);
+    h->length = cpu_to_le32(len);
+    h->revision = rev;
+#if (CONFIG_QEMU == 1)
+    memcpy(h->oem_id, "QEMU  ", 6);
+    memcpy(h->oem_table_id, "QEMU", 4);
+#else
+    memcpy(h->oem_id, "BOCHS ", 6);
+    memcpy(h->oem_table_id, "BXPC", 4);
+#endif
+    memcpy(h->oem_table_id + 4, sig, 4);
+    h->oem_revision = cpu_to_le32(1);
+#if (CONFIG_QEMU == 1)
+    memcpy(h->asl_compiler_id, "QEMU", 4);
+#else
+    memcpy(h->asl_compiler_id, "BXPC", 4);
+#endif
+    h->asl_compiler_revision = cpu_to_le32(1);
+    h->checksum = -checksum((void *)h, len);
+}
+
+static int
+acpi_build_processor_ssdt(u8 *ssdt)
+{
+    u8 *ssdt_ptr = ssdt;
+    int i, length;
+    int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
+
+    ssdt_ptr[9] = 0; // checksum;
+    ssdt_ptr += sizeof(struct acpi_table_header);
+
+    // caluculate the length of processor block and scope block excluding PkgLength
+    length = 0x0d * acpi_cpus + 4;
+
+    // build processor scope header
+    *(ssdt_ptr++) = 0x10; // ScopeOp
+    if (length <= 0x3e) {
+        *(ssdt_ptr++) = length + 1;
+    } else {
+        *(ssdt_ptr++) = 0x7F;
+        *(ssdt_ptr++) = (length + 2) >> 6;
+    }
+    *(ssdt_ptr++) = '_'; // Name
+    *(ssdt_ptr++) = 'P';
+    *(ssdt_ptr++) = 'R';
+    *(ssdt_ptr++) = '_';
+
+    // build object for each processor
+    for(i=0;i<acpi_cpus;i++) {
+        *(ssdt_ptr++) = 0x5B; // ProcessorOp
+        *(ssdt_ptr++) = 0x83;
+        *(ssdt_ptr++) = 0x0B; // Length
+        *(ssdt_ptr++) = 'C';  // Name (CPUxx)
+        *(ssdt_ptr++) = 'P';
+        if ((i & 0xf0) != 0)
+            *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
+        else
+            *(ssdt_ptr++) = 'U';
+        *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
+        *(ssdt_ptr++) = i;
+        *(ssdt_ptr++) = 0x10; // Processor block address
+        *(ssdt_ptr++) = 0xb0;
+        *(ssdt_ptr++) = 0;
+        *(ssdt_ptr++) = 0;
+        *(ssdt_ptr++) = 6;    // Processor block length
+    }
+
+    acpi_build_table_header((struct acpi_table_header *)ssdt,
+                            "SSDT", ssdt_ptr - ssdt, 1);
+
+    return ssdt_ptr - ssdt;
+}
+
+/* base_addr must be a multiple of 4KB */
+void acpi_bios_init(void)
+{
+    // This code is hardcoded for PIIX4 Power Management device.
+    PCIDevice d;
+    int ret = pci_find_device(0x8086, 0x7113, 0, &d);
+    if (ret)
+        // Device not found
+        return;
+
+    struct rsdp_descriptor *rsdp;
+    struct rsdt_descriptor_rev1 *rsdt;
+    struct fadt_descriptor_rev1 *fadt;
+    struct facs_descriptor_rev1 *facs;
+    struct multiple_apic_table *madt;
+    u8 *dsdt, *ssdt;
+    u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
+    u32 acpi_tables_size, madt_addr, madt_size;
+    int i;
+
+    /* reserve memory space for tables */
+#if (CONFIG_USE_EBDA_TABLES == 1)
+    ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
+    rsdp = (void *)(ebda_cur_addr);
+    ebda_cur_addr += sizeof(*rsdp);
+#else
+    bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
+    rsdp = (void *)(bios_table_cur_addr);
+    bios_table_cur_addr += sizeof(*rsdp);
+#endif
+
+    addr = base_addr = GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE;
+    add_e820(addr, CONFIG_ACPI_DATA_SIZE, E820_ACPI);
+    rsdt_addr = addr;
+    rsdt = (void *)(addr);
+    addr += sizeof(*rsdt);
+
+    fadt_addr = addr;
+    fadt = (void *)(addr);
+    addr += sizeof(*fadt);
+
+    /* XXX: FACS should be in RAM */
+    addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
+    facs_addr = addr;
+    facs = (void *)(addr);
+    addr += sizeof(*facs);
+
+    dsdt_addr = addr;
+    dsdt = (void *)(addr);
+    addr += sizeof(AmlCode);
+
+    ssdt_addr = addr;
+    ssdt = (void *)(addr);
+    addr += acpi_build_processor_ssdt(ssdt);
+
+    addr = (addr + 7) & ~7;
+    madt_addr = addr;
+    madt_size = sizeof(*madt) +
+        sizeof(struct madt_processor_apic) * smp_cpus +
+        sizeof(struct madt_io_apic);
+    madt = (void *)(addr);
+    addr += madt_size;
+
+    acpi_tables_size = addr - base_addr;
+
+    dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
+            " ACPI DATA addr=0x%08lx size=0x%x\n",
+            (unsigned long)rsdp,
+            (unsigned long)rsdt, acpi_tables_size);
+
+    /* RSDP */
+    memset(rsdp, 0, sizeof(*rsdp));
+    memcpy(rsdp->signature, "RSD PTR ", 8);
+#if (CONFIG_QEMU == 1)
+    memcpy(rsdp->oem_id, "QEMU  ", 6);
+#else
+    memcpy(rsdp->oem_id, "BOCHS ", 6);
+#endif
+    rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
+    rsdp->checksum = -checksum((void *)rsdp, 20);
+
+    /* RSDT */
+    memset(rsdt, 0, sizeof(*rsdt));
+    rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
+    rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
+    rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
+    acpi_build_table_header((struct acpi_table_header *)rsdt,
+                            "RSDT", sizeof(*rsdt), 1);
+
+    /* FADT */
+    memset(fadt, 0, sizeof(*fadt));
+    fadt->firmware_ctrl = cpu_to_le32(facs_addr);
+    fadt->dsdt = cpu_to_le32(dsdt_addr);
+    fadt->model = 1;
+    fadt->reserved1 = 0;
+    int pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
+    fadt->sci_int = cpu_to_le16(pm_sci_int);
+    fadt->smi_cmd = cpu_to_le32(BUILD_SMI_CMD_IO_ADDR);
+    fadt->acpi_enable = 0xf1;
+    fadt->acpi_disable = 0xf0;
+    fadt->pm1a_evt_blk = cpu_to_le32(BUILD_PM_IO_BASE);
+    fadt->pm1a_cnt_blk = cpu_to_le32(BUILD_PM_IO_BASE + 0x04);
+    fadt->pm_tmr_blk = cpu_to_le32(BUILD_PM_IO_BASE + 0x08);
+    fadt->pm1_evt_len = 4;
+    fadt->pm1_cnt_len = 2;
+    fadt->pm_tmr_len = 4;
+    fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
+    fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
+    /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
+    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
+    acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
+                            sizeof(*fadt), 1);
+
+    /* FACS */
+    memset(facs, 0, sizeof(*facs));
+    memcpy(facs->signature, "FACS", 4);
+    facs->length = cpu_to_le32(sizeof(*facs));
+
+    /* DSDT */
+    memcpy(dsdt, AmlCode, sizeof(AmlCode));
+
+    /* MADT */
+    {
+        struct madt_processor_apic *apic;
+        struct madt_io_apic *io_apic;
+
+        memset(madt, 0, madt_size);
+        madt->local_apic_address = cpu_to_le32(0xfee00000);
+        madt->flags = cpu_to_le32(1);
+        apic = (void *)(madt + 1);
+        for(i=0;i<smp_cpus;i++) {
+            apic->type = APIC_PROCESSOR;
+            apic->length = sizeof(*apic);
+            apic->processor_id = i;
+            apic->local_apic_id = i;
+            apic->flags = cpu_to_le32(1);
+            apic++;
+        }
+        io_apic = (void *)apic;
+        io_apic->type = APIC_IO;
+        io_apic->length = sizeof(*io_apic);
+        io_apic->io_apic_id = smp_cpus;
+        io_apic->address = cpu_to_le32(0xfec00000);
+        io_apic->interrupt = cpu_to_le32(0);
+
+        acpi_build_table_header((struct acpi_table_header *)madt,
+                                "APIC", madt_size, 1);
+    }
+}
diff --git a/src/acpi.h b/src/acpi.h
new file mode 100644
index 0000000..ab1f75d
--- /dev/null
+++ b/src/acpi.h
@@ -0,0 +1,24 @@
+#ifndef __ACPI_H
+#define __ACPI_H
+
+#include "types.h" // u32
+
+void acpi_bios_init(void);
+
+// XXX - move to better header.
+extern int smp_cpus;
+
+struct rsdp_descriptor         /* Root System Descriptor Pointer */
+{
+	u8                            signature [8];          /* ACPI signature, contains "RSD PTR " */
+	u8                              checksum;               /* To make sum of struct == 0 */
+	u8                            oem_id [6];             /* OEM identification */
+	u8                              revision;               /* Must be 0 for 1.0, 2 for 2.0 */
+	u32                             rsdt_physical_address;  /* 32-bit physical address of RSDT */
+	u32                             length;                 /* XSDT Length in bytes including hdr */
+	u64                             xsdt_physical_address;  /* 64-bit physical address of XSDT */
+	u8                              extended_checksum;      /* Checksum of entire table */
+	u8                            reserved [3];           /* Reserved field must be 0 */
+};
+
+#endif // acpi.h
diff --git a/src/config.h b/src/config.h
index 8ddce6b..de26919 100644
--- a/src/config.h
+++ b/src/config.h
@@ -46,16 +46,25 @@
 #define CONFIG_MAX_ATA_INTERFACES 4
 #define CONFIG_MAX_ATA_DEVICES  (CONFIG_MAX_ATA_INTERFACES*2)
 
-#define CONFIG_STACK_SEGMENT 0x00
-#define CONFIG_STACK_OFFSET  0xfffe
-
 #define CONFIG_ACPI_DATA_SIZE 0x00010000L
 
 #define CONFIG_MODEL_ID      0xFC
 #define CONFIG_SUBMODEL_ID   0x00
 #define CONFIG_BIOS_REVISION 0x01
 
+// Various memory addresses used by the code.
+#define BUILD_STACK_ADDR        0xfffe
+#define BUILD_CPU_COUNT_ADDR    0xf000
+#define BUILD_AP_BOOT_ADDR      0x10000
+#define BUILD_BSS_ADDR          0x40000
+ /* 64 KB used to copy the BIOS to shadow RAM */
+#define BUILD_BIOS_TMP_ADDR     0x30000
+
+#define BUILD_PM_IO_BASE        0xb000
+#define BUILD_SMB_IO_BASE       0xb100
+#define BUILD_SMI_CMD_IO_ADDR   0xb2
+
 // Start of fixed addresses in 0xf0000 segment.
-#define CONFIG_START_FIXED 0xe050
+#define BUILD_START_FIXED       0xe050
 
 #endif // config.h
diff --git a/src/pci.h b/src/pci.h
index edf94b1..7dc038e 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -27,6 +27,22 @@
 
 
 /****************************************************************
+ * PCI definitions
+ ****************************************************************/
+
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_DEVICE_ID		0x02	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define PCI_CLASS_DEVICE        0x0a    /* Device class */
+#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
+#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
+#define PCI_MIN_GNT		0x3e	/* 8 bits */
+#define PCI_MAX_LAT		0x3f	/* 8 bits */
+
+
+/****************************************************************
  * PIR table
  ****************************************************************/
 
diff --git a/src/post.c b/src/post.c
index 4593b69..afbd360 100644
--- a/src/post.c
+++ b/src/post.c
@@ -347,6 +347,6 @@
     "cld\n"
     "lidtl " __stringify(0xf0000 | OFFSET_pmode_IDT_info) "\n"
     "lgdtl " __stringify(0xf0000 | OFFSET_rombios32_gdt_48) "\n"
-    "movl $" __stringify(CONFIG_STACK_OFFSET) ", %esp\n"
+    "movl $" __stringify(BUILD_STACK_ADDR) ", %esp\n"
     "ljmp $0x10, $_start\n"
     );
diff --git a/src/rombios16.lds.S b/src/rombios16.lds.S
index f699816..32ac884 100644
--- a/src/rombios16.lds.S
+++ b/src/rombios16.lds.S
@@ -19,7 +19,7 @@
                 *(.rodata.*)
                 *(.data)
                 bios16c_end = .;
-                . = CONFIG_START_FIXED;
+                . = BUILD_START_FIXED;
                 *(.text.fixed.addr)
                 }
 
diff --git a/src/rombios32.c b/src/rombios32.c
index 1bf554a..a56539d 100644
--- a/src/rombios32.c
+++ b/src/rombios32.c
@@ -22,14 +22,7 @@
 #include "types.h" // u32
 #include "config.h" // CONFIG_*
 #include "memmap.h" // bios_table_cur_addr
-
-// Memory addresses used by this code.  (Note global variables (bss)
-// are at 0x40000).
-#define CPU_COUNT_ADDR    0xf000
-#define AP_BOOT_ADDR      0x10000
-
-#define PM_IO_BASE        0xb000
-#define SMB_IO_BASE       0xb100
+#include "acpi.h" // acpi_bios_init
 
 #define cpuid(index, eax, ebx, ecx, edx) \
   asm volatile ("cpuid" \
@@ -47,7 +40,6 @@
 #define APIC_ENABLED 0x0100
 
 #define MPTABLE_MAX_SIZE  0x00002000
-#define SMI_CMD_IO_ADDR   0xb2
 
 static inline void writel(void *addr, u32 val)
 {
@@ -87,9 +79,6 @@
 #if (CONFIG_USE_EBDA_TABLES == 1)
 unsigned long ebda_cur_addr;
 #endif
-int acpi_enabled;
-u32 pm_io_base, smb_io_base;
-int pm_sci_int;
 
 void uuid_probe(void)
 {
@@ -146,19 +135,19 @@
         val |= APIC_ENABLED;
         writel(APIC_BASE + APIC_SVR, val);
 
-        writew((void *)CPU_COUNT_ADDR, 1);
+        writew((void *)BUILD_CPU_COUNT_ADDR, 1);
         /* copy AP boot code */
-        memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
+        memcpy((void *)BUILD_AP_BOOT_ADDR, &smp_ap_boot_code_start,
                &smp_ap_boot_code_end - &smp_ap_boot_code_start);
 
         /* broadcast SIPI */
         writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
-        sipi_vector = AP_BOOT_ADDR >> 12;
+        sipi_vector = BUILD_AP_BOOT_ADDR >> 12;
         writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
 
         usleep(10*1000);
 
-        smp_cpus = readw((void *)CPU_COUNT_ADDR);
+        smp_cpus = readw((void *)BUILD_CPU_COUNT_ADDR);
     }
     dprintf(1, "Found %d cpu(s)\n", smp_cpus);
 }
@@ -175,17 +164,6 @@
 
 #define PCI_DEVICES_MAX 64
 
-#define PCI_VENDOR_ID		0x00	/* 16 bits */
-#define PCI_DEVICE_ID		0x02	/* 16 bits */
-#define PCI_COMMAND		0x04	/* 16 bits */
-#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
-#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
-#define PCI_CLASS_DEVICE        0x0a    /* Device class */
-#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
-#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
-#define PCI_MIN_GNT		0x3e	/* 8 bits */
-#define PCI_MAX_LAT		0x3f	/* 8 bits */
-
 static u32 pci_bios_io_addr;
 static u32 pci_bios_mem_addr;
 static u32 pci_bios_bigmem_addr;
@@ -274,7 +252,7 @@
     "smp_ap_boot_code_start:\n"
     "  xor %ax, %ax\n"
     "  mov %ax, %ds\n"
-    "  incw " __stringify(CPU_COUNT_ADDR) "\n"
+    "  incw " __stringify(BUILD_CPU_COUNT_ADDR) "\n"
     "1:\n"
     "  hlt\n"
     "  jmp 1b\n"
@@ -308,7 +286,7 @@
     "  jne 1f\n"
 
     /* ACPI disable */
-    "  mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+    "  mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
     "  inw %dx, %ax\n"
     "  andw $~1, %ax\n"
     "  outw %ax, %dx\n"
@@ -320,7 +298,7 @@
     "  jne 2f\n"
 
     /* ACPI enable */
-    "  mov $" __stringify(PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
+    "  mov $" __stringify(BUILD_PM_IO_BASE) " + 0x04, %dx\n" /* PMCNTRL */
     "  inw %dx, %ax\n"
     "  orw $1, %ax\n"
     "  outw %ax, %dx\n"
@@ -462,17 +440,15 @@
 
     if (vendor_id == 0x8086 && device_id == 0x7113) {
         /* PIIX4 Power Management device (for ACPI) */
-        pm_io_base = PM_IO_BASE;
+        u32 pm_io_base = BUILD_PM_IO_BASE;
         pci_config_writel(d, 0x40, pm_io_base | 1);
         pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
-        smb_io_base = SMB_IO_BASE;
+        u32 smb_io_base = BUILD_SMB_IO_BASE;
         pci_config_writel(d, 0x90, smb_io_base | 1);
         pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
-        pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
 #if (CONFIG_USE_SMM == 1)
         smm_init(d);
 #endif
-        acpi_enabled = 1;
     }
 }
 
@@ -546,11 +522,6 @@
     *pp = q;
 }
 
-static unsigned long align(unsigned long addr, unsigned long v)
-{
-    return (addr + v - 1) & ~(v - 1);
-}
-
 static void mptable_init(void)
 {
     u8 *mp_config_table, *q, *float_pointer_struct;
@@ -566,7 +537,7 @@
     mp_config_table = (u8 *)(GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE
                              - MPTABLE_MAX_SIZE);
 #else
-    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
     mp_config_table = (u8 *)bios_table_cur_addr;
 #endif
     q = mp_config_table;
@@ -648,10 +619,10 @@
 
     /* floating pointer structure */
 #if (CONFIG_USE_EBDA_TABLES == 1)
-    ebda_cur_addr = align(ebda_cur_addr, 16);
+    ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
     float_pointer_struct = (u8 *)ebda_cur_addr;
 #else
-    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
     float_pointer_struct = (u8 *)bios_table_cur_addr;
 #endif
     q = float_pointer_struct;
@@ -681,427 +652,6 @@
             mp_config_table_size);
 }
 
-/****************************************************/
-/* ACPI tables init */
-
-/* Table structure from Linux kernel (the ACPI tables are under the
-   BSD license) */
-
-#define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
-	u8                            signature [4];          /* ACPI signature (4 ASCII characters) */\
-	u32                             length;                 /* Length of table, in bytes, including header */\
-	u8                              revision;               /* ACPI Specification minor version # */\
-	u8                              checksum;               /* To make sum of entire table == 0 */\
-	u8                            oem_id [6];             /* OEM identification */\
-	u8                            oem_table_id [8];       /* OEM table identification */\
-	u32                             oem_revision;           /* OEM revision number */\
-	u8                            asl_compiler_id [4];    /* ASL compiler vendor ID */\
-	u32                             asl_compiler_revision;  /* ASL compiler revision number */
-
-
-struct acpi_table_header         /* ACPI common table header */
-{
-	ACPI_TABLE_HEADER_DEF
-};
-
-struct rsdp_descriptor         /* Root System Descriptor Pointer */
-{
-	u8                            signature [8];          /* ACPI signature, contains "RSD PTR " */
-	u8                              checksum;               /* To make sum of struct == 0 */
-	u8                            oem_id [6];             /* OEM identification */
-	u8                              revision;               /* Must be 0 for 1.0, 2 for 2.0 */
-	u32                             rsdt_physical_address;  /* 32-bit physical address of RSDT */
-	u32                             length;                 /* XSDT Length in bytes including hdr */
-	u64                             xsdt_physical_address;  /* 64-bit physical address of XSDT */
-	u8                              extended_checksum;      /* Checksum of entire table */
-	u8                            reserved [3];           /* Reserved field must be 0 */
-};
-
-/*
- * ACPI 1.0 Root System Description Table (RSDT)
- */
-struct rsdt_descriptor_rev1
-{
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             table_offset_entry [3]; /* Array of pointers to other */
-			 /* ACPI tables */
-};
-
-/*
- * ACPI 1.0 Firmware ACPI Control Structure (FACS)
- */
-struct facs_descriptor_rev1
-{
-	u8                            signature[4];           /* ACPI Signature */
-	u32                             length;                 /* Length of structure, in bytes */
-	u32                             hardware_signature;     /* Hardware configuration signature */
-	u32                             firmware_waking_vector; /* ACPI OS waking vector */
-	u32                             global_lock;            /* Global Lock */
-	u32                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
-	u32                             reserved1       : 31;   /* Must be 0 */
-	u8                              resverved3 [40];        /* Reserved - must be zero */
-};
-
-
-/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
- */
-struct fadt_descriptor_rev1
-{
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             firmware_ctrl;          /* Physical address of FACS */
-	u32                             dsdt;                   /* Physical address of DSDT */
-	u8                              model;                  /* System Interrupt Model */
-	u8                              reserved1;              /* Reserved */
-	u16                             sci_int;                /* System vector of SCI interrupt */
-	u32                             smi_cmd;                /* Port address of SMI command port */
-	u8                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
-	u8                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
-	u8                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
-	u8                              reserved2;              /* Reserved - must be zero */
-	u32                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
-	u32                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
-	u32                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
-	u32                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
-	u32                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
-	u32                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
-	u32                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
-	u32                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
-	u8                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
-	u8                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
-	u8                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
-	u8                              pm_tmr_len;              /* Byte Length of ports at pm_tm_blk */
-	u8                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
-	u8                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
-	u8                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
-	u8                              reserved3;              /* Reserved */
-	u16                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
-	u16                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
-	u16                             flush_size;             /* Size of area read to flush caches */
-	u16                             flush_stride;           /* Stride used in flushing caches */
-	u8                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
-	u8                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
-	u8                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
-	u8                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
-	u8                              century;                /* Index to century in RTC CMOS RAM */
-	u8                              reserved4;              /* Reserved */
-	u8                              reserved4a;             /* Reserved */
-	u8                              reserved4b;             /* Reserved */
-#if 0
-	u32                             wb_invd         : 1;    /* The wbinvd instruction works properly */
-	u32                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
-	u32                             proc_c1         : 1;    /* All processors support C1 state */
-	u32                             plvl2_up        : 1;    /* C2 state works on MP system */
-	u32                             pwr_button      : 1;    /* Power button is handled as a generic feature */
-	u32                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
-	u32                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
-	u32                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
-	u32                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
-	u32                             reserved5       : 23;   /* Reserved - must be zero */
-#else
-        u32 flags;
-#endif
-};
-
-/*
- * MADT values and structures
- */
-
-/* Values for MADT PCATCompat */
-
-#define DUAL_PIC                0
-#define MULTIPLE_APIC           1
-
-
-/* Master MADT */
-
-struct multiple_apic_table
-{
-	ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
-	u32                             local_apic_address;     /* Physical address of local APIC */
-#if 0
-	u32                             PCATcompat      : 1;    /* A one indicates system also has dual 8259s */
-	u32                             reserved1       : 31;
-#else
-        u32                             flags;
-#endif
-};
-
-
-/* Values for Type in APIC_HEADER_DEF */
-
-#define APIC_PROCESSOR          0
-#define APIC_IO                 1
-#define APIC_XRUPT_OVERRIDE     2
-#define APIC_NMI                3
-#define APIC_LOCAL_NMI          4
-#define APIC_ADDRESS_OVERRIDE   5
-#define APIC_IO_SAPIC           6
-#define APIC_LOCAL_SAPIC        7
-#define APIC_XRUPT_SOURCE       8
-#define APIC_RESERVED           9           /* 9 and greater are reserved */
-
-/*
- * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
- */
-#define APIC_HEADER_DEF                     /* Common APIC sub-structure header */\
-	u8                              type; \
-	u8                              length;
-
-/* Sub-structures for MADT */
-
-struct madt_processor_apic
-{
-	APIC_HEADER_DEF
-	u8                              processor_id;           /* ACPI processor id */
-	u8                              local_apic_id;          /* Processor's local APIC id */
-#if 0
-	u32                             processor_enabled: 1;   /* Processor is usable if set */
-	u32                             reserved2       : 31;   /* Reserved, must be zero */
-#else
-        u32 flags;
-#endif
-};
-
-struct madt_io_apic
-{
-	APIC_HEADER_DEF
-	u8                              io_apic_id;             /* I/O APIC ID */
-	u8                              reserved;               /* Reserved - must be zero */
-	u32                             address;                /* APIC physical address */
-	u32                             interrupt;              /* Global system interrupt where INTI
-			  * lines start */
-};
-
-#include "acpi-dsdt.hex"
-
-static inline u16 cpu_to_le16(u16 x)
-{
-    return x;
-}
-
-static inline u32 cpu_to_le32(u32 x)
-{
-    return x;
-}
-
-static void acpi_build_table_header(struct acpi_table_header *h,
-                                    char *sig, int len, u8 rev)
-{
-    memcpy(h->signature, sig, 4);
-    h->length = cpu_to_le32(len);
-    h->revision = rev;
-#if (CONFIG_QEMU == 1)
-    memcpy(h->oem_id, "QEMU  ", 6);
-    memcpy(h->oem_table_id, "QEMU", 4);
-#else
-    memcpy(h->oem_id, "BOCHS ", 6);
-    memcpy(h->oem_table_id, "BXPC", 4);
-#endif
-    memcpy(h->oem_table_id + 4, sig, 4);
-    h->oem_revision = cpu_to_le32(1);
-#if (CONFIG_QEMU == 1)
-    memcpy(h->asl_compiler_id, "QEMU", 4);
-#else
-    memcpy(h->asl_compiler_id, "BXPC", 4);
-#endif
-    h->asl_compiler_revision = cpu_to_le32(1);
-    h->checksum = -checksum((void *)h, len);
-}
-
-int acpi_build_processor_ssdt(u8 *ssdt)
-{
-    u8 *ssdt_ptr = ssdt;
-    int i, length;
-    int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
-
-    ssdt_ptr[9] = 0; // checksum;
-    ssdt_ptr += sizeof(struct acpi_table_header);
-
-    // caluculate the length of processor block and scope block excluding PkgLength
-    length = 0x0d * acpi_cpus + 4;
-
-    // build processor scope header
-    *(ssdt_ptr++) = 0x10; // ScopeOp
-    if (length <= 0x3e) {
-        *(ssdt_ptr++) = length + 1;
-    } else {
-        *(ssdt_ptr++) = 0x7F;
-        *(ssdt_ptr++) = (length + 2) >> 6;
-    }
-    *(ssdt_ptr++) = '_'; // Name
-    *(ssdt_ptr++) = 'P';
-    *(ssdt_ptr++) = 'R';
-    *(ssdt_ptr++) = '_';
-
-    // build object for each processor
-    for(i=0;i<acpi_cpus;i++) {
-        *(ssdt_ptr++) = 0x5B; // ProcessorOp
-        *(ssdt_ptr++) = 0x83;
-        *(ssdt_ptr++) = 0x0B; // Length
-        *(ssdt_ptr++) = 'C';  // Name (CPUxx)
-        *(ssdt_ptr++) = 'P';
-        if ((i & 0xf0) != 0)
-            *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
-        else
-            *(ssdt_ptr++) = 'U';
-        *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
-        *(ssdt_ptr++) = i;
-        *(ssdt_ptr++) = 0x10; // Processor block address
-        *(ssdt_ptr++) = 0xb0;
-        *(ssdt_ptr++) = 0;
-        *(ssdt_ptr++) = 0;
-        *(ssdt_ptr++) = 6;    // Processor block length
-    }
-
-    acpi_build_table_header((struct acpi_table_header *)ssdt,
-                            "SSDT", ssdt_ptr - ssdt, 1);
-
-    return ssdt_ptr - ssdt;
-}
-
-/* base_addr must be a multiple of 4KB */
-void acpi_bios_init(void)
-{
-    struct rsdp_descriptor *rsdp;
-    struct rsdt_descriptor_rev1 *rsdt;
-    struct fadt_descriptor_rev1 *fadt;
-    struct facs_descriptor_rev1 *facs;
-    struct multiple_apic_table *madt;
-    u8 *dsdt, *ssdt;
-    u32 base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
-    u32 acpi_tables_size, madt_addr, madt_size;
-    int i;
-
-    /* reserve memory space for tables */
-#if (CONFIG_USE_EBDA_TABLES == 1)
-    ebda_cur_addr = align(ebda_cur_addr, 16);
-    rsdp = (void *)(ebda_cur_addr);
-    ebda_cur_addr += sizeof(*rsdp);
-#else
-    bios_table_cur_addr = align(bios_table_cur_addr, 16);
-    rsdp = (void *)(bios_table_cur_addr);
-    bios_table_cur_addr += sizeof(*rsdp);
-#endif
-
-    addr = base_addr = GET_EBDA(ram_size) - CONFIG_ACPI_DATA_SIZE;
-    add_e820(addr, CONFIG_ACPI_DATA_SIZE, E820_ACPI);
-    rsdt_addr = addr;
-    rsdt = (void *)(addr);
-    addr += sizeof(*rsdt);
-
-    fadt_addr = addr;
-    fadt = (void *)(addr);
-    addr += sizeof(*fadt);
-
-    /* XXX: FACS should be in RAM */
-    addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
-    facs_addr = addr;
-    facs = (void *)(addr);
-    addr += sizeof(*facs);
-
-    dsdt_addr = addr;
-    dsdt = (void *)(addr);
-    addr += sizeof(AmlCode);
-
-    ssdt_addr = addr;
-    ssdt = (void *)(addr);
-    addr += acpi_build_processor_ssdt(ssdt);
-
-    addr = (addr + 7) & ~7;
-    madt_addr = addr;
-    madt_size = sizeof(*madt) +
-        sizeof(struct madt_processor_apic) * smp_cpus +
-        sizeof(struct madt_io_apic);
-    madt = (void *)(addr);
-    addr += madt_size;
-
-    acpi_tables_size = addr - base_addr;
-
-    dprintf(1, "ACPI tables: RSDP addr=0x%08lx"
-            " ACPI DATA addr=0x%08lx size=0x%x\n",
-            (unsigned long)rsdp,
-            (unsigned long)rsdt, acpi_tables_size);
-
-    /* RSDP */
-    memset(rsdp, 0, sizeof(*rsdp));
-    memcpy(rsdp->signature, "RSD PTR ", 8);
-#if (CONFIG_QEMU == 1)
-    memcpy(rsdp->oem_id, "QEMU  ", 6);
-#else
-    memcpy(rsdp->oem_id, "BOCHS ", 6);
-#endif
-    rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
-    rsdp->checksum = -checksum((void *)rsdp, 20);
-
-    /* RSDT */
-    memset(rsdt, 0, sizeof(*rsdt));
-    rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
-    rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
-    rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
-    acpi_build_table_header((struct acpi_table_header *)rsdt,
-                            "RSDT", sizeof(*rsdt), 1);
-
-    /* FADT */
-    memset(fadt, 0, sizeof(*fadt));
-    fadt->firmware_ctrl = cpu_to_le32(facs_addr);
-    fadt->dsdt = cpu_to_le32(dsdt_addr);
-    fadt->model = 1;
-    fadt->reserved1 = 0;
-    fadt->sci_int = cpu_to_le16(pm_sci_int);
-    fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
-    fadt->acpi_enable = 0xf1;
-    fadt->acpi_disable = 0xf0;
-    fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
-    fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
-    fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
-    fadt->pm1_evt_len = 4;
-    fadt->pm1_cnt_len = 2;
-    fadt->pm_tmr_len = 4;
-    fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
-    fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
-    /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
-    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
-    acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
-                            sizeof(*fadt), 1);
-
-    /* FACS */
-    memset(facs, 0, sizeof(*facs));
-    memcpy(facs->signature, "FACS", 4);
-    facs->length = cpu_to_le32(sizeof(*facs));
-
-    /* DSDT */
-    memcpy(dsdt, AmlCode, sizeof(AmlCode));
-
-    /* MADT */
-    {
-        struct madt_processor_apic *apic;
-        struct madt_io_apic *io_apic;
-
-        memset(madt, 0, madt_size);
-        madt->local_apic_address = cpu_to_le32(0xfee00000);
-        madt->flags = cpu_to_le32(1);
-        apic = (void *)(madt + 1);
-        for(i=0;i<smp_cpus;i++) {
-            apic->type = APIC_PROCESSOR;
-            apic->length = sizeof(*apic);
-            apic->processor_id = i;
-            apic->local_apic_id = i;
-            apic->flags = cpu_to_le32(1);
-            apic++;
-        }
-        io_apic = (void *)apic;
-        io_apic->type = APIC_IO;
-        io_apic->length = sizeof(*io_apic);
-        io_apic->io_apic_id = smp_cpus;
-        io_apic->address = cpu_to_le32(0xfec00000);
-        io_apic->interrupt = cpu_to_le32(0);
-
-        acpi_build_table_header((struct acpi_table_header *)madt,
-                                "APIC", madt_size, 1);
-    }
-}
-
 /* SMBIOS entry point -- must be written to a 16-bit aligned address
    between 0xf0000 and 0xfffff.
  */
@@ -1558,10 +1108,10 @@
     int memsize = GET_EBDA(ram_size) / (1024 * 1024);
 
 #if (CONFIG_USE_EBDA_TABLES == 1)
-    ebda_cur_addr = align(ebda_cur_addr, 16);
+    ebda_cur_addr = ALIGN(ebda_cur_addr, 16);
     start = (void *)(ebda_cur_addr);
 #else
-    bios_table_cur_addr = align(bios_table_cur_addr, 16);
+    bios_table_cur_addr = ALIGN(bios_table_cur_addr, 16);
     start = (void *)(bios_table_cur_addr);
 #endif
 
@@ -1631,8 +1181,7 @@
 
         smbios_init();
 
-        if (acpi_enabled)
-            acpi_bios_init();
+        acpi_bios_init();
 
         dprintf(1, "bios_table_cur_addr: 0x%08x\n", bios_table_cur_addr);
         if (bios_table_cur_addr > bios_table_end_addr)
diff --git a/src/rombios32.lds.S b/src/rombios32.lds.S
index 532317e..312850a 100644
--- a/src/rombios32.lds.S
+++ b/src/rombios32.lds.S
@@ -19,8 +19,7 @@
         .text     : { *(.text)    }
         .rodata   : { *(.rodata)  }
         .data     : { *(.data)    }
-        // XXX - should change code so it doesn't require global variables.
-        . = 0x00040000;
+        . = BUILD_BSS_ADDR;
         __bss_start = . ;
         .bss      : { *(.bss) *(COMMON) }
         __bss_end = . ;
diff --git a/src/romlayout.S b/src/romlayout.S
index b20ee90..c852261 100644
--- a/src/romlayout.S
+++ b/src/romlayout.S
@@ -109,13 +109,13 @@
         .macro RESET_STACK
         xorw %ax, %ax
         movw %ax, %ss
-        movl $ CONFIG_STACK_OFFSET , %esp
+        movl $ BUILD_STACK_ADDR , %esp
         .endm
 
         // Specify a location in the fixed part of bios area.
         .macro ORG addr
         .section .text.fixed.addr
-        .org \addr - CONFIG_START_FIXED
+        .org \addr - BUILD_START_FIXED
         .endm
 
 
diff --git a/src/shadow.c b/src/shadow.c
index 6500029..887851d 100644
--- a/src/shadow.c
+++ b/src/shadow.c
@@ -8,8 +8,6 @@
 #include "util.h" // memcpy
 #include "pci.h" // pci_config_writeb
 
-#define BIOS_TMP_STORAGE  0x30000 /* 64 KB used to copy the BIOS to shadow RAM */
-
 // Test if 'addr' is in the range from 'start'..'start+size'
 #define IN_RANGE(addr, start, size) ({   \
             u32 __addr = (addr);         \
@@ -25,7 +23,7 @@
     int v = pci_config_readb(d, 0x59);
     v |= 0x30;
     pci_config_writeb(d, 0x59, v);
-    memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
+    memcpy((void *)0x000f0000, (void *)BUILD_BIOS_TMP_ADDR, 0x10000);
 }
 
 // Make the BIOS code segment area (0xf0000) writable.
@@ -46,14 +44,14 @@
     }
 
     // Copy the bios to a temporary area.
-    memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
+    memcpy((void *)BUILD_BIOS_TMP_ADDR, (void *)0x000f0000, 0x10000);
 
     // Enable shadowing and copy bios.
     if (IN_RANGE((u32)copy_bios, 0xf0000, 0x10000)) {
         // Jump to shadow enable function - use the copy in the
         // temporary storage area so that memory does not change under
         // the executing code.
-        u32 pos = (u32)copy_bios - 0xf0000 + BIOS_TMP_STORAGE;
+        u32 pos = (u32)copy_bios - 0xf0000 + BUILD_BIOS_TMP_ADDR;
         void (*func)(PCIDevice) = (void*)pos;
         func(d);
     } else {
@@ -61,7 +59,7 @@
     }
 
     // Clear the temporary area.
-    memset((void *)BIOS_TMP_STORAGE, 0, 0x10000);
+    memset((void *)BUILD_BIOS_TMP_ADDR, 0, 0x10000);
 }
 
 // Make the BIOS code segment area (0xf0000) read-only.
diff --git a/src/types.h b/src/types.h
index 0f25df8..81b6739 100644
--- a/src/types.h
+++ b/src/types.h
@@ -36,6 +36,8 @@
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 
 #define NULL ((void *)0)