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Martin Roth9b1b3352016-02-24 12:27:06 -08001#ifndef __ASM_MSR_H
2#define __ASM_MSR_H
3
4/*
5 * Access to machine-specific registers (available on 586 and better only)
6 * Note: the rd* operations modify the parameters directly (without using
7 * pointer indirection), this allows gcc to optimize better
8 */
Martin Roth4dcd13d2016-02-24 13:53:07 -08009
10#define __FIXUP_ALIGN ".align 8"
Martin Roth9b1b3352016-02-24 12:27:06 -080011#define __FIXUP_WORD ".quad"
12#define EFAULT 14 /* Bad address */
13
14#define rdmsr(msr,val1,val2) \
15 __asm__ __volatile__("rdmsr" \
16 : "=a" (val1), "=d" (val2) \
17 : "c" (msr) : "edi")
18
19/*
20#define rdmsr_safe(msr,val1,val2) ({\
21 int _rc; \
22 __asm__ __volatile__( \
23 "1: rdmsr\n2:\n" \
24 ".section .fixup,\"ax\"\n" \
25 "3: movl %5,%2\n; jmp 2b\n" \
26 ".previous\n" \
27 ".section __ex_table,\"a\"\n" \
28 " "__FIXUP_ALIGN"\n" \
29 ".previous\n" \
30 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
31 : "c" (msr), "2" (0), "i" (-EFAULT)); \
Martin Roth4dcd13d2016-02-24 13:53:07 -080032 _rc; })
Martin Roth9b1b3352016-02-24 12:27:06 -080033*/
34
35#define wrmsr(msr,val1,val2) \
36 __asm__ __volatile__("wrmsr" \
37 : /* no outputs */ \
38 : "c" (msr), "a" (val1), "d" (val2))
39
40#define rdtsc(low,high) \
41 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
42
43#define rdtscl(low) \
44 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
45
46#define rdtscll(val) \
47 __asm__ __volatile__("rdtsc" : "=A" (val))
48
49#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
50
51#define rdpmc(counter,low,high) \
52 __asm__ __volatile__("rdpmc" \
53 : "=a" (low), "=d" (high) \
54 : "c" (counter))
55
56/* symbolic names for some interesting MSRs */
57/* Intel defined MSRs. */
58#define MSR_IA32_P5_MC_ADDR 0
59#define MSR_IA32_P5_MC_TYPE 1
60#define MSR_IA32_PLATFORM_ID 0x17
61#define MSR_IA32_EBL_CR_POWERON 0x2a
62
63#define MSR_IA32_APICBASE 0x1b
64#define MSR_IA32_APICBASE_BSP (1<<8)
65#define MSR_IA32_APICBASE_ENABLE (1<<11)
66#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
67
68#define MSR_IA32_UCODE_WRITE 0x79
69#define MSR_IA32_UCODE_REV 0x8b
70
71#define MSR_IA32_BBL_CR_CTL 0x119
72
73#define MSR_IA32_MCG_CAP 0x179
74#define MSR_IA32_MCG_STATUS 0x17a
75#define MSR_IA32_MCG_CTL 0x17b
76
77#define MSR_IA32_THERM_CONTROL 0x19a
78#define MSR_IA32_THERM_INTERRUPT 0x19b
79#define MSR_IA32_THERM_STATUS 0x19c
80#define MSR_IA32_MISC_ENABLE 0x1a0
81#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
82
83#define MSR_IA32_DEBUGCTLMSR 0x1d9
84#define MSR_IA32_LASTBRANCHFROMIP 0x1db
85#define MSR_IA32_LASTBRANCHTOIP 0x1dc
86#define MSR_IA32_LASTINTFROMIP 0x1dd
87#define MSR_IA32_LASTINTTOIP 0x1de
88
89#define MSR_IA32_MC0_CTL 0x400
90#define MSR_IA32_MC0_STATUS 0x401
91#define MSR_IA32_MC0_ADDR 0x402
92#define MSR_IA32_MC0_MISC 0x403
93
94#define MSR_P6_PERFCTR0 0xc1
95#define MSR_P6_PERFCTR1 0xc2
96#define MSR_P6_EVNTSEL0 0x186
97#define MSR_P6_EVNTSEL1 0x187
98
99#define MSR_IA32_PERF_STATUS 0x198
100#define MSR_IA32_PERF_CTL 0x199
101
102/* AMD Defined MSRs */
103#define MSR_K6_EFER 0xC0000080
104#define MSR_K6_STAR 0xC0000081
105#define MSR_K6_WHCR 0xC0000082
106#define MSR_K6_UWCCR 0xC0000085
107#define MSR_K6_EPMR 0xC0000086
108#define MSR_K6_PSOR 0xC0000087
109#define MSR_K6_PFIR 0xC0000088
110
111#define MSR_K7_EVNTSEL0 0xC0010000
112#define MSR_K7_PERFCTR0 0xC0010004
113#define MSR_K7_HWCR 0xC0010015
114#define MSR_K7_CLK_CTL 0xC001001b
115#define MSR_K7_FID_VID_CTL 0xC0010041
116#define MSR_K7_VID_STATUS 0xC0010042
117
118/* Centaur-Hauls/IDT defined MSRs. */
119#define MSR_IDT_FCR1 0x107
120#define MSR_IDT_FCR2 0x108
121#define MSR_IDT_FCR3 0x109
122#define MSR_IDT_FCR4 0x10a
123
124#define MSR_IDT_MCR0 0x110
125#define MSR_IDT_MCR1 0x111
126#define MSR_IDT_MCR2 0x112
127#define MSR_IDT_MCR3 0x113
128#define MSR_IDT_MCR4 0x114
129#define MSR_IDT_MCR5 0x115
130#define MSR_IDT_MCR6 0x116
131#define MSR_IDT_MCR7 0x117
132#define MSR_IDT_MCR_CTRL 0x120
133
134/* VIA Cyrix defined MSRs*/
135#define MSR_VIA_FCR 0x1107
136#define MSR_VIA_LONGHAUL 0x110a
137#define MSR_VIA_BCR2 0x1147
138
139/* Transmeta defined MSRs */
140#define MSR_TMTA_LONGRUN_CTRL 0x80868010
141#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
142#define MSR_TMTA_LRTI_READOUT 0x80868018
143#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
144
145#endif /* __ASM_MSR_H */