blob: f837da9b7716b10dbb0eddf5d417ec4a88f7acab [file] [log] [blame]
Martin Roth9b1b3352016-02-24 12:27:06 -08001// This is the extra stuff added to the memtest+ from memtest.org
2// Code from Eric Nelson and Wee
3// (Checked without vendor-specific optimization before adding)
4/* extra.c -
5 *
6 * Released under version 2 of the Gnu Public License.
7 *
8 */
9
10#include "test.h"
11#include "screen_buffer.h"
12#include "pci.h"
13#include "extra.h"
14
15static int ctrl = -1;
16
17struct memory_controller {
18 unsigned vendor;
19 unsigned device;
Ben Gardner90f7d112016-03-15 15:25:22 -050020 int worked;
21 void (*change_timing)(int cas, int rcd, int rp, int ras);
Martin Roth9b1b3352016-02-24 12:27:06 -080022};
23
24static struct memory_controller mem_ctr[] = {
Martin Roth9b1b3352016-02-24 12:27:06 -080025 /* AMD 64*/
Ben Gardner90f7d112016-03-15 15:25:22 -050026 { 0x1022, 0x1100, 1, change_timing_amd64 }, //AMD64 hypertransport link
Martin Roth9b1b3352016-02-24 12:27:06 -080027
28 /* nVidia */
Ben Gardner90f7d112016-03-15 15:25:22 -050029 { 0x10de, 0x01E0, 0, change_timing_nf2 }, // nforce2
Martin Roth9b1b3352016-02-24 12:27:06 -080030
31 /* Intel */
Ben Gardner90f7d112016-03-15 15:25:22 -050032 { 0x8086, 0x2570, 0, change_timing_i875 }, //Intel i848/i865
33 { 0x8086, 0x2578, 0, change_timing_i875 }, //Intel i875P
34 { 0x8086, 0x2580, 0, change_timing_i925 }, //Intel i915P/G
35 { 0x8086, 0x2584, 0, change_timing_i925 }, //Intel i925X
36 { 0x8086, 0x2770, 0, change_timing_i925 }, //Intel Lakeport
37 { 0x8086, 0x3580, 0, change_timing_i852 }, //Intel i852GM - i855GM/GME (But not i855PM)
Martin Roth9b1b3352016-02-24 12:27:06 -080038};
39
40struct drc {
41 unsigned t_rwt;
42 unsigned t_wrt;
43 unsigned t_ref;
44 unsigned t_en2t;
45 unsigned t_rwqb;
46 unsigned t_rct;
47 unsigned t_rrd;
48 unsigned t_wr;
49};
50
51static struct drc a64;
52
53void find_memctr(void) // Basically copy from the find_controller function
54{
55 unsigned long vendor;
56 unsigned long device;
57 unsigned long a64;
58 int i= 0;
59 int result;
60
61 result = pci_conf_read(0, 0, 0, PCI_VENDOR_ID, 2, &vendor);
62 result = pci_conf_read(0, 0, 0, PCI_DEVICE_ID, 2, &device);
63
64 pci_conf_read(0, 24, 0, 0x00, 4, &a64);
65
Ben Gardner90f7d112016-03-15 15:25:22 -050066 if (a64 == 0x11001022) {
Martin Roth9b1b3352016-02-24 12:27:06 -080067 ctrl = 0;
68 return;
69 }
70
71 if (result == 0) {
Ben Gardner90f7d112016-03-15 15:25:22 -050072 for (i = 1; i < sizeof(mem_ctr)/sizeof(mem_ctr[0]); i++) {
Martin Roth9b1b3352016-02-24 12:27:06 -080073 if ((mem_ctr[i].vendor == vendor) &&
Ben Gardner90f7d112016-03-15 15:25:22 -050074 (mem_ctr[i].device == device)) {
Martin Roth9b1b3352016-02-24 12:27:06 -080075 ctrl = i;
76 return;
77 }
78 }
79 }
80 ctrl = -1;
81}
82
83void a64_parameter(void)
84{
Martin Roth9b1b3352016-02-24 12:27:06 -080085 ulong dramtlr;
86
Ben Gardner90f7d112016-03-15 15:25:22 -050087 if (0 == pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr) ) {
Martin Roth9b1b3352016-02-24 12:27:06 -080088 a64.t_rct = 7 + ((dramtlr>>4) & 0x0F);
89 a64.t_rrd = 0 + ((dramtlr>>16) & 0x7);
90 a64.t_wr = 2 + ((dramtlr>>28) & 0x1);
91 }
92
Ben Gardner90f7d112016-03-15 15:25:22 -050093 if (0 == pci_conf_read(0, 24, 2, 0x8C, 4, &dramtlr) ) {
Martin Roth9b1b3352016-02-24 12:27:06 -080094 a64.t_rwt = 1 + ((dramtlr>>4) & 0x07);
95 a64.t_wrt = 1 + (dramtlr & 0x1);
96 a64.t_ref = 1 + ((dramtlr>>11) & 0x3);
97 }
98
Ben Gardner90f7d112016-03-15 15:25:22 -050099 if (0 == pci_conf_read(0, 24, 2, 0x90, 4, &dramtlr) ) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800100 a64.t_en2t = 1 + ((dramtlr>>28) & 0x1);
101 a64.t_rwqb = 2 << ((dramtlr>>14) & 0x3);
102 }
103}
104
105
106
107void change_timing(int cas, int rcd, int rp, int ras)
108{
109 find_memctr();
Ben Gardner90f7d112016-03-15 15:25:22 -0500110 if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0]))) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800111 return;
112 }
113
114 mem_ctr[ctrl].change_timing(cas, rcd, rp, ras);
115 restart();
116}
117
118void amd64_option()
119{
120 int rwt=0, wrt=0, ref=0, en2t=0, rct=0, rrd=0, rwqb=0, wr = 0, flag=0;
121
Ben Gardner90f7d112016-03-15 15:25:22 -0500122 if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0]))) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800123 return;
124 }
125
Ben Gardner90f7d112016-03-15 15:25:22 -0500126 if (mem_ctr[ctrl].worked) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800127 a64_parameter();
128 cprint(POP_Y+1, POP_X+4, "AMD64 options");
129
130 cprint(POP_Y+3, POP_X+4, "(1) Rd-Wr Delay : ");
131 dprint(POP_Y+3, POP_X+24, a64.t_rwt, 2, 0);
132
133 cprint(POP_Y+4, POP_X+4, "(2) Wr-Rd Delay : ");
134 dprint(POP_Y+4, POP_X+24, a64.t_wrt, 2, 0);
135
136 cprint(POP_Y+5, POP_X+4, "(3) Rd/Wr Bypass : ");
137 dprint(POP_Y+5, POP_X+24, a64.t_rwqb, 2, 0);
138
139 cprint(POP_Y+6, POP_X+4, "(4) Refresh Rate : ");
Ben Gardner90f7d112016-03-15 15:25:22 -0500140 switch (a64.t_ref) {
141 case 1: cprint(POP_Y+6, POP_X+23, "15.6us"); break;
142 case 2: cprint(POP_Y+6, POP_X+23, " 7.8us"); break;
143 case 3: cprint(POP_Y+6, POP_X+23, " 3.9us"); break;
Martin Roth9b1b3352016-02-24 12:27:06 -0800144 }
145 cprint(POP_Y+7, POP_X+4, "(5) Command Rate :");
146 dprint(POP_Y+7, POP_X+24, a64.t_en2t, 2, 0);
147 cprint(POP_Y+7, POP_X+26, "T ");
148
149 cprint(POP_Y+8, POP_X+4, "(6) Row Cycle Time: ");
150 dprint(POP_Y+8, POP_X+24, a64.t_rct, 2, 0);
151
152 cprint(POP_Y+9, POP_X+4, "(7) RAS-RAS Delay : ");
153 dprint(POP_Y+9, POP_X+24, a64.t_rrd, 2, 0);
154
155 cprint(POP_Y+10, POP_X+4, "(8) Write Recovery: ");
156 dprint(POP_Y+10, POP_X+24, a64.t_wr, 2, 0);
157
Ben Gardner90f7d112016-03-15 15:25:22 -0500158 cprint(POP_Y+11, POP_X+4, "(0) Cancel ");
Martin Roth9b1b3352016-02-24 12:27:06 -0800159
Ben Gardner90f7d112016-03-15 15:25:22 -0500160 while (!flag)
Martin Roth9b1b3352016-02-24 12:27:06 -0800161 {
Ben Gardner90f7d112016-03-15 15:25:22 -0500162 switch (get_key()) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800163 case 2:
164 popclear();
165 // read-to-write delay
166 cprint(POP_Y+3, POP_X+4, "Rd-Wr delay ");
167 cprint(POP_Y+4, POP_X+4, " (2 - 6 cycles)");
168 cprint(POP_Y+5, POP_X+4, "Current: ");
169 dprint(POP_Y+5, POP_X+14, a64.t_rwt, 4, 0);
170 cprint(POP_Y+7, POP_X+4, "New: ");
171 rwt = getval(POP_Y+7, POP_X+12, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500172 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800173 break;
174
175 case 3:
176 popclear();
177 // read-to-write delay
178 cprint(POP_Y+3, POP_X+4, "Wr-Rd delay ");
179 cprint(POP_Y+4, POP_X+4, " (1 - 2 cycles)");
180 cprint(POP_Y+5, POP_X+4, "Current: ");
181 dprint(POP_Y+5, POP_X+14, a64.t_wrt, 4, 0);
182 cprint(POP_Y+7, POP_X+4, "New: ");
183 wrt = getval(POP_Y+7, POP_X+12, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500184 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800185 break;
186
187 case 4:
188 popclear();
189 // Read write queue bypass count
190 cprint(POP_Y+3, POP_X+4, "Rd/Wr bypass ");
191 cprint(POP_Y+4, POP_X+4, " (2, 4 or 8 )");
192 cprint(POP_Y+5, POP_X+4, "Current: ");
193 dprint(POP_Y+5, POP_X+14, a64.t_rwqb, 2, 0);
194 cprint(POP_Y+7, POP_X+4, "New: ");
195 rwqb = getval(POP_Y+7, POP_X+11, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500196 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800197 break;
198
199 case 5:
200 popclear();
201 // refresh rate
202 cprint(POP_Y+3, POP_X+4, "Refresh rate ");
203 cprint(POP_Y+4, POP_X+4, "Current: ");
Ben Gardner90f7d112016-03-15 15:25:22 -0500204 switch (a64.t_ref) {
205 case 1: cprint(POP_Y+4, POP_X+14, "15.6us"); break;
206 case 2: cprint(POP_Y+4, POP_X+14, "7.8us "); break;
207 case 3: cprint(POP_Y+4, POP_X+14, "3.9us "); break;
Martin Roth9b1b3352016-02-24 12:27:06 -0800208 }
209 cprint(POP_Y+6, POP_X+4, "New: ");
210 cprint(POP_Y+7, POP_X+4, "(1) 15.6us");
211 cprint(POP_Y+8, POP_X+4, "(2) 7.8us ");
212 cprint(POP_Y+9, POP_X+4, "(3) 3.9us ");
213 ref = getval(POP_Y+6, POP_X+11, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500214 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800215 break;
216
217 case 6:
218 popclear();
219 //Enable 2T command and addressing
220 cprint(POP_Y+3, POP_X+4, "Command rate:");
221 cprint(POP_Y+5, POP_X+4, "(1) 1T "); //only supoprted by CG revision and later
222 cprint(POP_Y+6, POP_X+4, "(2) 2T ");
223 en2t = getval(POP_Y+3, POP_X+22, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500224 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800225 break;
226
227 case 7:
228 popclear();
229 //Row cycle time
230 cprint(POP_Y+3, POP_X+4, "Row cycle time: ");
231 cprint(POP_Y+4, POP_X+4, " (7 - 20 cycles)");
232 cprint(POP_Y+5, POP_X+4, "Current: ");
233 dprint(POP_Y+5, POP_X+14, a64.t_rct, 4, 0);
234 cprint(POP_Y+7, POP_X+4, "New: ");
235 rct = getval(POP_Y+7, POP_X+12, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500236 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800237 break;
238
239 case 8:
240 popclear();
241 //Active-to-Active RAS Delay
242 cprint(POP_Y+3, POP_X+4, "RAS-RAS Delay: ");
243 cprint(POP_Y+4, POP_X+4, " (2 - 4 cycles)");
244 cprint(POP_Y+5, POP_X+4, "Current: ");
245 dprint(POP_Y+5, POP_X+14, a64.t_rrd, 2, 0);
246 cprint(POP_Y+7, POP_X+4, "New: ");
247 rrd = getval(POP_Y+7, POP_X+12, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500248 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800249 break;
250
251 case 9:
252 popclear();
253 //Active-to-Active RAS Delay
254 cprint(POP_Y+3, POP_X+4, "Write Recovery: ");
255 cprint(POP_Y+4, POP_X+4, " (2 - 3 cycles)");
256 cprint(POP_Y+5, POP_X+4, "Current: ");
257 dprint(POP_Y+5, POP_X+14, a64.t_wr, 2, 0);
258 cprint(POP_Y+7, POP_X+4, "New: ");
259 wr = getval(POP_Y+7, POP_X+12, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500260 amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
Martin Roth9b1b3352016-02-24 12:27:06 -0800261 break;
262
263 case 11:
264 case 57:
265 flag++;
266 /* 0/CR - Cancel */
267 break;
268 }
269 }
270 }
271}
272
273void get_option()
274{
Ben Gardner90f7d112016-03-15 15:25:22 -0500275 int cas =0, rp=0, rcd=0, ras=0, sflag = 0;
Martin Roth9b1b3352016-02-24 12:27:06 -0800276
Ben Gardner90f7d112016-03-15 15:25:22 -0500277 while (!sflag)
Martin Roth9b1b3352016-02-24 12:27:06 -0800278 {
Ben Gardner90f7d112016-03-15 15:25:22 -0500279 switch (get_key()) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800280 case 2:
281 popclear();
282 cas = get_cas();
283 popclear();
284
285 cprint(POP_Y+3, POP_X+8, "tRCD: ");
286 rcd = getval(POP_Y+3, POP_X+15, 0);
287 popclear();
288
289 cprint(POP_Y+3, POP_X+8, "tRP: ");
290 rp = getval(POP_Y+3, POP_X+15, 0);
291 popclear();
292
293 cprint(POP_Y+3, POP_X+8, "tRAS: ");
294 ras = getval(POP_Y+3, POP_X+15, 0);
295 popclear();
296 change_timing(cas, rcd, rp, ras);
297 break;
298
299 case 3:
300 popclear();
301 cas = get_cas();
302 change_timing(cas, 0, 0, 0);
303 sflag++;
304 break;
305
306 case 4:
307 popclear();
308 cprint(POP_Y+3, POP_X+8, "tRCD: ");
309 rcd =getval(POP_Y+3, POP_X+15, 0);
310 change_timing(0, rcd, 0, 0);
311 sflag++;
312 break;
313
314 case 5:
315 popclear();
316 cprint(POP_Y+3, POP_X+8, "tRP: ");
317 rp =getval(POP_Y+3, POP_X+15, 0);
318 change_timing(0, 0, rp, 0);
319 sflag++;
320 break;
321
322 case 6:
323 popclear();
324 cprint(POP_Y+3, POP_X+8, "tRAS: ");
325 ras =getval(POP_Y+3, POP_X+15, 0);
326 change_timing(0, 0, 0, ras);
327 sflag++;
328 break;
329
330 case 7:
331 popclear();
332 amd64_option();
333 sflag++;
334 popclear();
335 break;
336
337 case 8:
338 break;
339
340 case 11:
341 case 57:
342 sflag++;
343 /* 0/CR - Cancel */
344 break;
345 }
346 }
347}
348
349void get_option_1()
350{
Ben Gardner90f7d112016-03-15 15:25:22 -0500351 int rp=0, rcd=0, ras=0, sflag = 0;
Martin Roth9b1b3352016-02-24 12:27:06 -0800352
Ben Gardner90f7d112016-03-15 15:25:22 -0500353 while (!sflag)
Martin Roth9b1b3352016-02-24 12:27:06 -0800354 {
Ben Gardner90f7d112016-03-15 15:25:22 -0500355 switch (get_key()) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800356 case 2:
357 popclear();
358 cprint(POP_Y+3, POP_X+8, "tRCD: ");
359 rcd = getval(POP_Y+3, POP_X+15, 0);
360 popclear();
361
362 cprint(POP_Y+3, POP_X+8, "tRP: ");
363 rp = getval(POP_Y+3, POP_X+15, 0);
364 popclear();
365
366 cprint(POP_Y+3, POP_X+8, "tRAS: ");
367 ras = getval(POP_Y+3, POP_X+15, 0);
368 popclear();
369 change_timing(0, rcd, rp, ras);
370 break;
371
372 case 3:
373 popclear();
374 cprint(POP_Y+3, POP_X+8, "tRCD: ");
375 rcd =getval(POP_Y+3, POP_X+15, 0);
376 change_timing(0, rcd, 0, 0);
377 break;
378
379 case 4:
380 popclear();
381 cprint(POP_Y+3, POP_X+8, "tRP: ");
382 rp =getval(POP_Y+3, POP_X+15, 0);
383 change_timing(0, 0, rp, 0);
384 break;
385
386 case 5:
387 popclear();
388 cprint(POP_Y+3, POP_X+8, "tRAS: ");
389 ras =getval(POP_Y+3, POP_X+15, 0);
390 change_timing(0, 0, 0, ras);
391 break;
392
393 case 6:
394 popclear();
395 amd64_option();
396 sflag++;
397 popclear();
398 break;
399
400 case 7:
401 break;
402
403 case 11:
404 case 57:
405 sflag++;
406 /* 0/CR - Cancel */
407 break;
408 }
409 }
410}
411
412
413void get_menu(void)
414{
Ben Gardner90f7d112016-03-15 15:25:22 -0500415 int menu;
Martin Roth9b1b3352016-02-24 12:27:06 -0800416
417 find_memctr();
418
Ben Gardner90f7d112016-03-15 15:25:22 -0500419 switch (ctrl) {
420 case 0: menu = 2; break;
Martin Roth9b1b3352016-02-24 12:27:06 -0800421 case 1:
422 case 2:
423 case 3:
Ben Gardner90f7d112016-03-15 15:25:22 -0500424 case 4: menu = 0; break;
425 case 5: menu = 1; break;
426 case 6: menu = 0; break;
427 default: menu = -1; break;
Martin Roth9b1b3352016-02-24 12:27:06 -0800428 }
429
Ben Gardner90f7d112016-03-15 15:25:22 -0500430 if (menu == -1) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800431 popclear();
Ben Gardner90f7d112016-03-15 15:25:22 -0500432 } else if (menu == 0) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800433 cprint(POP_Y+1, POP_X+2, "Modify Timing:");
434 cprint(POP_Y+3, POP_X+5, "(1) Modify All ");
435 cprint(POP_Y+4, POP_X+5, "(2) Modify tCAS ");
436 cprint(POP_Y+5, POP_X+5, "(3) Modify tRCD ");
437 cprint(POP_Y+6, POP_X+5, "(4) Modify tRP ");
438 cprint(POP_Y+7, POP_X+5, "(5) Modify tRAS ");
439 cprint(POP_Y+8, POP_X+5, "(0) Cancel");
440 wait_keyup();
Ben Gardner90f7d112016-03-15 15:25:22 -0500441 get_option();
442 } else if (menu == 1) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800443 cprint(POP_Y+1, POP_X+2, "Modify Timing:");
444 cprint(POP_Y+3, POP_X+5, "(1) Modify All ");
445 cprint(POP_Y+4, POP_X+5, "(2) Modify tRCD ");
446 cprint(POP_Y+5, POP_X+5, "(3) Modify tRP ");
447 cprint(POP_Y+6, POP_X+5, "(4) Modify tRAS ");
448 cprint(POP_Y+7, POP_X+5, "(0) Cancel");
449 wait_keyup();
Ben Gardner90f7d112016-03-15 15:25:22 -0500450 get_option();
451 } else { // AMD64 special menu
Martin Roth9b1b3352016-02-24 12:27:06 -0800452 cprint(POP_Y+1, POP_X+2, "Modify Timing:");
453 cprint(POP_Y+3, POP_X+5, "(1) Modify All ");
454 cprint(POP_Y+4, POP_X+5, "(2) Modify tRCD ");
455 cprint(POP_Y+5, POP_X+5, "(3) Modify tRP ");
456 cprint(POP_Y+6, POP_X+5, "(4) Modify tRAS ");
457 cprint(POP_Y+7, POP_X+5, "(5) AMD64 Options");
458 cprint(POP_Y+8, POP_X+5, "(0) Cancel");
459 wait_keyup();
Ben Gardner90f7d112016-03-15 15:25:22 -0500460 get_option_1();
Martin Roth9b1b3352016-02-24 12:27:06 -0800461 }
462}
463
464int get_cas(void)
465{
466 int i852=0, cas=0;
467 ulong drc, ddr;
468 long *ptr;
469
Ben Gardner90f7d112016-03-15 15:25:22 -0500470 switch (ctrl) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800471 case 0: ddr = 1; break;
472 case 1:
473 case 2:
Ben Gardner90f7d112016-03-15 15:25:22 -0500474 case 3: ddr = 1; break;
Martin Roth9b1b3352016-02-24 12:27:06 -0800475 case 4:
476 pci_conf_read( 0, 0, 0, 0x44, 4, &ddr);
477 ddr &= 0xFFFFC000;
478 ptr=(long*)(ddr+0x120);
479 drc = *ptr;
480
481 if ((drc & 3) == 2) ddr = 2;
482 else ddr = 1;
483 break;
484 case 5: ddr = 2; break;
485 case 6: ddr = 1; i852 = 1; break;
486 default: ddr = 1;
487 }
488
Ben Gardner90f7d112016-03-15 15:25:22 -0500489 if (ddr == 1) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800490 cprint(POP_Y+3, POP_X+8, "tCAS: ");
491 cprint(POP_Y+5, POP_X+8, "(1) CAS 2.5 ");
492 cprint(POP_Y+6, POP_X+8, "(2) CAS 2 ");
Ben Gardner90f7d112016-03-15 15:25:22 -0500493 if (!i852) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800494 cprint(POP_Y+7, POP_X+8, "(3) CAS 3 ");
495 }
496 cas = getval(POP_Y+3, POP_X+15, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500497 } else if (ddr == 2) {
Martin Roth9b1b3352016-02-24 12:27:06 -0800498 cprint(POP_Y+3, POP_X+8, "tCAS: ");
499 cprint(POP_Y+5, POP_X+8, "(1) CAS 4 ");
500 cprint(POP_Y+6, POP_X+8, "(2) CAS 3 ");
501 cprint(POP_Y+7, POP_X+8, "(3) CAS 5 ");
502 cas = getval(POP_Y+3, POP_X+15, 0);
Ben Gardner90f7d112016-03-15 15:25:22 -0500503 } else {
Martin Roth9b1b3352016-02-24 12:27:06 -0800504 cas = -1;
505 }
506
507 popclear();
508 return (cas);
509}
510
511/////////////////////////////////////////////////////////
512// here we go for the exciting timing change part... //
513/////////////////////////////////////////////////////////
514
Ben Gardner90f7d112016-03-15 15:25:22 -0500515void change_timing_i852(int cas, int rcd, int rp, int ras)
516{
Martin Roth9b1b3352016-02-24 12:27:06 -0800517 ulong dramtlr;
518 ulong int1, int2;
519
520 pci_conf_read(0, 0, 1, 0x60, 4, &dramtlr);
521
522 // CAS Latency (tCAS)
523 int1 = dramtlr & 0xFF9F;
524 if (cas == 2) { int2 = int1 ^ 0x20; }
525 else if (cas == 1) { int2 = int1; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500526 else { int2 = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800527
528
529 // RAS-To-CAS (tRCD)
530 int1 = int2 & 0xFFF3;
531 if (rcd == 2) { int2 = int1 ^ 0x8; }
532 else if (rcd == 3) { int2 = int1 ^ 0x4; }
533 else if (rcd == 4) { int2 = int1; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500534 // else { int2 = int2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800535
536
537 // RAS Precharge (tRP)
538 int1 = int2 & 0xFFFC;
539 if (rp == 2) { int2 = int1 ^ 0x2; }
540 else if (rp == 3) { int2 = int1 ^ 0x1; }
541 else if (rp == 4) { int2 = int1; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500542 // else { int2 = int2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800543
544
545 // RAS Active to precharge (tRAS)
546 int1 = int2 & 0xF9FF;
Ben Gardner90f7d112016-03-15 15:25:22 -0500547 if (ras == 5) { int2 = int1 ^ 0x0600; }
548 else if (ras == 6) { int2 = int1 ^ 0x0400; }
549 else if (ras == 7) { int2 = int1 ^ 0x0200; }
550 else if (ras == 8) { int2 = int1; }
551 // else { int2 = int2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800552
553 pci_conf_write(0, 0, 1, 0x60, 4, int2);
554 __delay(500);
555}
556
557void change_timing_i925(int cas, int rcd, int rp, int ras)
558{
559 ulong int1, dev0, temp;
560 long *ptr;
561
562 //read MMRBAR
563 pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
564 dev0 &= 0xFFFFC000;
565
566 ptr=(long*)(dev0+0x114);
567 temp = *ptr;
568
569 // RAS-To-CAS (tRCD)
570 int1 = temp | 0x70;
571 if (rcd == 2) { temp = int1 ^ 0x70; }
572 else if (rcd == 3) { temp = int1 ^ 0x60; }
573 else if (rcd == 4) { temp = int1 ^ 0x50; }
574 else if (rcd == 5) { temp = int1 ^ 0x40; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500575 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800576
577 //RAS precharge (tRP)
578 int1 = temp | 0x7;
579 if (rp == 2) { temp = int1 ^ 0x7; }
580 else if (rp == 3) { temp = int1 ^ 0x6; }
581 else if (rp == 4) { temp = int1 ^ 0x5; }
582 else if (rp == 5) { temp = int1 ^ 0x4; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500583 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800584
Ben Gardner90f7d112016-03-15 15:25:22 -0500585 if (mem_ctr[ctrl].device == 0x2770) { // Lakeport?
Martin Roth9b1b3352016-02-24 12:27:06 -0800586 // RAS Active to precharge (tRAS)
Ben Gardner90f7d112016-03-15 15:25:22 -0500587 int1 = temp | 0xF80000; // bits 23:19
Martin Roth9b1b3352016-02-24 12:27:06 -0800588 if (ras == 4) { temp = int1 ^ 0xD80000; }
589 else if (ras == 5) { temp = int1 ^ 0xD00000; }
590 else if (ras == 6) { temp = int1 ^ 0xC80000; }
591 else if (ras == 7) { temp = int1 ^ 0xC00000; }
592 else if (ras == 8) { temp = int1 ^ 0xB80000; }
593 else if (ras == 9) { temp = int1 ^ 0xB00000; }
594 else if (ras == 10) { temp = int1 ^ 0xA80000; }
595 else if (ras == 11) { temp = int1 ^ 0xA00000; }
596 else if (ras == 12) { temp = int1 ^ 0x980000; }
597 else if (ras == 13) { temp = int1 ^ 0x900000; }
598 else if (ras == 14) { temp = int1 ^ 0x880000; }
599 else if (ras == 15) { temp = int1 ^ 0x800000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500600 // else { temp = temp; }
601 } else {
Martin Roth9b1b3352016-02-24 12:27:06 -0800602 // RAS Active to precharge (tRAS)
Ben Gardner90f7d112016-03-15 15:25:22 -0500603 int1 = temp | 0xF00000; // bits 23:20
Martin Roth9b1b3352016-02-24 12:27:06 -0800604 if (ras == 4) { temp = int1 ^ 0xB00000; }
605 else if (ras == 5) { temp = int1 ^ 0xA00000; }
606 else if (ras == 6) { temp = int1 ^ 0x900000; }
607 else if (ras == 7) { temp = int1 ^ 0x800000; }
608 else if (ras == 8) { temp = int1 ^ 0x700000; }
609 else if (ras == 9) { temp = int1 ^ 0x600000; }
610 else if (ras == 10) { temp = int1 ^ 0x500000; }
611 else if (ras == 11) { temp = int1 ^ 0x400000; }
612 else if (ras == 12) { temp = int1 ^ 0x300000; }
613 else if (ras == 13) { temp = int1 ^ 0x200000; }
614 else if (ras == 14) { temp = int1 ^ 0x100000; }
615 else if (ras == 15) { temp = int1 ^ 0x000000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500616 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800617 }
618
619 // CAS Latency (tCAS)
620 int1 = temp | 0x0300;
621 if (cas == 1) { temp = int1 ^ 0x200; } // cas 2.5
622 else if (cas == 2) { temp = int1 ^ 0x100; }
623 else if (cas == 3) { temp = int1 ^ 0x300; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500624 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800625
626 *ptr = temp;
627 __delay(500);
628 return;
629}
630
631void change_timing_Lakeport(int cas, int rcd, int rp, int ras)
632{
633 ulong int1, dev0, temp;
634 long *ptr;
635
636 //read MMRBAR
637 pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
638 dev0 &= 0xFFFFC000;
639
640 ptr=(long*)(dev0+0x114);
641 temp = *ptr;
642
643 // RAS-To-CAS (tRCD)
644 int1 = temp | 0x70;
645 if (rcd == 2) { temp = int1 ^ 0x70; }
646 else if (rcd == 3) { temp = int1 ^ 0x60; }
647 else if (rcd == 4) { temp = int1 ^ 0x50; }
648 else if (rcd == 5) { temp = int1 ^ 0x40; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500649 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800650
651 //RAS precharge (tRP)
652 int1 = temp | 0x7;
653 if (rp == 2) { temp = int1 ^ 0x7; }
654 else if (rp == 3) { temp = int1 ^ 0x6; }
655 else if (rp == 4) { temp = int1 ^ 0x5; }
656 else if (rp == 5) { temp = int1 ^ 0x4; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500657 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800658
659
660 // CAS Latency (tCAS)
661 int1 = temp | 0x0300;
662 if (cas == 1) { temp = int1 ^ 0x200; } // cas 2.5
663 else if (cas == 2) { temp = int1 ^ 0x100; }
664 else if (cas == 3) { temp = int1 ^ 0x300; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500665 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800666
667 *ptr = temp;
668 __delay(500);
669 return;
670}
671
Ben Gardner90f7d112016-03-15 15:25:22 -0500672void change_timing_i875(int cas, int rcd, int rp, int ras)
673{
Martin Roth9b1b3352016-02-24 12:27:06 -0800674 ulong int1, dev6, temp;
675 long *ptr;
676
677 /* Read the MMR Base Address & Define the pointer from the BAR6 overflow register */
678 pci_conf_read( 0, 6, 0, 0x10, 4, &dev6);
679
680 ptr=(long*)(dev6+0x60);
681
682 temp = *ptr;
683
684 // RAS-To-CAS (tRCD)
685 int1 = temp | 0xC;
686 if (rcd == 2) { temp = int1 ^ 0x4; }
687 else if (rcd == 3) { temp = int1 ^ 0x8; }
688 else if (rcd == 4) { temp = int1 ^ 0xC; }
689 else if (rcd == 5) { temp = int1 ^ 0xC; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500690 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800691
692
693 //RAS precharge (tRP)
694 int1 = temp | 0x3;
695 if (rp == 2) { temp = int1 ^ 0x1; }
696 else if (rp == 3) { temp = int1 ^ 0x2; }
697 else if (rp == 4) { temp = int1 ^ 0x3; }
698 else if (rp == 5) { temp = int1 ^ 0x3; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500699 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800700
701
702 // RAS Active to precharge (tRAS)
703 int1 = temp | 0x380;
704 if (ras == 5) { temp = int1 ^ 0x100; }
705 else if (ras == 6) { temp = int1 ^ 0x180; }
706 else if (ras == 7) { temp = int1 ^ 0x200; }
707 else if (ras == 8) { temp = int1 ^ 0x280; }
708 else if (ras == 9) { temp = int1 ^ 0x300; }
709 else if (ras == 10) { temp = int1 ^ 0x380; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500710 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800711
712 // CAS Latency (tCAS)
713 int1 = temp | 0x60;
714 if (cas == 1) { temp = int1 ^ 0x60; } // cas 2.5
715 else if (cas == 2) { temp = int1 ^ 0x40; }
716 else if (cas == 3) { temp = int1 ^ 0x20; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500717 // else { temp = temp; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800718
719 *ptr = temp;
720 __delay(500);
721 return;
722}
723
724
Ben Gardner90f7d112016-03-15 15:25:22 -0500725void change_timing_nf2(int cas, int rcd, int rp, int ras)
726{
Martin Roth9b1b3352016-02-24 12:27:06 -0800727 ulong dramtlr, dramtlr2;
728 ulong int1, int2;
729
730 pci_conf_read(0, 0, 1, 0x90, 4, &dramtlr);
731 pci_conf_read(0, 0, 1, 0xA0, 4, &dramtlr2);
732
733
734 // CAS Latency (tCAS)
735 int1 = dramtlr2 | 0x0070;
736 if (cas == 1) { int2 = int1 ^ 0x10; } // cas = 2.5
737 else if (cas == 2) { int2 = int1 ^ 0x50; }
738 else if (cas == 3) { int2 = int1 ^ 0x40; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500739 else { int2 = dramtlr2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800740
741 pci_conf_write(0, 0, 1, 0xA0, 4, int2);
742
743 // RAS-To-CAS (tRCD)
744
745 int1 = dramtlr | 0x700000;
746 if (rcd == 2) { int2 = int1 ^ 0x500000; }
747 else if (rcd == 3) { int2 = int1 ^ 0x400000; }
748 else if (rcd == 4) { int2 = int1 ^ 0x300000; }
749 else if (rcd == 5) { int2 = int1 ^ 0x200000; }
750 else if (rcd == 6) { int2 = int1 ^ 0x100000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500751 else { int2 = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800752
753
754 // RAS Precharge (tRP)
755 int1 = int2 | 0x70000000;
756 if (rp == 2) { int2 = int1 ^ 0x50000000; }
757 else if (rp == 3) { int2 = int1 ^ 0x40000000; }
758 else if (rp == 4) { int2 = int1 ^ 0x30000000; }
759 else if (rp == 5) { int2 = int1 ^ 0x20000000; }
760 else if (rp == 6) { int2 = int1 ^ 0x10000000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500761 // else { int2 = int2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800762
763
764 // RAS Active to precharge (tRAS)
765
766 int1 = int2 | 0x78000;
767 if (ras == 4) { int2 = int1 ^ 0x58000; }
768 else if (ras == 5) { int2 = int1 ^ 0x50000; }
769 else if (ras == 6) { int2 = int1 ^ 0x48000; }
770 else if (ras == 7) { int2 = int1 ^ 0x40000; }
771 else if (ras == 8) { int2 = int1 ^ 0x38000; }
772 else if (ras == 9) { int2 = int1 ^ 0x30000; }
773 else if (ras == 10) { int2 = int1 ^ 0x28000; }
774 else if (ras == 11) { int2 = int1 ^ 0x20000; }
775 else if (ras == 12) { int2 = int1 ^ 0x18000; }
776 else if (ras == 13) { int2 = int1 ^ 0x10000; }
777 else if (ras == 14) { int2 = int1 ^ 0x08000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500778 // else { int2 = int2; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800779
780
781 pci_conf_write(0, 0, 1, 0x90, 4, int2);
782 __delay(500);
783}
784
785
Ben Gardner90f7d112016-03-15 15:25:22 -0500786void change_timing_amd64(int cas, int rcd, int rp, int ras)
787{
Martin Roth9b1b3352016-02-24 12:27:06 -0800788 ulong dramtlr;
789 ulong int1= 0x0;
790
791 pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);
792
793 // RAS-To-CAS (tRCD)
794 int1 = dramtlr | 0x7000;
795 if (rcd == 2) { dramtlr = int1 ^ 0x5000; }
796 else if (rcd == 3) { dramtlr = int1 ^ 0x4000; }
797 else if (rcd == 4) { dramtlr = int1 ^ 0x3000; }
798 else if (rcd == 5) { dramtlr = int1 ^ 0x2000; }
799 else if (rcd == 6) { dramtlr = int1 ^ 0x1000; }
800 else if (rcd == 1) { dramtlr = int1 ^ 0x6000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500801 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800802
803
804 //RAS precharge (tRP)
805 int1 = dramtlr | 0x7000000;
806 if (rp == 2) { dramtlr = int1 ^ 0x5000000; }
807 else if (rp == 3) { dramtlr = int1 ^ 0x4000000; }
808 else if (rp == 1) { dramtlr = int1 ^ 0x6000000; }
809 else if (rp == 4) { dramtlr = int1 ^ 0x3000000; }
810 else if (rp == 5) { dramtlr = int1 ^ 0x2000000; }
811 else if (rp == 6) { dramtlr = int1 ^ 0x1000000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500812 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800813
814
815 // RAS Active to precharge (tRAS)
816 int1 = dramtlr | 0xF00000;
817 if (ras == 5) { dramtlr = int1 ^ 0xA00000; }
818 else if (ras == 6) { dramtlr = int1 ^ 0x900000; }
819 else if (ras == 7) { dramtlr = int1 ^ 0x800000; }
820 else if (ras == 8) { dramtlr = int1 ^ 0x700000; }
821 else if (ras == 9) { dramtlr = int1 ^ 0x600000; }
822 else if (ras == 10) { dramtlr = int1 ^ 0x500000; }
823 else if (ras == 11) { dramtlr = int1 ^ 0x400000; }
824 else if (ras == 12) { dramtlr = int1 ^ 0x300000; }
825 else if (ras == 13) { dramtlr = int1 ^ 0x200000; }
826 else if (ras == 14) { dramtlr = int1 ^ 0x100000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500827 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800828
829
830 // CAS Latency (tCAS)
Ben Gardner90f7d112016-03-15 15:25:22 -0500831 int1 = dramtlr | 0x7; // some changes will cause the system hang, tried Draminit to no avail
832 if (cas == 1) { dramtlr = int1 ^ 0x2; } // cas 2.5
Martin Roth9b1b3352016-02-24 12:27:06 -0800833 else if (cas == 2) { dramtlr = int1 ^ 0x6; }
834 else if (cas == 3) { dramtlr = int1 ^ 0x5; }
835 else if (cas == 4) { dramtlr = int1 ^ 0x7; } //cas 1.5 on a64
Ben Gardner90f7d112016-03-15 15:25:22 -0500836 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800837
838// pci_conf_read(0, 24, 2, 0x90, 4, &dramcr);// use dram init
839 pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
840 __delay(500);
841
842////////////////////////////////////////////////////////////////
843// trying using the draminit, but do not work
844}
845
846// copy from lib.c code to add delay to chipset timing modification
847void __delay(ulong loops)
848{
849 int d0;
Ben Gardner90f7d112016-03-15 15:25:22 -0500850 __asm__ __volatile__ (
Martin Roth9b1b3352016-02-24 12:27:06 -0800851 "\tjmp 1f\n"
852 ".align 16\n"
853 "1:\tjmp 2f\n"
854 ".align 16\n"
855 "2:\tdecl %0\n\tjns 2b"
Ben Gardner90f7d112016-03-15 15:25:22 -0500856 : "=&a" (d0)
857 : "0" (loops));
Martin Roth9b1b3352016-02-24 12:27:06 -0800858}
859
860void amd64_tweak(int rwt, int wrt, int ref, int en2t, int rct, int rrd, int rwqb, int wr)
861{
862 ulong dramtlr;
863 ulong int1= 0x0;
864
865 pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);
866
867 // Row Cycle time
868 int1 = dramtlr | 0xF0;
Ben Gardner90f7d112016-03-15 15:25:22 -0500869 if (rct == 7) { dramtlr = int1 ^ 0xF0; }
870 else if (rct == 8) { dramtlr = int1 ^ 0xE0; }
871 else if (rct == 9) { dramtlr = int1 ^ 0xD0; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800872 else if (rct == 10) { dramtlr = int1 ^ 0xC0; }
873 else if (rct == 11) { dramtlr = int1 ^ 0xB0; }
874 else if (rct == 12) { dramtlr = int1 ^ 0xA0; }
875 else if (rct == 13) { dramtlr = int1 ^ 0x90; }
876 else if (rct == 14) { dramtlr = int1 ^ 0x80; }
877 else if (rct == 15) { dramtlr = int1 ^ 0x70; }
878 else if (rct == 16) { dramtlr = int1 ^ 0x60; }
879 else if (rct == 17) { dramtlr = int1 ^ 0x50; }
880 else if (rct == 18) { dramtlr = int1 ^ 0x40; }
881 else if (rct == 19) { dramtlr = int1 ^ 0x30; }
882 else if (rct == 20) { dramtlr = int1 ^ 0x20; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500883 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800884
885 //Active-avtive ras-ras delay
886 int1 = dramtlr | 0x70000;
887 if (rrd == 2) { dramtlr = int1 ^ 0x50000; } // 2 bus clocks
888 else if (rrd == 3) { dramtlr = int1 ^ 0x40000; } // 3 bus clocks
889 else if (rrd == 4) { dramtlr = int1 ^ 0x30000; } // 4 bus clocks
Ben Gardner90f7d112016-03-15 15:25:22 -0500890 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800891
892 //Write recovery time
893 int1 = dramtlr | 0x10000000;
894 if (wr == 2) { dramtlr = int1 ^ 0x10000000; } // 2 bus clocks
895 else if (wr == 3) { dramtlr = int1 ^ 0x00000000; } // 3 bus clocks
Ben Gardner90f7d112016-03-15 15:25:22 -0500896 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800897
898 pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
899 __delay(500);
900 //////////////////////////////////////////////
901
902 pci_conf_read(0, 24, 2, 0x8C, 4, &dramtlr);
903
904 // Write-to read delay
905 int1 = dramtlr | 0x1;
906 if (wrt == 2) { dramtlr = int1 ^ 0x0; }
907 else if (wrt == 1) { dramtlr = int1 ^ 0x1; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500908 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800909
910 // Read-to Write delay
911 int1 = dramtlr | 0x70;
912 if (rwt == 1) { dramtlr = int1 ^ 0x70; }
913 else if (rwt == 2) { dramtlr = int1 ^ 0x60; }
914 else if (rwt == 3) { dramtlr = int1 ^ 0x50; }
915 else if (rwt == 4) { dramtlr = int1 ^ 0x40; }
916 else if (rwt == 5) { dramtlr = int1 ^ 0x30; }
917 else if (rwt == 6) { dramtlr = int1 ^ 0x20; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500918 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800919
920 //Refresh Rate
921 int1 = dramtlr | 0x1800;
922 if (ref == 1) { dramtlr = int1 ^ 0x1800; } // 15.6us
923 else if (ref == 2) { dramtlr = int1 ^ 0x1000; } // 7.8us
924 else if (ref == 3) { dramtlr = int1 ^ 0x0800; } // 3.9us
Ben Gardner90f7d112016-03-15 15:25:22 -0500925 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800926
927 pci_conf_write(0, 24, 2, 0x8c, 4, dramtlr);
928 __delay(500);
929 /////////////////////////////////////
930
931 pci_conf_read(0, 24, 2, 0x90, 4, &dramtlr);
932
933 // Enable 2t command
934 int1 = dramtlr | 0x10000000;
935 if (en2t == 2) { dramtlr = int1 ^ 0x00000000; } // 2T
936 else if (en2t == 1) { dramtlr = int1 ^ 0x10000000; } // 1T
Ben Gardner90f7d112016-03-15 15:25:22 -0500937 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800938
939 // Read Write queue bypass count
940 int1 = dramtlr | 0xC000;
941 if (rwqb == 2) { dramtlr = int1 ^ 0xC000; }
942 else if (rwqb == 4) { dramtlr = int1 ^ 0x8000; }
943 else if (rwqb == 8) { dramtlr = int1 ^ 0x4000; }
944 else if (rwqb == 16) { dramtlr = int1 ^ 0x0000; }
Ben Gardner90f7d112016-03-15 15:25:22 -0500945 // else { dramtlr = dramtlr; }
Martin Roth9b1b3352016-02-24 12:27:06 -0800946
947 pci_conf_write(0, 24, 2, 0x90, 4, dramtlr);
948 __delay(500);
949 restart();
950}