Another round of semi-automated white space clean up

I used Uncrustify, meld, and some hand-editing to clean up the white space.
See https://review.coreboot.org/#/c/13963/ for method details.

Change-Id: I0ec070969d7660cdea485bd3bce49267a7389814
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/controller.c b/controller.c
index e4ebdf0..da05d70 100644
--- a/controller.c
+++ b/controller.c
@@ -37,23 +37,23 @@
 */
 /* controller ECC capabilities and mode */
 #define __ECC_UNEXPECTED 1      /* Unknown ECC capability present */
-#define __ECC_DETECT     2	/* Can detect ECC errors */
-#define __ECC_CORRECT    4	/* Can correct some ECC errors */
-#define __ECC_SCRUB      8	/* Can scrub corrected ECC errors */
-#define __ECC_CHIPKILL  16	/* Can corrected multi-errors */
+#define __ECC_DETECT     2      /* Can detect ECC errors */
+#define __ECC_CORRECT    4      /* Can correct some ECC errors */
+#define __ECC_SCRUB      8      /* Can scrub corrected ECC errors */
+#define __ECC_CHIPKILL  16      /* Can corrected multi-errors */
 
 #define ECC_UNKNOWN      (~0UL)    /* Unknown error correcting ability/status */
 #define ECC_NONE         0       /* Doesnt support ECC (or is BIOS disabled) */
 #define ECC_RESERVED     __ECC_UNEXPECTED  /* Reserved ECC type */
 #define ECC_DETECT       __ECC_DETECT
 #define ECC_CORRECT      (__ECC_DETECT | __ECC_CORRECT)
-#define ECC_CHIPKILL	 (__ECC_DETECT | __ECC_CORRECT | __ECC_CHIPKILL)
+#define ECC_CHIPKILL     (__ECC_DETECT | __ECC_CORRECT | __ECC_CHIPKILL)
 #define ECC_SCRUB        (__ECC_DETECT | __ECC_CORRECT | __ECC_SCRUB)
 
 
 static struct ecc_info {
-	int index;
-	int poll;
+	int      index;
+	int      poll;
 	unsigned bus;
 	unsigned dev;
 	unsigned fn;
@@ -66,12 +66,12 @@
 	 * host bridge, and the host bridge is not on bus 0  device 0
 	 * fn 0.  But just in case leave these as variables.
 	 */
-	.bus = 0,
-	.dev = 0,
-	.fn = 0,
+	.bus   = 0,
+	.dev   = 0,
+	.fn    = 0,
 	/* Properties of the current memory controller */
-	.cap = ECC_UNKNOWN,
-	.mode = ECC_UNKNOWN,
+	.cap   = ECC_UNKNOWN,
+	.mode  = ECC_UNKNOWN,
 };
 
 
@@ -83,19 +83,18 @@
 	double amd_raw_temp;
 
 	// Only enable coretemp if IMC is known
-	if(imc_type == 0) { return; }
+	if (imc_type == 0) { return; }
 
 	tnow = 0;
 
 	// Intel  CPU
-	if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.max_cpuid >= 6)
-	{
-		if(cpu_id.dts_pmp & 1){
+	if (cpu_id.vend_id.char_array[0] == 'G' && cpu_id.max_cpuid >= 6) {
+		if (cpu_id.dts_pmp & 1) {
 			rdmsr(MSR_IA32_THERM_STATUS, msrl, msrh);
 			tabs = ((msrl >> 16) & 0x7F);
 			rdmsr(MSR_IA32_TEMPERATURE_TARGET, msrl, msrh);
 			tjunc = ((msrl >> 16) & 0x7F);
-			if(tjunc < 50 || tjunc > 125) { tjunc = 90; } // assume Tjunc = 90°C if boggus value received.
+			if (tjunc < 50 || tjunc > 125) { tjunc = 90; } // assume Tjunc = 90°C if boggus value received.
 			tnow = tjunc - tabs;
 			dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
 			v->check_temp = tnow;
@@ -104,15 +103,12 @@
 	}
 
 	// AMD CPU
-	if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.extendedFamily > 0)
-	{
+	if (cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.extendedFamily > 0) {
 		pci_conf_read(0, 24, 3, 0xA4, 4, &rtcr);
 		amd_raw_temp = ((rtcr >> 21) & 0x7FF);
 		v->check_temp = (int)(amd_raw_temp / 8);
 		dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
 	}
-
-
 }
 
 void print_cpu_line(float dram_freq, float fsb_freq, int ram_type)
@@ -126,25 +122,23 @@
 	cprint(LINE_CPU, cur_col, "MHz (");
 	cur_col += 5;
 
-	switch(ram_type)
-	{
-		default:
-		case 1:
-			cprint(LINE_CPU, cur_col, "DDR-");
-			cur_col += 4;
-			break;
-		case 2:
-			cprint(LINE_CPU, cur_col, "DDR2-");
-			cur_col += 5;
-			break;
-		case 3:
-			cprint(LINE_CPU, cur_col, "DDR3-");
-			cur_col += 5;
-			break;
+	switch (ram_type) {
+	default:
+	case 1:
+		cprint(LINE_CPU, cur_col, "DDR-");
+		cur_col += 4;
+		break;
+	case 2:
+		cprint(LINE_CPU, cur_col, "DDR2-");
+		cur_col += 5;
+		break;
+	case 3:
+		cprint(LINE_CPU, cur_col, "DDR3-");
+		cur_col += 5;
+		break;
 	}
 
-	if(dram_freq < 500)
-	{
+	if (dram_freq < 500) {
 		dprint(LINE_CPU, cur_col, dram_freq*2, 3, 0);
 		cur_col += 3;
 	} else {
@@ -154,14 +148,12 @@
 	cprint(LINE_CPU, cur_col, ")");
 	cur_col++;
 
-	if(fsb_freq > 10)
-	{
+	if (fsb_freq > 10) {
 		cprint(LINE_CPU, cur_col, " - BCLK: ");
 		cur_col += 9;
 
 		dprint(LINE_CPU, cur_col, fsb_freq, 3, 0);
 	}
-
 }
 
 void print_ram_line(float cas, int rcd, int rp, int ras, int chan)
@@ -213,28 +205,26 @@
 	}
 
 
-	switch(chan)
-	{
-		case 0:
-			break;
-		case 1:
-			cprint(LINE_RAM, cur_col, " @ 64-bit Mode");
-			break;
-		case 2:
-			cprint(LINE_RAM, cur_col, " @ 128-bit Mode");
-			break;
-		case 3:
-			cprint(LINE_RAM, cur_col, " @ 192-bit Mode");
-			break;
-		case 4:
-			cprint(LINE_RAM, cur_col, " @ 256-bit Mode");
-			break;
+	switch (chan) {
+	case 0:
+		break;
+	case 1:
+		cprint(LINE_RAM, cur_col, " @ 64-bit Mode");
+		break;
+	case 2:
+		cprint(LINE_RAM, cur_col, " @ 128-bit Mode");
+		break;
+	case 3:
+		cprint(LINE_RAM, cur_col, " @ 192-bit Mode");
+		break;
+	case 4:
+		cprint(LINE_RAM, cur_col, " @ 256-bit Mode");
+		break;
 	}
 }
 
 static void poll_fsb_nothing(void)
 {
-
 	char *name;
 
 	/* Print the controller name */
@@ -278,7 +268,6 @@
 	if (!(dev0 & 0x1)) {
 		pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
 	}
-
 }
 
 
@@ -294,28 +283,27 @@
 
 	/* First, locate the PCI bus where the MCH is located */
 
-	for(i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
+	for (i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
 		vid &= 0xFFFF;
 		did &= 0xFF00;
-		if(vid == 0x8086 && did >= 0x2C00) {
+		if (vid == 0x8086 && did >= 0x2C00) {
 			nhm_bus = possible_nhm_bus[i];
-			}
-}
+		}
+	}
 
 	/* Now, we have the last IMC bus number in nhm_bus */
 	/* Check for ECC & Scrub */
 
 	pci_conf_read(nhm_bus, 3, 0, 0x4C, 2, &mc_control);
-	if((mc_control >> 4) & 1) {
+	if ((mc_control >> 4) & 1) {
 		ctrl.mode = ECC_CORRECT;
 		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
-		if(mc_ssrcontrol & 3) {
+		if (mc_ssrcontrol & 3) {
 			ctrl.mode = ECC_SCRUB;
 		}
 	}
-
 }
 
 static void setup_nhm32(void)
@@ -329,27 +317,26 @@
 	ctrl.mode = ECC_NONE;
 
 	/* First, locate the PCI bus where the MCH is located */
-	for(i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
+	for (i = 0; i < sizeof(possible_nhm_bus) / sizeof(possible_nhm_bus[0]); i++) {
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x00, 2, &vid);
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
 		vid &= 0xFFFF;
 		did &= 0xFF00;
-		if(vid == 0x8086 && did >= 0x2C00) {
+		if (vid == 0x8086 && did >= 0x2C00) {
 			nhm_bus = possible_nhm_bus[i];
-			}
+		}
 	}
 
 	/* Now, we have the last IMC bus number in nhm_bus */
 	/* Check for ECC & Scrub */
 	pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
-	if((mc_control >> 1) & 1) {
+	if ((mc_control >> 1) & 1) {
 		ctrl.mode = ECC_CORRECT;
 		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
-		if(mc_ssrcontrol & 1) {
+		if (mc_ssrcontrol & 1) {
 			ctrl.mode = ECC_SCRUB;
 		}
 	}
-
 }
 
 static void setup_amd64(void)
@@ -370,7 +357,7 @@
 	if (cpu_id.vers.bits.extendedModel >= 4) {
 		/* NEW K8 0Fh Family 90 nm */
 
-		if ((dramcl >> 19)&1){
+		if ((dramcl >> 19)&1) {
 			/* Fill in the correct memory capabilites */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
 			ctrl.mode = ddim[(nbxcfg >> 22)&3];
@@ -384,11 +371,10 @@
 		/* Clear any previous error */
 		pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
 		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
-
 	} else {
 		/* OLD K8 130 nm */
 
-		if ((dramcl >> 17)&1){
+		if ((dramcl >> 17)&1) {
 			/* Fill in the correct memory capabilites */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
 			ctrl.mode = ddim[(nbxcfg >> 22)&3];
@@ -421,38 +407,35 @@
 	// Check First if ECC DRAM Modules are used */
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
 
-		if ((dramcl >> 19)&1){
-			// Fill in the correct memory capabilites */
-			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
-			ctrl.mode = ddim[(nbxcfg >> 22)&3];
-		} else {
-			ctrl.mode = ECC_NONE;
-		}
-		// Enable NB ECC Logging by MSR Write */
-		rdmsr(0x017B, mcgsrl, mcgsth);
-		wrmsr(0x017B, 0x10, mcgsth);
+	if ((dramcl >> 19)&1) {
+		// Fill in the correct memory capabilites */
+		pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
+		ctrl.mode = ddim[(nbxcfg >> 22)&3];
+	} else {
+		ctrl.mode = ECC_NONE;
+	}
+	// Enable NB ECC Logging by MSR Write */
+	rdmsr(0x017B, mcgsrl, mcgsth);
+	wrmsr(0x017B, 0x10, mcgsth);
 
-		// Clear any previous error */
-		pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
-		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
+	// Clear any previous error */
+	pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
+	pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
 
-		/* Enable ECS */
-		rdmsr(0xC001001F, msr_low,  msr_high);
-		wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
-		rdmsr(0xC001001F, msr_low,  msr_high);
-
+	/* Enable ECS */
+	rdmsr(0xC001001F, msr_low,  msr_high);
+	wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
+	rdmsr(0xC001001F, msr_low,  msr_high);
 }
 
 static void setup_apu(void)
 {
-
 	ulong msr_low, msr_high;
 
 	/* Enable ECS */
 	rdmsr(0xC001001F, msr_low,  msr_high);
 	wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
 	rdmsr(0xC001001F, msr_low,  msr_high);
-
 }
 
 /*
@@ -512,7 +495,7 @@
 	/* Fill in the correct memory capabilites */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5a, 2, &dram_status);
 	ctrl.cap = ECC_CORRECT;
-	ctrl.mode = (dram_status & (1 << 2))?ECC_CORRECT: ECC_NONE;
+	ctrl.mode = (dram_status & (1 << 2)) ? ECC_CORRECT : ECC_NONE;
 }
 
 /*
@@ -691,21 +674,17 @@
 		/* Now, we can active Dev1/Fun1 */
 		/* Thanks to Tyan for providing us the board to solve this */
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE0, 2, &dvnp);
-		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn , 0xE0, 2, (dvnp & 0xFE));
+		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xE0, 2, (dvnp & 0xFE));
 
 		/* Clear any routing of ECC errors to interrupts that the BIOS might have set up */
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x88, 1, 0x0);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8A, 1, 0x0);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8C, 1, 0x0);
-
-
 	}
 
 	/* Clear any prexisting error reports */
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, 3);
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, 3);
-
-
 }
 
 static void setup_iE7520(void)
@@ -735,12 +714,11 @@
 
 	/* Now, we can activate Fun1 */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xF4, 1, &dvnp1);
-	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn , 0xF4, 1, (dvnp1 | 0x20));
+	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xF4, 1, (dvnp1 | 0x20));
 
 	/* Clear any prexisting error reports */
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, 0x4747);
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, 0x4747);
-
 }
 
 /*
@@ -891,9 +869,8 @@
 
 static void setup_i875(void)
 {
-
 	long *ptr;
-	ulong dev0, dev6 ;
+	ulong dev0, dev6;
 
 	/* Fill in the correct memory capabilites */
 
@@ -921,7 +898,6 @@
 
 static void setup_i925(void)
 {
-
 	// Activate MMR I/O
 	ulong dev0, drc;
 	unsigned long tolm;
@@ -952,12 +928,10 @@
 	} else {
 		ctrl.mode = ECC_NONE;
 	}
-
 }
 
 static void setup_p35(void)
 {
-
 	// Activate MMR I/O
 	ulong dev0, capid0;
 
@@ -1318,16 +1292,13 @@
 
 
 	/* Find multiplier (by MSR) */
-	if (cpu_id.vers.bits.family == 6)
-	{
-		if(cpu_id.fid.bits.eist & 1)
-		{
+	if (cpu_id.vers.bits.family == 6) {
+		if (cpu_id.fid.bits.eist & 1) {
 			rdmsr(0x198, msr_lo, msr_hi);
 			coef = ((msr_lo) >> 8) & 0x1F;
 			if ((msr_lo >> 14) & 0x1) { coef += 0.5f; }
 			// Atom Fix
-			if(coef == 6)
-			{
+			if (coef == 6) {
 				coef = ((msr_hi) >> 8) & 0x1F;
 				if ((msr_hi >> 14) & 0x1) { coef += 0.5f; }
 			}
@@ -1335,17 +1306,12 @@
 			rdmsr(0x2A, msr_lo, msr_hi);
 			coef = (msr_lo >> 22) & 0x1F;
 		}
-	}
-	else
-	{
-		if (cpu_id.vers.bits.model < 2)
-		{
+	} else {
+		if (cpu_id.vers.bits.model < 2) {
 			rdmsr(0x2A, msr_lo, msr_hi);
 			coef = (msr_lo >> 8) & 0xF;
 			coef = p4model1ratios[(int)coef];
-		}
-		else
-		{
+		} else {
 			rdmsr(0x2C, msr_lo, msr_hi);
 			coef = (msr_lo >> 24) & 0x1F;
 		}
@@ -1362,15 +1328,16 @@
 	/* Find multiplier (by MSR) */
 	/* First, check if Flexible Ratio is Enabled */
 	rdmsr(0x194, msr_lo, msr_hi);
-	if((msr_lo >> 16) & 1){
+	if ((msr_lo >> 16) & 1) {
 		coef = (msr_lo >> 8) & 0xFF;
-	 } else {
+	} else {
 		rdmsr(0xCE, msr_lo, msr_hi);
 		coef = (msr_lo >> 8) & 0xFF;
-	 }
+	}
 
 	return coef;
 }
+
 static float getSNBmultiplier(void)
 {
 	unsigned int msr_lo, msr_hi;
@@ -1402,11 +1369,11 @@
 
 	/* Get RAM ratio */
 	switch (mdr & 0x3) {
-		default:
-		case 0:	dramratio = 3.0f; break;
-		case 1:	dramratio = 4.0f; break;
-		case 2:	dramratio = 5.0f; break;
-		case 3:	dramratio = 6.0f; break;
+	default:
+	case 0: dramratio = 3.0f; break;
+	case 1: dramratio = 4.0f; break;
+	case 2: dramratio = 5.0f; break;
+	case 3: dramratio = 6.0f; break;
 	}
 
 	// Compute FSB & RAM Frequency
@@ -1415,11 +1382,10 @@
 
 	// Print'em all. Whoa !
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_amd64(void) {
-
+static void poll_fsb_amd64(void)
+{
 	unsigned int mcgsrl;
 	unsigned int mcgsth;
 	unsigned long fid, temp2;
@@ -1451,54 +1417,53 @@
 
 	/* Next, we need the clock ratio */
 	if (cpu_id.vers.bits.extendedModel >= 4) {
-	/* K8 0FH */
+		/* K8 0FH */
 		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 		temp2 = (dramchr & 0x7);
 		clockratio = coef;
 		ram_type = 2;
 
 		switch (temp2) {
-			case 0x0:
-				clockratio = (int)(coef);
-				break;
-			case 0x1:
-				clockratio = (int)(coef * 3.0f/4.0f);
-				break;
-			case 0x2:
-				clockratio = (int)(coef * 3.0f/5.0f);
-				break;
-			case 0x3:
-				clockratio = (int)(coef * 3.0f/6.0f);
-				break;
-			}
-
-	 } else {
-	 /* OLD K8 */
+		case 0x0:
+			clockratio = (int)(coef);
+			break;
+		case 0x1:
+			clockratio = (int)(coef * 3.0f/4.0f);
+			break;
+		case 0x2:
+			clockratio = (int)(coef * 3.0f/5.0f);
+			break;
+		case 0x3:
+			clockratio = (int)(coef * 3.0f/6.0f);
+			break;
+		}
+	} else {
+		/* OLD K8 */
 		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 		temp2 = (dramchr >> 20) & 0x7;
 		ram_type = 1;
 		clockratio = coef;
 
 		switch (temp2) {
-			case 0x0:
-				clockratio = (int)(coef * 2.0f);
-				break;
-			case 0x2:
-				clockratio = (int)((coef * 3.0f/2.0f) + 0.81f);
-				break;
-			case 0x4:
-				clockratio = (int)((coef * 4.0f/3.0f) + 0.81f);
-				break;
-			case 0x5:
-				clockratio = (int)((coef * 6.0f/5.0f) + 0.81f);
-				break;
-			case 0x6:
-				clockratio = (int)((coef * 10.0f/9.0f) + 0.81f);
-				break;
-			case 0x7:
-				clockratio = (int)(coef + 0.81f);
-				break;
-			}
+		case 0x0:
+			clockratio = (int)(coef * 2.0f);
+			break;
+		case 0x2:
+			clockratio = (int)((coef * 3.0f/2.0f) + 0.81f);
+			break;
+		case 0x4:
+			clockratio = (int)((coef * 4.0f/3.0f) + 0.81f);
+			break;
+		case 0x5:
+			clockratio = (int)((coef * 6.0f/5.0f) + 0.81f);
+			break;
+		case 0x6:
+			clockratio = (int)((coef * 10.0f/9.0f) + 0.81f);
+			break;
+		case 0x7:
+			clockratio = (int)(coef + 0.81f);
+			break;
+		}
 	}
 
 	/* Compute the final DRAM Clock */
@@ -1506,11 +1471,10 @@
 
 	/* ...and print */
 	print_cpu_line(dramclock, (extclock / 1000 / coef), ram_type);
-
 }
 
-static void poll_fsb_k10(void) {
-
+static void poll_fsb_k10(void)
+{
 	unsigned int mcgsrl;
 	unsigned int mcgsth;
 	unsigned long temp2;
@@ -1520,17 +1484,17 @@
 	ulong offset = 0;
 	int ram_type = 2;
 
-		/* First, we need the clock ratio */
-		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
-		temp2 = (dramchr & 0x7);
+	/* First, we need the clock ratio */
+	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
+	temp2 = (dramchr & 0x7);
 
-		switch (temp2) {
-			case 0x7: temp2++;
-			case 0x6: temp2++;
-			case 0x5: temp2++;
-			case 0x4: temp2++;
-			default:  temp2 += 3;
-		}
+	switch (temp2) {
+	case 0x7: temp2++;
+	case 0x6: temp2++;
+	case 0x5: temp2++;
+	case 0x4: temp2++;
+	default:  temp2 += 3;
+	}
 
 	/* Compute the final DRAM Clock */
 	if (cpu_id.vers.bits.extendedModel == 1) {
@@ -1547,132 +1511,126 @@
 
 		pci_conf_read(0, 24, 3, 0xD4, 4, &mainPllId);
 
-		if ( mainPllId & 0x40 )
+		if (mainPllId & 0x40)
 			mainPllId &= 0x3F;
 		else
-			mainPllId = 8;	/* FID for 1600 */
+			mainPllId = 8;  /* FID for 1600 */
 
 		mcgsth = (mcgsth >> 17) & 0x3F;
-		if ( mcgsth ) {
-			if ( mainPllId > mcgsth )
+		if (mcgsth) {
+			if (mainPllId > mcgsth)
 				mainPllId = mcgsth;
 		}
 
 		dx = (mainPllId + 8) * 1200;
-		for ( divisor = 3; divisor < 100; divisor++ )
-			if ( (dx / divisor) <= target )
+		for (divisor = 3; divisor < 100; divisor++)
+			if ( (dx / divisor) <= target)
 				break;
 
 
-	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
+		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
-	// If Channel A not enabled, switch to channel B
-	if(((dramchr>>14) & 0x1))
-	{
-		offset = 0x100;
-		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
-	}
+		// If Channel A not enabled, switch to channel B
+		if (((dramchr>>14) & 0x1)) {
+			offset = 0x100;
+			pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
+		}
 
-	//DDR2 or DDR3
-	if ((dramchr >> 8)&1) {
-		ram_type = 3;
-	} else {
-		ram_type = 2;;
-	}
+		//DDR2 or DDR3
+		if ((dramchr >> 8)&1) {
+			ram_type = 3;
+		} else {
+			ram_type = 2;
+		}
 
 		dramclock = ((dx / divisor) / 6.0) + 0.25;
-}
+	}
 
 	/* ...and print */
 	print_cpu_line(dramclock, 0, ram_type);
-
 }
 
-static void poll_fsb_k12(void) {
-
+static void poll_fsb_k12(void)
+{
 	unsigned long temp2;
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb, did;
-	unsigned int mcgsrl,mcgsth, fid, did_raw;
+	unsigned int mcgsrl, mcgsth, fid, did_raw;
 
 	// Get current FID & DID
- 	rdmsr(0xc0010071, mcgsrl, mcgsth);
- 	did_raw = mcgsrl & 0xF;
- 	fid = (mcgsrl >> 4) & 0xF;
+	rdmsr(0xc0010071, mcgsrl, mcgsth);
+	did_raw = mcgsrl & 0xF;
+	fid = (mcgsrl >> 4) & 0xF;
 
-	switch(did_raw)
-	{
-		default:
-		case 0x0:
-			did = 1.0f;
-			break;
-		case 0x1:
-			did = 1.5f;
-			break;
-		case 0x2:
-			did = 2.0f;
-			break;
-		case 0x3:
-			did = 3.0f;
-			break;
-		case 0x4:
-			did = 4.0f;
-			break;
-		case 0x5:
-			did = 6.0f;
-			break;
-		case 0x6:
-			did = 8.0f;
-			break;
-		case 0x7:
-			did = 12.0f;
-			break;
-		case 0x8:
-			did = 16.0f;
-			break;
+	switch (did_raw) {
+	default:
+	case 0x0:
+		did = 1.0f;
+		break;
+	case 0x1:
+		did = 1.5f;
+		break;
+	case 0x2:
+		did = 2.0f;
+		break;
+	case 0x3:
+		did = 3.0f;
+		break;
+	case 0x4:
+		did = 4.0f;
+		break;
+	case 0x5:
+		did = 6.0f;
+		break;
+	case 0x6:
+		did = 8.0f;
+		break;
+	case 0x7:
+		did = 12.0f;
+		break;
+	case 0x8:
+		did = 16.0f;
+		break;
 	}
 
-  fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / did));
+	fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / did));
 
 	/* Finaly, we need the clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
-	if(((dramchr >> 14) & 0x1) == 1)
-	{
+	if (((dramchr >> 14) & 0x1) == 1) {
 		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);
 	}
 
 	temp2 = (dramchr & 0x1F);
 
 	switch (temp2) {
-		default:
-		case 0x06:
-			dramratio = 4.0f;
-			break;
-		case 0x0A:
-			dramratio = 16.0f / 3.0f;
-			break;
-		case 0x0E:
-			dramratio = 20.0f / 3.0f;
-			break;
-		case 0x12:
-			dramratio = 8.0f;
-			break;
-		case 0x16:
-			dramratio = 28.0f / 3.0f;
-			break;
+	default:
+	case 0x06:
+		dramratio = 4.0f;
+		break;
+	case 0x0A:
+		dramratio = 16.0f / 3.0f;
+		break;
+	case 0x0E:
+		dramratio = 20.0f / 3.0f;
+		break;
+	case 0x12:
+		dramratio = 8.0f;
+		break;
+	case 0x16:
+		dramratio = 28.0f / 3.0f;
+		break;
 	}
 
 	dramclock = fsb * dramratio;
 
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
 static void poll_fsb_k16(void)
 {
-
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
 
@@ -1683,137 +1641,132 @@
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
 	switch (dramchr & 0x1F) {
-		default:
-		case 0x04: /* 333 */
-			dramratio = 10.0f / 3.0f;
-			break;
-		case 0x06: /* 400 */
-			dramratio = 4.0f;
-			break;
-		case 0x0A: /* 533 */
-			dramratio = 16.0f / 3.0f;
-			break;
-		case 0x0E: /* 667 */
-			dramratio = 20.0f / 3.0f;
-			break;
-		case 0x12: /* 800 */
-			dramratio = 8.0f;
-			break;
-		case 0x16: /* 933 */
-			dramratio = 28.0f / 3.0f;
-			break;
-		case 0x19: /* 1050 */
-			dramratio = 21.0f / 2.0f;
-			break;
-		case 0x1A: /* 1066 */
-			dramratio = 32.0f / 3.0f;
-			break;
+	default:
+	case 0x04:         /* 333 */
+		dramratio = 10.0f / 3.0f;
+		break;
+	case 0x06:         /* 400 */
+		dramratio = 4.0f;
+		break;
+	case 0x0A:         /* 533 */
+		dramratio = 16.0f / 3.0f;
+		break;
+	case 0x0E:         /* 667 */
+		dramratio = 20.0f / 3.0f;
+		break;
+	case 0x12:         /* 800 */
+		dramratio = 8.0f;
+		break;
+	case 0x16:         /* 933 */
+		dramratio = 28.0f / 3.0f;
+		break;
+	case 0x19:         /* 1050 */
+		dramratio = 21.0f / 2.0f;
+		break;
+	case 0x1A:         /* 1066 */
+		dramratio = 32.0f / 3.0f;
+		break;
 	}
 
 	dramclock = fsb * dramratio;
 
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_k15(void) {
-
+static void poll_fsb_k15(void)
+{
 	unsigned long temp2;
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
-	unsigned int mcgsrl,mcgsth, fid, did;
+	unsigned int mcgsrl, mcgsth, fid, did;
 
 	// Get current FID & DID
- 	rdmsr(0xc0010071, mcgsrl, mcgsth);
- 	fid = mcgsrl & 0x3F;
- 	did = (mcgsrl >> 6) & 0x7;
+	rdmsr(0xc0010071, mcgsrl, mcgsth);
+	fid = mcgsrl & 0x3F;
+	did = (mcgsrl >> 6) & 0x7;
 
-  fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / (2^did)) / 2);
+	fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / (2^did)) / 2);
 
 	/* Finaly, we need the clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
-	if(((dramchr >> 14) & 0x1) == 1)
-	{
+	if (((dramchr >> 14) & 0x1) == 1) {
 		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);
 	}
 
 	temp2 = (dramchr & 0x1F);
 
 	switch (temp2) {
-		case 0x04:
-			dramratio = 10.0f / 3.0f;
-			break;
-		default:
-		case 0x06:
-			dramratio = 4.0f;
-			break;
-		case 0x0A:
-			dramratio = 16.0f / 3.0f;
-			break;
-		case 0x0E:
-			dramratio = 20.0f / 3.0f;
-			break;
-		case 0x12:
-			dramratio = 8.0f;
-			break;
-		case 0x16:
-			dramratio = 28.0f / 3.0f;
-			break;
-		case 0x1A:
-			dramratio = 32.0f / 3.0f;
-			break;
-		case 0x1F:
-			dramratio = 36.0f / 3.0f;
-			break;
+	case 0x04:
+		dramratio = 10.0f / 3.0f;
+		break;
+	default:
+	case 0x06:
+		dramratio = 4.0f;
+		break;
+	case 0x0A:
+		dramratio = 16.0f / 3.0f;
+		break;
+	case 0x0E:
+		dramratio = 20.0f / 3.0f;
+		break;
+	case 0x12:
+		dramratio = 8.0f;
+		break;
+	case 0x16:
+		dramratio = 28.0f / 3.0f;
+		break;
+	case 0x1A:
+		dramratio = 32.0f / 3.0f;
+		break;
+	case 0x1F:
+		dramratio = 36.0f / 3.0f;
+		break;
 	}
 
 	dramclock = fsb * dramratio;
 
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
 static void poll_fsb_k14(void)
 {
-
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
 
 	// FIXME: Unable to find a real way to detect multiplier.
-  fsb = 100.0f;
+	fsb = 100.0f;
 
 	/* Clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
 	switch (dramchr & 0x1F) {
-		default:
-		case 0x06:
-			dramratio = 4.0f;
-			break;
-		case 0x0A:
-			dramratio = 16.0f / 3.0f;
-			break;
-		case 0x0E:
-			dramratio = 20.0f / 3.0f;
-			break;
-		case 0x12:
-			dramratio = 8.0f;
-			break;
+	default:
+	case 0x06:
+		dramratio = 4.0f;
+		break;
+	case 0x0A:
+		dramratio = 16.0f / 3.0f;
+		break;
+	case 0x0E:
+		dramratio = 20.0f / 3.0f;
+		break;
+	case 0x12:
+		dramratio = 8.0f;
+		break;
 	}
 
 	dramclock = fsb * dramratio;
 
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
 
-static void poll_fsb_i925(void) {
-
+static void poll_fsb_i925(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, mchcfg2, dev0, drc, idetect;
 	float coef = getP4PMmultiplier();
@@ -1845,17 +1798,17 @@
 			if (mchcfg2 == 2) { dramratio = 0.75; } else { dramratio = 1; }
 		} else {
 			switch (mchcfg2) {
-				case 1:
-					dramratio = 0.66667;
-					break;
-				case 2:
-					if (idetect != 0x2590) { dramratio = 1; } else { dramratio = 1.5; }
-					break;
-				case 3:
-						// Checking for FSB533 Mode & Alviso
-						if ((mchcfg & 1) == 0) { dramratio = 1.33334; }
-						else if (idetect == 0x2590) { dramratio = 2; }
-						else { dramratio = 1.5; }
+			case 1:
+				dramratio = 0.66667;
+				break;
+			case 2:
+				if (idetect != 0x2590) { dramratio = 1; } else { dramratio = 1.5; }
+				break;
+			case 3:
+				// Checking for FSB533 Mode & Alviso
+				if ((mchcfg & 1) == 0) { dramratio = 1.33334; }
+				else if (idetect == 0x2590) { dramratio = 2; }
+				else { dramratio = 1.5; }
 			}
 		}
 	}
@@ -1865,11 +1818,10 @@
 
 
 	print_cpu_line(dramclock, fsb, ddr_type);
-
 }
 
-static void poll_fsb_i945(void) {
-
+static void poll_fsb_i945(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, dev0;
 	float coef = getP4PMmultiplier();
@@ -1883,10 +1835,10 @@
 	dramratio = 1;
 
 	switch ((mchcfg >> 4)&7) {
-		case 1:	dramratio = 1.0; break;
-		case 2:	dramratio = 1.33334; break;
-		case 3:	dramratio = 1.66667; break;
-		case 4:	dramratio = 2.0; break;
+	case 1: dramratio = 1.0; break;
+	case 2: dramratio = 1.33334; break;
+	case 3: dramratio = 1.66667; break;
+	case 4: dramratio = 2.0; break;
 	}
 
 	// Compute RAM Frequency
@@ -1896,11 +1848,10 @@
 
 	// Print
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
-static void poll_fsb_i945gme(void) {
-
+static void poll_fsb_i945gme(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, dev0, fsb_mch;
 	float coef = getP4PMmultiplier();
@@ -1914,36 +1865,36 @@
 	dramratio = 1;
 
 	switch (mchcfg & 7) {
-		case 0: fsb_mch = 400; break;
-		default:
-		case 1: fsb_mch = 533; break;
-		case 2:	fsb_mch = 667; break;
+	case 0: fsb_mch = 400; break;
+	default:
+	case 1: fsb_mch = 533; break;
+	case 2: fsb_mch = 667; break;
 	}
 
 
 	switch (fsb_mch) {
 	case 400:
 		switch ((mchcfg >> 4)&7) {
-			case 2:	dramratio = 1.0f; break;
-			case 3:	dramratio = 4.0f/3.0f; break;
-			case 4:	dramratio = 5.0f/3.0f; break;
+		case 2: dramratio = 1.0f; break;
+		case 3: dramratio = 4.0f/3.0f; break;
+		case 4: dramratio = 5.0f/3.0f; break;
 		}
 		break;
 
 	default:
 	case 533:
 		switch ((mchcfg >> 4)&7) {
-			case 2:	dramratio = 3.0f/4.0f; break;
-			case 3:	dramratio = 1.0f; break;
-			case 4:	dramratio = 5.0f/4.0f; break;
+		case 2: dramratio = 3.0f/4.0f; break;
+		case 3: dramratio = 1.0f; break;
+		case 4: dramratio = 5.0f/4.0f; break;
 		}
 		break;
 
 	case 667:
 		switch ((mchcfg >> 4)&7) {
-			case 2:	dramratio = 3.0f/5.0f; break;
-			case 3:	dramratio = 4.0f/5.0f; break;
-			case 4:	dramratio = 1.0f; break;
+		case 2: dramratio = 3.0f/5.0f; break;
+		case 3: dramratio = 4.0f/5.0f; break;
+		case 4: dramratio = 1.0f; break;
 		}
 		break;
 	}
@@ -1953,12 +1904,11 @@
 	dramclock = fsb * dramratio * 2;
 
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
 
-static void poll_fsb_i975(void) {
-
+static void poll_fsb_i975(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, dev0, fsb_mch;
 	float coef = getP4PMmultiplier();
@@ -1972,38 +1922,38 @@
 	dramratio = 1;
 
 	switch (mchcfg & 7) {
-		case 1: fsb_mch = 533; break;
-		case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;
-		default: fsb_mch = 1066; break;
+	case 1: fsb_mch = 533; break;
+	case 2: fsb_mch = 800; break;
+	case 3: fsb_mch = 667; break;
+	default: fsb_mch = 1066; break;
 	}
 
 
 	switch (fsb_mch) {
 	case 533:
 		switch ((mchcfg >> 4)&7) {
-			case 0:	dramratio = 1.25; break;
-			case 1:	dramratio = 1.5; break;
-			case 2:	dramratio = 2.0; break;
+		case 0: dramratio = 1.25; break;
+		case 1: dramratio = 1.5; break;
+		case 2: dramratio = 2.0; break;
 		}
 		break;
 
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 1.0; break;
-			case 2:	dramratio = 1.33334; break;
-			case 3:	dramratio = 1.66667; break;
-			case 4:	dramratio = 2.0; break;
+		case 1: dramratio = 1.0; break;
+		case 2: dramratio = 1.33334; break;
+		case 3: dramratio = 1.66667; break;
+		case 4: dramratio = 2.0; break;
 		}
 		break;
 
 	case 1066:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 0.75; break;
-			case 2:	dramratio = 1.0; break;
-			case 3:	dramratio = 1.25; break;
-			case 4:	dramratio = 1.5; break;
+		case 1: dramratio = 0.75; break;
+		case 2: dramratio = 1.0; break;
+		case 3: dramratio = 1.25; break;
+		case 4: dramratio = 1.5; break;
 		}
 		break;
 	}
@@ -2013,11 +1963,10 @@
 	dramclock = fsb * dramratio;
 
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
-static void poll_fsb_i965(void) {
-
+static void poll_fsb_i965(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, dev0, fsb_mch;
 	float coef = getP4PMmultiplier();
@@ -2031,65 +1980,64 @@
 	dramratio = 1;
 
 	switch (mchcfg & 7) {
-		case 0: fsb_mch = 1066; break;
-		case 1: fsb_mch = 533; break;
-		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;
-		case 4: fsb_mch = 1333; break;
-		case 6: fsb_mch = 1600; break;
+	case 0: fsb_mch = 1066; break;
+	case 1: fsb_mch = 533; break;
+	default: case 2: fsb_mch = 800; break;
+	case 3: fsb_mch = 667; break;
+	case 4: fsb_mch = 1333; break;
+	case 6: fsb_mch = 1600; break;
 	}
 
 
 	switch (fsb_mch) {
 	case 533:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 2.0; break;
-			case 2:	dramratio = 2.5; break;
-			case 3:	dramratio = 3.0; break;
+		case 1: dramratio = 2.0; break;
+		case 2: dramratio = 2.5; break;
+		case 3: dramratio = 3.0; break;
 		}
 		break;
 
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
-			case 0:	dramratio = 1.0; break;
-			case 1:	dramratio = 5.0f/4.0f; break;
-			case 2:	dramratio = 5.0f/3.0f; break;
-			case 3:	dramratio = 2.0f; break;
-			case 4:	dramratio = 8.0f/3.0f; break;
-			case 5:	dramratio = 10.0f/3.0f; break;
+		case 0: dramratio = 1.0; break;
+		case 1: dramratio = 5.0f/4.0f; break;
+		case 2: dramratio = 5.0f/3.0f; break;
+		case 3: dramratio = 2.0f; break;
+		case 4: dramratio = 8.0f/3.0f; break;
+		case 5: dramratio = 10.0f/3.0f; break;
 		}
 		break;
 
 	case 1066:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 1.0f; break;
-			case 2:	dramratio = 5.0f/4.0f; break;
-			case 3:	dramratio = 3.0f/2.0f; break;
-			case 4:	dramratio = 2.0f; break;
-			case 5:	dramratio = 5.0f/2.0f; break;
+		case 1: dramratio = 1.0f; break;
+		case 2: dramratio = 5.0f/4.0f; break;
+		case 3: dramratio = 3.0f/2.0f; break;
+		case 4: dramratio = 2.0f; break;
+		case 5: dramratio = 5.0f/2.0f; break;
 		}
 		break;
 
 	case 1333:
 		switch ((mchcfg >> 4)&7) {
-			case 2:	dramratio = 1.0f; break;
-			case 3:	dramratio = 6.0f/5.0f; break;
-			case 4:	dramratio = 8.0f/5.0f; break;
-			case 5:	dramratio = 2.0f; break;
+		case 2: dramratio = 1.0f; break;
+		case 3: dramratio = 6.0f/5.0f; break;
+		case 4: dramratio = 8.0f/5.0f; break;
+		case 5: dramratio = 2.0f; break;
 		}
 		break;
 
 	case 1600:
 		switch ((mchcfg >> 4)&7) {
-			case 3:	dramratio = 1.0f; break;
-			case 4:	dramratio = 4.0f/3.0f; break;
-			case 5:	dramratio = 3.0f/2.0f; break;
-			case 6:	dramratio = 2.0f; break;
+		case 3: dramratio = 1.0f; break;
+		case 4: dramratio = 4.0f/3.0f; break;
+		case 5: dramratio = 3.0f/2.0f; break;
+		case 6: dramratio = 2.0f; break;
 		}
 		break;
-
-}
+	}
 
 	// Compute RAM Frequency
 	fsb = ((extclock / 1000) / coef);
@@ -2097,13 +2045,12 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
-static void poll_fsb_p35(void) {
-
+static void poll_fsb_p35(void)
+{
 	double dramclock, dramratio, fsb;
-	unsigned long mchcfg, dev0, fsb_mch, Device_ID, Memory_Check,	c0ckectrl, offset;
+	unsigned long mchcfg, dev0, fsb_mch, Device_ID, Memory_Check, c0ckectrl, offset;
 	float coef = getP4PMmultiplier();
 	long *ptr;
 	int ram_type;
@@ -2120,75 +2067,74 @@
 
 
 	// If DIMM 0 not populated, check DIMM 1
-	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
+	((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);
 
 	ptr=(long*)(dev0+0xC00);
 	mchcfg = *ptr & 0xFFFF;
 	dramratio = 1;
 
 	switch (mchcfg & 7) {
-		case 0: fsb_mch = 1066; break;
-		case 1: fsb_mch = 533; break;
-		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;
-		case 4: fsb_mch = 1333; break;
-		case 6: fsb_mch = 1600; break;
+	case 0: fsb_mch = 1066; break;
+	case 1: fsb_mch = 533; break;
+	default: case 2: fsb_mch = 800; break;
+	case 3: fsb_mch = 667; break;
+	case 4: fsb_mch = 1333; break;
+	case 6: fsb_mch = 1600; break;
 	}
 
 
 	switch (fsb_mch) {
 	case 533:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 2.0; break;
-			case 2:	dramratio = 2.5; break;
-			case 3:	dramratio = 3.0; break;
+		case 1: dramratio = 2.0; break;
+		case 2: dramratio = 2.5; break;
+		case 3: dramratio = 3.0; break;
 		}
 		break;
 
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
-			case 0:	dramratio = 1.0; break;
-			case 1:	dramratio = 5.0f/4.0f; break;
-			case 2:	dramratio = 5.0f/3.0f; break;
-			case 3:	dramratio = 2.0; break;
-			case 4:	dramratio = 8.0f/3.0f; break;
-			case 5:	dramratio = 10.0f/3.0f; break;
+		case 0: dramratio = 1.0; break;
+		case 1: dramratio = 5.0f/4.0f; break;
+		case 2: dramratio = 5.0f/3.0f; break;
+		case 3: dramratio = 2.0; break;
+		case 4: dramratio = 8.0f/3.0f; break;
+		case 5: dramratio = 10.0f/3.0f; break;
 		}
 		break;
 
 	case 1066:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 1.0f; break;
-			case 2:	dramratio = 5.0f/4.0f; break;
-			case 3:	dramratio = 3.0f/2.0f; break;
-			case 4:	dramratio = 2.0f; break;
-			case 5:	dramratio = 5.0f/2.0f; break;
+		case 1: dramratio = 1.0f; break;
+		case 2: dramratio = 5.0f/4.0f; break;
+		case 3: dramratio = 3.0f/2.0f; break;
+		case 4: dramratio = 2.0f; break;
+		case 5: dramratio = 5.0f/2.0f; break;
 		}
 		break;
 
 	case 1333:
 		switch ((mchcfg >> 4)&7) {
-			case 2:	dramratio = 1.0f; break;
-			case 3:	dramratio = 6.0f/5.0f; break;
-			case 4:	dramratio = 8.0f/5.0f; break;
-			case 5:	dramratio = 2.0f; break;
+		case 2: dramratio = 1.0f; break;
+		case 3: dramratio = 6.0f/5.0f; break;
+		case 4: dramratio = 8.0f/5.0f; break;
+		case 5: dramratio = 2.0f; break;
 		}
 		break;
 
 	case 1600:
 		switch ((mchcfg >> 4)&7) {
-			case 3:	dramratio = 1.0f; break;
-			case 4:	dramratio = 4.0f/3.0f; break;
-			case 5:	dramratio = 3.0f/2.0f; break;
-			case 6:	dramratio = 2.0f; break;
+		case 3: dramratio = 1.0f; break;
+		case 4: dramratio = 4.0f/3.0f; break;
+		case 5: dramratio = 3.0f/2.0f; break;
+		case 6: dramratio = 2.0f; break;
 		}
 		break;
-
 	}
 
 	// On P45, check 1A8
-	if(Device_ID > 0x2E00 && imc_type != 8) {
+	if (Device_ID > 0x2E00 && imc_type != 8) {
 		ptr = (long*)(dev0+offset+0x1A8);
 		Memory_Check = *ptr & 0xFFFFFFFF;
 		Memory_Check >>= 2;
@@ -2217,11 +2163,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, ram_type);
-
 }
 
-static void poll_fsb_im965(void) {
-
+static void poll_fsb_im965(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, dev0, fsb_mch;
 	float coef = getP4PMmultiplier();
@@ -2235,48 +2180,48 @@
 	dramratio = 1;
 
 	switch (mchcfg & 7) {
-		case 1: fsb_mch = 533; break;
-		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;
-		case 6:	fsb_mch = 1066; break;
+	case 1: fsb_mch = 533; break;
+	default: case 2: fsb_mch = 800; break;
+	case 3: fsb_mch = 667; break;
+	case 6: fsb_mch = 1066; break;
 	}
 
 
 	switch (fsb_mch) {
 	case 533:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 5.0f/4.0f; break;
-			case 2:	dramratio = 3.0f/2.0f; break;
-			case 3:	dramratio = 2.0f; break;
+		case 1: dramratio = 5.0f/4.0f; break;
+		case 2: dramratio = 3.0f/2.0f; break;
+		case 3: dramratio = 2.0f; break;
 		}
 		break;
 
 	case 667:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 1.0f; break;
-			case 2:	dramratio = 6.0f/5.0f; break;
-			case 3:	dramratio = 8.0f/5.0f; break;
-			case 4:	dramratio = 2.0f; break;
-			case 5:	dramratio = 12.0f/5.0f; break;
+		case 1: dramratio = 1.0f; break;
+		case 2: dramratio = 6.0f/5.0f; break;
+		case 3: dramratio = 8.0f/5.0f; break;
+		case 4: dramratio = 2.0f; break;
+		case 5: dramratio = 12.0f/5.0f; break;
 		}
 		break;
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
-			case 1:	dramratio = 5.0f/6.0f; break;
-			case 2:	dramratio = 1.0f; break;
-			case 3:	dramratio = 4.0f/3.0f; break;
-			case 4:	dramratio = 5.0f/3.0f; break;
-			case 5:	dramratio = 2.0f; break;
+		case 1: dramratio = 5.0f/6.0f; break;
+		case 2: dramratio = 1.0f; break;
+		case 3: dramratio = 4.0f/3.0f; break;
+		case 4: dramratio = 5.0f/3.0f; break;
+		case 5: dramratio = 2.0f; break;
 		}
 		break;
 	case 1066:
 		switch ((mchcfg >> 4)&7) {
-			case 5:	dramratio = 3.0f/2.0f; break;
-			case 6:	dramratio = 2.0f; break;
+		case 5: dramratio = 3.0f/2.0f; break;
+		case 6: dramratio = 2.0f; break;
 		}
 		break;
-}
+	}
 
 	// Compute RAM Frequency
 	fsb = ((extclock / 1000) / coef);
@@ -2284,12 +2229,11 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
 
-static void poll_fsb_5400(void) {
-
+static void poll_fsb_5400(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long ambase_low, ambase_high, ddrfrq;
 	float coef = getP4PMmultiplier();
@@ -2300,23 +2244,23 @@
 	pci_conf_read( 0, 16, 0, 0x4C, 4, &ambase_high);
 	ambase_high &= 0xFF;
 	pci_conf_read( 0, 16, 1, 0x56, 1, &ddrfrq);
-  ddrfrq &= 7;
-  dramratio = 1;
+	ddrfrq &= 7;
+	dramratio = 1;
 
 	switch (ddrfrq) {
-			case 0:
-			case 1:
-			case 4:
-				dramratio = 1.0;
-				break;
-			case 2:
-				dramratio = 5.0f/4.0f;
-				break;
-			case 3:
-			case 7:
-				dramratio = 4.0f/5.0f;
-				break;
-		}
+	case 0:
+	case 1:
+	case 4:
+		dramratio = 1.0;
+		break;
+	case 2:
+		dramratio = 5.0f/4.0f;
+		break;
+	case 3:
+	case 7:
+		dramratio = 4.0f/5.0f;
+		break;
+	}
 
 
 	// Compute RAM Frequency
@@ -2325,12 +2269,11 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
 
-static void poll_fsb_nf4ie(void) {
-
+static void poll_fsb_nf4ie(void)
+{
 	double dramclock, dramratio, fsb;
 	float mratio, nratio;
 	unsigned long reg74, reg60;
@@ -2347,7 +2290,7 @@
 	if (nratio == 0) { nratio = 16; }
 
 	// Check if synchro or pseudo-synchro mode
-	if((reg60 >> 22) & 1) {
+	if ((reg60 >> 22) & 1) {
 		dramratio = 1;
 	} else {
 		dramratio = nratio / mratio;
@@ -2359,11 +2302,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 2);
-
 }
 
-static void poll_fsb_i875(void) {
-
+static void poll_fsb_i875(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mchcfg, smfs;
 	float coef = getP4PMmultiplier();
@@ -2395,19 +2337,18 @@
 	print_cpu_line(dramclock, fsb, 2);
 }
 
-static void poll_fsb_p4(void) {
-
+static void poll_fsb_p4(void)
+{
 	ulong fsb, idetect;
 	float coef = getP4PMmultiplier();
 	char *name;
-	int col,temp;
+	int col, temp;
 
 	fsb = ((extclock /1000) / coef);
 
 	/* For synchro only chipsets */
 	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
-	if (idetect == 0x2540 || idetect == 0x254C)
-	{
+	if (idetect == 0x2540 || idetect == 0x254C) {
 		print_cpu_line(fsb, fsb, 1);
 	} else {
 		/* Print the controller name */
@@ -2419,25 +2360,23 @@
 		cprint(LINE_CPU, col, name);
 		/* Now figure out how much I just printed */
 		temp = 20;
-		while(name[temp - 20] != '\0') {
+		while (name[temp - 20] != '\0') {
 			col++;
 			temp++;
 		}
 
-		if(temp < 36){
+		if (temp < 36) {
 			cprint(LINE_CPU, col +1, "- FSB : ");
 			col += 9;
-			dprint(LINE_CPU, col, fsb, 3,0);
+			dprint(LINE_CPU, col, fsb, 3, 0);
 			col += 3;
 		}
-
 	}
 }
 
-static void poll_fsb_i855(void) {
-
-
-	double dramclock, dramratio, fsb ;
+static void poll_fsb_i855(void)
+{
+	double dramclock, dramratio, fsb;
 	unsigned int msr_lo, msr_hi;
 	ulong mchcfg, idetect;
 	int coef;
@@ -2465,15 +2404,14 @@
 		pci_conf_read( 0, 0, 3, 0xC0, 2, &mchcfg);
 		mchcfg = mchcfg & 0x7;
 
-		if (mchcfg == 1 || mchcfg == 2 || mchcfg == 4 || mchcfg == 5) {	dramratio = 1; }
+		if (mchcfg == 1 || mchcfg == 2 || mchcfg == 4 || mchcfg == 5) { dramratio = 1; }
 		if (mchcfg == 0 || mchcfg == 3) { dramratio = 1.333333333; }
 		if (mchcfg == 6) { dramratio = 1.25; }
 		if (mchcfg == 7) { dramratio = 1.666666667; }
-
 	} else {
 		pci_conf_read( 0, 0, 0, 0xC6, 2, &mchcfg);
-		if (((mchcfg >> 10)&3) == 0) { dramratio = 1; }
-		else if (((mchcfg >> 10)&3) == 1) { dramratio = 1.666667; }
+		if (((mchcfg >> 10) & 3) == 0) { dramratio = 1; }
+		else if (((mchcfg >> 10) & 3) == 1) { dramratio = 1.666667; }
 		else { dramratio = 1.333333333; }
 	}
 
@@ -2482,11 +2420,10 @@
 
 	/* ...and print */
 	print_cpu_line(dramclock, fsb, 1);
-
 }
 
-static void poll_fsb_amd32(void) {
-
+static void poll_fsb_amd32(void)
+{
 	unsigned int mcgsrl;
 	unsigned int mcgsth;
 	unsigned long temp;
@@ -2499,10 +2436,10 @@
 	rdmsr(0x0c0010015, mcgsrl, mcgsth);
 	temp = (mcgsrl >> 24)&0x0F;
 
-	if ((mcgsrl >> 19)&1) { coef2 = athloncoef2[temp]; }
+	if ((mcgsrl >> 19) & 1) { coef2 = athloncoef2[temp]; }
 	else { coef2 = athloncoef[temp]; }
 
-	if (coef2 == 0) { coef2 = 1; };
+	if (coef2 == 0) { coef2 = 1; }
 
 	/* Compute the final FSB Clock */
 	dramclock = (extclock /1000) / coef2;
@@ -2516,23 +2453,21 @@
 	cprint(LINE_CPU, col, name);
 	/* Now figure out how much I just printed */
 	temp = 20;
-	while(name[temp - 20] != '\0') {
+	while (name[temp - 20] != '\0') {
 		col++;
 		temp++;
 	}
 
-	if(temp < 36){
+	if (temp < 36) {
 		cprint(LINE_CPU, col +1, "- FSB : ");
 		col += 9;
-		dprint(LINE_CPU, col, dramclock, 3,0);
+		dprint(LINE_CPU, col, dramclock, 3, 0);
 		col += 3;
 	}
-
-
 }
 
-static void poll_fsb_nf2(void) {
-
+static void poll_fsb_nf2(void)
+{
 	unsigned int mcgsrl;
 	unsigned int mcgsth;
 	unsigned long temp, mempll;
@@ -2545,7 +2480,7 @@
 	rdmsr(0x0c0010015, mcgsrl, mcgsth);
 	temp = (mcgsrl >> 24)&0x0F;
 
-	if ((mcgsrl >> 19)&1) { coef = athloncoef2[temp]; }
+	if ((mcgsrl >> 19) & 1) { coef = athloncoef2[temp]; }
 	else { coef = athloncoef[temp]; }
 
 	/* Get the coef (COEF = N/M) - Here is for Crush17 */
@@ -2554,7 +2489,7 @@
 	mem_n = ((mempll >> 4) & 0x0F);
 
 	/* If something goes wrong, the chipset is probably a Crush18 */
-	if ( mem_m == 0 || mem_n == 0 ) {
+	if (mem_m == 0 || mem_n == 0) {
 		pci_conf_read(0, 0, 3, 0x7C, 4, &mempll);
 		mem_m = (mempll&0x0F);
 		mem_n = ((mempll >> 4) & 0x0F);
@@ -2566,11 +2501,10 @@
 
 	/* ...and print */
 	print_cpu_line(dramclock, fsb, 1);
-
 }
 
-static void poll_fsb_us15w(void) {
-
+static void poll_fsb_us15w(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long msr;
 
@@ -2619,11 +2553,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 1);
-
 }
 
-static void poll_fsb_nhm(void) {
-
+static void poll_fsb_nhm(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mc_dimm_clk_ratio;
 	float coef = getNHMmultiplier();
@@ -2663,11 +2596,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_nhm32(void) {
-
+static void poll_fsb_nhm32(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long mc_dimm_clk_ratio;
 	float coef = getNHMmultiplier();
@@ -2706,11 +2638,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_wmr(void) {
-
+static void poll_fsb_wmr(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long dev0;
 	float coef = getNHMmultiplier();
@@ -2731,11 +2662,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_snb(void) {
-
+static void poll_fsb_snb(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long dev0;
 	float coef = getSNBmultiplier();
@@ -2757,11 +2687,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_ivb(void) {
-
+static void poll_fsb_ivb(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long dev0, mchcfg;
 	float coef = getSNBmultiplier();
@@ -2777,14 +2706,13 @@
 	dramratio = 1;
 
 	/* Get the clock ratio */
-	switch((mchcfg >> 8) & 0x01)
-	{
-		case 0x0:
-			dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f);
-			break;
-		case 0x1:
-			dramratio = (float)(*ptr & 0x1F) * (100.0f / 100.0f);
-			break;
+	switch ((mchcfg >> 8) & 0x01) {
+	case 0x0:
+		dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f);
+		break;
+	case 0x1:
+		dramratio = (float)(*ptr & 0x1F) * (100.0f / 100.0f);
+		break;
 	}
 
 	// Compute RAM Frequency
@@ -2792,11 +2720,10 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
 }
 
-static void poll_fsb_snbe(void) {
-
+static void poll_fsb_snbe(void)
+{
 	double dramclock, dramratio, fsb;
 	unsigned long dev0;
 	float coef = getSNBmultiplier();
@@ -2815,17 +2742,13 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-
-
-
 }
 
 /* ------------------ Here the code for Timings detection ------------------ */
 /* ------------------------------------------------------------------------- */
 
-static void poll_timings_nf4ie(void) {
-
-
+static void poll_timings_nf4ie(void)
+{
 	ulong regd0, reg8c, reg9c, reg80;
 	int cas, rcd, rp, ras, chan;
 
@@ -2849,8 +2772,8 @@
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_i875(void) {
-
+static void poll_timings_i875(void)
+{
 	ulong dev6;
 	ulong temp;
 	float cas;
@@ -2867,15 +2790,21 @@
 	ptr=(long*)(dev6+0x60);
 	// CAS Latency (tCAS)
 	temp = ((*ptr >> 5)& 0x3);
-	if (temp == 0x0) { cas = 2.5; } else if (temp == 0x1) { cas = 2; } else { cas = 3; }
+	if (temp == 0x0) { cas = 2.5; }
+	else if (temp == 0x1) { cas = 2; }
+	else { cas = 3; }
 
 	// RAS-To-CAS (tRCD)
 	temp = ((*ptr >> 2)& 0x3);
-	if (temp == 0x0) { rcd = 4; } else if (temp == 0x1) { rcd = 3; } else { rcd = 2; }
+	if (temp == 0x0) { rcd = 4; }
+	else if (temp == 0x1) { rcd = 3; }
+	else { rcd = 2; }
 
 	// RAS Precharge (tRP)
 	temp = (*ptr&0x3);
-	if (temp == 0x0) { rp = 4; } else if (temp == 0x1) { rp = 3; } else { rp = 2; }
+	if (temp == 0x0) { rp = 4; }
+	else if (temp == 0x1) { rp = 3; }
+	else { rp = 2; }
 
 	// RAS Active to precharge (tRAS)
 	temp = ((*ptr >> 7)& 0x7);
@@ -2890,11 +2819,11 @@
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_i925(void) {
-
+static void poll_timings_i925(void)
+{
 	// Thanks for CDH optis
 	float cas;
-	int rcd,rp,ras,chan;
+	int rcd, rp, ras, chan;
 	ulong dev0, drt, drc, dcc, idetect, temp;
 	long *ptr;
 
@@ -2918,17 +2847,17 @@
 	// CAS Latency (tCAS)
 	temp = ((drt >> 8)& 0x3);
 
-	if ((drc & 3) == 2){
+	if ((drc & 3) == 2) {
 		// Timings DDR-II
 		if      (temp == 0x0) { cas = 5; }
 		else if (temp == 0x1) { cas = 4; }
 		else if (temp == 0x2) { cas = 3; }
-		else		      { cas = 6; }
+		else                  { cas = 6; }
 	} else {
 		// Timings DDR-I
 		if      (temp == 0x0) { cas = 3; }
-		else if (temp == 0x1) { cas = 2.5f;}
-		else		      { cas = 2; }
+		else if (temp == 0x1) { cas = 2.5f; }
+		else                  { cas = 2; }
 	}
 
 	// RAS-To-CAS (tRCD)
@@ -2948,19 +2877,18 @@
 	temp = (dcc&0x3);
 	if      (temp == 1) { chan = 2; }
 	else if (temp == 2) { chan = 2; }
-	else		    { chan = 1; }
+	else                { chan = 1; }
 
 	print_ram_line(cas, rcd, rp, ras, chan);
-
 }
 
-static void poll_timings_i965(void) {
-
+static void poll_timings_i965(void)
+{
 	// Thanks for CDH optis
 	ulong dev0, c0ckectrl, c1ckectrl, offset;
 	ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register;
 	long *ptr;
-	int rcd,rp,ras,chan;
+	int rcd, rp, ras, chan;
 	float cas;
 
 	//Now, read MMR Base Address
@@ -2974,7 +2902,7 @@
 	c1ckectrl = *ptr & 0xFFFFFFFF;
 
 	// If DIMM 0 not populated, check DIMM 1
-	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
+	((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x29C);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
@@ -3003,20 +2931,20 @@
 
 	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
 		chan = 2;
-	}	else {
+	} else {
 		chan = 1;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_im965(void) {
-
+static void poll_timings_im965(void)
+{
 	// Thanks for CDH optis
 	ulong dev0, c0ckectrl, c1ckectrl, offset;
 	ulong ODT_Control_Register, Precharge_Register;
 	long *ptr;
-	int rcd,rp,ras,chan;
+	int rcd, rp, ras, chan;
 	float cas;
 
 	//Now, read MMR Base Address
@@ -3030,7 +2958,7 @@
 	c1ckectrl = *ptr & 0xFFFFFFFF;
 
 	// If DIMM 0 not populated, check DIMM 1
-	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x100);
+	((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);
 
 	ptr = (long*)(dev0+offset+0x121C);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
@@ -3053,14 +2981,14 @@
 
 	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
 		chan = 2;
-	}	else {
+	} else {
 		chan = 1;
 	}
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_p35(void) {
-
+static void poll_timings_p35(void)
+{
 	// Thanks for CDH optis
 	float cas;
 	int rcd, rp, ras, chan;
@@ -3082,7 +3010,7 @@
 	c1ckectrl = *ptr & 0xFFFFFFFF;
 
 	// If DIMM 0 not populated, check DIMM 1
-	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
+	((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x265);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
@@ -3098,7 +3026,7 @@
 
 
 	// CAS Latency (tCAS)
-	if(Device_ID > 0x2E00 && imc_type != 8) {
+	if (Device_ID > 0x2E00 && imc_type != 8) {
 		cas = ((ODT_Control_Register >> 8)& 0x3F) - 6.0f;
 	} else {
 		cas = ((ODT_Control_Register >> 8)& 0x3F) - 9.0f;
@@ -3115,14 +3043,14 @@
 
 	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
 		chan = 2;
-	}	else {
+	} else {
 		chan = 1;
 	}
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_wmr(void) {
-
+static void poll_timings_wmr(void)
+{
 	float cas;
 	int rcd, rp, ras, chan;
 	ulong dev0, c0ckectrl, c1ckectrl, offset;
@@ -3140,7 +3068,7 @@
 	c1ckectrl = *ptr & 0xFFFFFFFF;
 
 	// If DIMM 0 not populated, check DIMM 1
-	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
+	((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x265);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
@@ -3158,7 +3086,7 @@
 	MRC_Register = *ptr & 0xFFFFFFFF;
 
 	// CAS Latency (tCAS)
-	if(MRC_Register & 0xF) {
+	if (MRC_Register & 0xF) {
 		cas = (MRC_Register & 0xF) + 3.0f;
 	} else {
 		cas = ((ODT_Control_Register >> 8)& 0x3F) - 5.0f;
@@ -3175,16 +3103,15 @@
 
 	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
 		chan = 2;
-	}	else {
+	} else {
 		chan = 1;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
-
 }
 
-static void poll_timings_snb(void) {
-
+static void poll_timings_snb(void)
+{
 	float cas;
 	int rcd, rp, ras, chan;
 	ulong dev0, offset;
@@ -3218,7 +3145,7 @@
 	ptr = (long*)(dev0+offset+0x5008);
 	MCMain1_Register = *ptr & 0xFFFF;
 
-	if(MCMain0_Register == 0 || MCMain1_Register == 0) {
+	if (MCMain0_Register == 0 || MCMain1_Register == 0) {
 		chan = 1;
 	} else {
 		chan = 2;
@@ -3227,8 +3154,8 @@
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_hsw(void) {
-
+static void poll_timings_hsw(void)
+{
 	float cas;
 	int rcd, rp, ras, chan;
 	ulong dev0, offset = 0;
@@ -3246,13 +3173,14 @@
 	ptr = (long*)(dev0+offset+0x5008);
 	MCMain1_Register = *ptr & 0xFFFF;
 
-	if(MCMain0_Register && MCMain1_Register) {
+	if (MCMain0_Register && MCMain1_Register) {
 		chan = 2;
 	} else {
 		chan = 1;
 	}
 
-	if(MCMain0_Register) { offset = 0x0000; } else {	offset = 0x0400; }
+	if (MCMain0_Register) { offset = 0x0000; }
+	else { offset = 0x0400; }
 
 	// CAS Latency (tCAS)
 	ptr = (long*)(dev0+offset+0x4014);
@@ -3275,8 +3203,8 @@
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_snbe(void) {
-
+static void poll_timings_snbe(void)
+{
 	float cas;
 	int rcd, rp, ras;
 	int nb_channel = 0, current_channel = 0;
@@ -3286,26 +3214,26 @@
 	//Read Channel #1
 	pci_conf_read(0xFF, 16, 2, 0x80, 4, &temp);
 	temp &= 0x3F;
-	if(temp != 0xB) { current_channel = 0; nb_channel++; }
+	if (temp != 0xB) { current_channel = 0; nb_channel++; }
 
 	//Read Channel #2
 	pci_conf_read(0xFF, 16, 3, 0x80, 4, &temp);
 	temp &= 0x3F;
-	if(temp != 0xB) { current_channel = 1; nb_channel++; }
+	if (temp != 0xB) { current_channel = 1; nb_channel++; }
 
 	//Read Channel #3
 	pci_conf_read(0xFF, 16, 6, 0x80, 4, &temp);
 	temp &= 0x3F;
-	if(temp != 0xB) { current_channel = 4; nb_channel++; }
+	if (temp != 0xB) { current_channel = 4; nb_channel++; }
 
 	//Read Channel #4
 	pci_conf_read(0xFF, 16, 7, 0x80, 4, &temp);
 	temp &= 0x3F;
-	if(temp != 0xB) { current_channel = 5; nb_channel++; }
+	if (temp != 0xB) { current_channel = 5; nb_channel++; }
 
 
 	pci_conf_read(0, 5, 0, 0x84, 4, &temp);
-	ptr = (long*)((temp & 0xFC000000) + (MAKE_PCIE_ADDRESS(0xFF,16,current_channel) | 0x200));
+	ptr = (long*)((temp & 0xFC000000) + (MAKE_PCIE_ADDRESS(0xFF, 16, current_channel) | 0x200));
 	IMC_Register = *ptr & 0xFFFFFFFF;
 
 	// CAS Latency (tCAS)
@@ -3322,11 +3250,10 @@
 
 
 	print_ram_line(cas, rcd, rp, ras, nb_channel);
-
 }
 
-static void poll_timings_5400(void) {
-
+static void poll_timings_5400(void)
+{
 	// Thanks for CDH optis
 	ulong ambase, mtr1, mtr2, offset, mca;
 	long *ptr;
@@ -3335,11 +3262,11 @@
 
 	//Hard-coded Ambase value (should not be realocated by software when using Memtest86+
 	ambase = 0xFE000000;
-  offset = mtr1 = mtr2 = 0;
+	offset = mtr1 = mtr2 = 0;
 
-  // Will loop until a valid populated channel is found
-  // Bug  : DIMM 0 must be populated or it will fall in an endless loop
-  while(((mtr2 & 0xF) < 3) || ((mtr2 & 0xF) > 6)) {
+	// Will loop until a valid populated channel is found
+	// Bug  : DIMM 0 must be populated or it will fall in an endless loop
+	while (((mtr2 & 0xF) < 3) || ((mtr2 & 0xF) > 6)) {
 		ptr = (long*)(ambase+0x378+offset);
 		mtr1 = *ptr & 0xFFFFFFFF;
 
@@ -3366,21 +3293,20 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = 16 - (3 * ((mtr1 >> 29) & 3)) + ((mtr1 >> 12) & 3);
-  if(((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { ras = 9; }
+	if (((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { ras = 9; }
 
 
 	if ((mca >> 14) & 1) {
 		chan = 1;
-	}	else {
+	} else {
 		chan = 2;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
-
 }
 
-static void poll_timings_E7520(void) {
-
+static void poll_timings_E7520(void)
+{
 	ulong drt, ddrcsr;
 	float cas;
 	int rcd, rp, ras, chan;
@@ -3403,8 +3329,8 @@
 }
 
 
-static void poll_timings_i855(void) {
-
+static void poll_timings_i855(void)
+{
 	ulong drt, temp;
 	float cas;
 	int rcd, rp, ras = 0;
@@ -3427,7 +3353,7 @@
 
 	// RAS Precharge (tRP)
 	temp = (drt&0x1);
-	if (temp == 0x0) { rp = 3 ; }
+	if (temp == 0x0) { rp = 3; }
 	else { rp = 2; }
 
 	// RAS Active to precharge (tRAS)
@@ -3440,11 +3366,10 @@
 	else if (temp == 0x2) { ras = 5; }
 
 	print_ram_line(cas, rcd, rp, ras, 1);
-
 }
 
-static void poll_timings_E750x(void) {
-
+static void poll_timings_E750x(void)
+{
 	ulong drt, drc, temp;
 	float cas;
 	int rcd, rp, ras, chan;
@@ -3452,12 +3377,14 @@
 	pci_conf_read( 0, 0, 0, 0x78, 4, &drt);
 	pci_conf_read( 0, 0, 0, 0x7C, 4, &drc);
 
-	if ((drt >> 4) & 1) { cas = 2; } else { cas = 2.5; };
-	if ((drt >> 1) & 1) { rcd = 2; } else { rcd = 3; };
-	if (drt & 1) { rp = 2; } else { rp = 3; };
+	if ((drt >> 4) & 1) { cas = 2; } else { cas = 2.5; }
+	if ((drt >> 1) & 1) { rcd = 2; } else { rcd = 3; }
+	if (drt & 1) { rp = 2; } else { rp = 3; }
 
 	temp = ((drt >> 9) & 3);
-	if (temp == 2) { ras = 5; } else if (temp == 1) { ras = 6; } else { ras = 7; }
+	if (temp == 2) { ras = 5; }
+	else if (temp == 1) { ras = 6; }
+	else { ras = 7; }
 
 	if (((drc >> 22)&1) == 1) {
 		chan = 2;
@@ -3466,11 +3393,10 @@
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
-
 }
 
-static void poll_timings_i852(void) {
-
+static void poll_timings_i852(void)
+{
 	ulong drt, temp;
 	float cas;
 	int rcd, rp, ras;
@@ -3483,7 +3409,7 @@
 
 	// CAS Latency (tCAS)
 	temp = ((drt >> 5)&0x1);
-	if (temp == 0x0) { cas = 2.5;  }
+	if (temp == 0x0) { cas = 2.5; }
 	else { cas = 2; }
 
 	// RAS-To-CAS (tRCD)
@@ -3506,15 +3432,14 @@
 	else if (temp == 0x3) { ras = 5; }
 
 	print_ram_line(cas, rcd, rp, ras, 1);
-
 }
 
-static void poll_timings_amd64(void) {
-
+static void poll_timings_amd64(void)
+{
 	ulong dramtlr, dramclr;
 	int temp, chan;
 	float tcas = 0.0;
-	int trcd, trp, tras ;
+	int trcd, trp, tras;
 
 	pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramclr);
@@ -3522,57 +3447,55 @@
 	if (cpu_id.vers.bits.extendedModel >= 4) {
 		/* NEW K8 0Fh Family 90 nm (DDR2) */
 
-			// CAS Latency (tCAS)
-			tcas = (dramtlr & 0x7) + 1;
+		// CAS Latency (tCAS)
+		tcas = (dramtlr & 0x7) + 1;
 
-			// RAS-To-CAS (tRCD)
-			trcd = ((dramtlr >> 4) & 0x3) + 3;
+		// RAS-To-CAS (tRCD)
+		trcd = ((dramtlr >> 4) & 0x3) + 3;
 
-			// RAS Precharge (tRP)
-			trp = ((dramtlr >> 8) & 0x3) + 3;
+		// RAS Precharge (tRP)
+		trp = ((dramtlr >> 8) & 0x3) + 3;
 
-			// RAS Active to precharge (tRAS)
-			tras = ((dramtlr >> 12) & 0xF) + 3;
+		// RAS Active to precharge (tRAS)
+		tras = ((dramtlr >> 12) & 0xF) + 3;
 
-			// Print 64 or 128 bits mode
-			if ((dramclr >> 11)&1) {
-				chan = 2;
-			} else {
-				chan = 1;
-			}
-
+		// Print 64 or 128 bits mode
+		if ((dramclr >> 11)&1) {
+			chan = 2;
+		} else {
+			chan = 1;
+		}
 	} else {
 		/* OLD K8 (DDR1) */
 
-			// CAS Latency (tCAS)
-			temp = (dramtlr & 0x7);
-			if (temp == 0x1) { tcas = 2; }
-			else if (temp == 0x2) { tcas = 3; }
-			else if (temp == 0x5) { tcas = 2.5; }
+		// CAS Latency (tCAS)
+		temp = (dramtlr & 0x7);
+		if (temp == 0x1) { tcas = 2; }
+		else if (temp == 0x2) { tcas = 3; }
+		else if (temp == 0x5) { tcas = 2.5; }
 
-			// RAS-To-CAS (tRCD)
-			trcd = ((dramtlr >> 12) & 0x7);
+		// RAS-To-CAS (tRCD)
+		trcd = ((dramtlr >> 12) & 0x7);
 
-			// RAS Precharge (tRP)
-			trp = ((dramtlr >> 24) & 0x7);
+		// RAS Precharge (tRP)
+		trp = ((dramtlr >> 24) & 0x7);
 
-			// RAS Active to precharge (tRAS)
-			tras = ((dramtlr >> 20) & 0xF);
+		// RAS Active to precharge (tRAS)
+		tras = ((dramtlr >> 20) & 0xF);
 
-			// Print 64 or 128 bits mode
-			if (((dramclr >> 16)&1) == 1) {
-				chan = 2;
-			} else {
-				chan = 1;
-			}
+		// Print 64 or 128 bits mode
+		if (((dramclr >> 16)&1) == 1) {
+			chan = 2;
+		} else {
+			chan = 1;
+		}
 	}
 
 	print_ram_line(tcas, trcd, trp, tras, chan);
-
 }
 
-static void poll_timings_k10(void) {
-
+static void poll_timings_k10(void)
+{
 	ulong dramtlr, dramclr, dramchr, dramchrb;
 	ulong offset = 0;
 	int cas, rcd, rp, ras, chan;
@@ -3580,11 +3503,10 @@
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dramchrb);
 
-	if(((dramchr>>14) & 0x1) || ((dramchr>>14) & 0x1)) { chan = 1; } else { chan = 2; }
+	if (((dramchr>>14) & 0x1) || ((dramchr>>14) & 0x1)) { chan = 1; } else { chan = 2; }
 
 	// If Channel A not enabled, switch to channel B
-	if(((dramchr>>14) & 0x1))
-	{
+	if (((dramchr>>14) & 0x1)) {
 		offset = 0x100;
 		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
 	}
@@ -3593,41 +3515,39 @@
 	pci_conf_read(0, 24, 2, 0x110, 4, &dramclr);
 
 	// CAS Latency (tCAS)
-	if(((dramchr >> 8)&1) || ((dramchr & 0x7) == 0x4)){
+	if (((dramchr >> 8)&1) || ((dramchr & 0x7) == 0x4)) {
 		// DDR3 or DDR2-1066
 		cas = (dramtlr & 0xF) + 4;
 		rcd = ((dramtlr >> 4) & 0x7) + 5;
 		rp = ((dramtlr >> 7) & 0x7) + 5;
-	  ras = ((dramtlr >> 12) & 0xF) + 15;
+		ras = ((dramtlr >> 12) & 0xF) + 15;
 	} else {
-	// DDR2-800 or less
+		// DDR2-800 or less
 		cas = (dramtlr & 0xF) + 1;
 		rcd = ((dramtlr >> 4) & 0x3) + 3;
 		rp = ((dramtlr >> 8) & 0x3) + 3;
-	  ras = ((dramtlr >> 12) & 0xF) + 3;
+		ras = ((dramtlr >> 12) & 0xF) + 3;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_k12(void) {
-
+static void poll_timings_k12(void)
+{
 	ulong dramt0 = 0, dramlow = 0, dimma, dimmb;
 	int cas, rcd, rp, ras, chan = 0;
 
 	pci_conf_read(0, 24, 2, 0x94, 4, &dimma);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dimmb);
 
-	if(((dimma >> 14) & 0x1) == 0)
-	{
+	if (((dimma >> 14) & 0x1) == 0) {
 		chan++;
 		pci_conf_read(0, 24, 2, 0x88, 4, &dramlow);
 		pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040);
 		pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);
 	}
 
-	if(((dimmb >> 14) & 0x1) == 0)
-	{
+	if (((dimmb >> 14) & 0x1) == 0) {
 		chan++;
 		pci_conf_read(0, 24, 2, 0x188, 4, &dramlow);
 		pci_conf_write(0, 24, 2, 0x1F0, 4, 0x00000040);
@@ -3637,14 +3557,14 @@
 	cas = (dramlow & 0xF) + 4;
 	rcd = (dramt0 & 0xF) + 5;
 	rp = ((dramt0 >> 8) & 0xF) + 5;
-  ras = ((dramt0 >> 16) & 0x1F) + 15;
+	ras = ((dramt0 >> 16) & 0x1F) + 15;
 
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
 
-static void poll_timings_k14(void) {
-
+static void poll_timings_k14(void)
+{
 	ulong dramt0, dramlow;
 	int cas, rcd, rp, ras;
 
@@ -3655,19 +3575,19 @@
 	cas = (dramlow & 0xF) + 4;
 	rcd = (dramt0 & 0xF) + 5;
 	rp = ((dramt0 >> 8) & 0xF) + 5;
-  ras = ((dramt0 >> 16) & 0x1F) + 15;
+	ras = ((dramt0 >> 16) & 0x1F) + 15;
 
 	print_ram_line(cas, rcd, rp, ras, 1);
 }
 
-static void poll_timings_k15(void) {
-
+static void poll_timings_k15(void)
+{
 	ulong dramp1, dramp2, dimma, dimmb;
 	int cas, rcd, rp, ras, chan = 0;
 
 	pci_conf_read(0, 24, 2, 0x94, 4, &dimma);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dimmb);
-	if(((dimma>>14) & 0x1) || ((dimmb>>14) & 0x1)) { chan = 1; } else { chan = 2; }
+	if (((dimma>>14) & 0x1) || ((dimmb>>14) & 0x1)) { chan = 1; } else { chan = 2; }
 
 	pci_conf_read(0, 24, 2, 0x200, 4, &dramp1);
 	pci_conf_read(0, 24, 2, 0x204, 4, &dramp2);
@@ -3675,13 +3595,13 @@
 	cas = dramp1 & 0x1F;
 	rcd = (dramp1 >> 8) & 0x1F;
 	rp = (dramp1 >> 16) & 0x1F;
-  ras = (dramp1 >> 24) & 0x3F;
+	ras = (dramp1 >> 24) & 0x3F;
 
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_k16(void) {
-
+static void poll_timings_k16(void)
+{
 	ulong dramt0, dramt1;
 	int cas, rcd, rp, ras;
 
@@ -3696,8 +3616,8 @@
 	print_ram_line(cas, rcd, rp, ras, 1);
 }
 
-static void poll_timings_EP80579(void) {
-
+static void poll_timings_EP80579(void)
+{
 	ulong drt1, drt2;
 	float cas;
 	int rcd, rp, ras;
@@ -3713,8 +3633,8 @@
 	print_ram_line(cas, rcd, rp, ras, 0);
 }
 
-static void poll_timings_nf2(void) {
-
+static void poll_timings_nf2(void)
+{
 	ulong dramtlr, dramtlr2, dramtlr3, temp;
 	ulong dimm1p, dimm2p, dimm3p;
 	float cas = 0.0;
@@ -3745,7 +3665,7 @@
 	// Print 64 or 128 bits mode
 	// If DIMM1 & DIMM3 or DIMM1 & DIMM2 populated, than Dual Channel.
 
-	if ((dimm3p&1) + (dimm2p&1) == 2 || (dimm3p&1) + (dimm1p&1) == 2 ) {
+	if ((dimm3p&1) + (dimm2p&1) == 2 || (dimm3p&1) + (dimm1p&1) == 2) {
 		chan = 2;
 	} else {
 		chan = 1;
@@ -3753,8 +3673,8 @@
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
-static void poll_timings_us15w(void) {
-
+static void poll_timings_us15w(void)
+{
 	// Thanks for CDH optis
 	ulong dtr;
 	float cas;
@@ -3775,11 +3695,10 @@
 	rp = ((dtr >> 0) & 0x3) + 3;
 
 	print_ram_line(cas, rcd, rp, 9, 1);
-
 }
 
-static void poll_timings_nhm(void) {
-
+static void poll_timings_nhm(void)
+{
 	ulong mc_channel_bank_timing, mc_control, mc_channel_mrs_value;
 	float cas;
 	int rcd, rp, ras, chan;
@@ -3790,11 +3709,11 @@
 	mc_control = (mc_control >> 8) & 0x7;
 
 	/* Get the first valid channel */
-	if(mc_control & 1) {
+	if (mc_control & 1) {
 		fvc_bn = 4;
-	} else if(mc_control & 2) {
+	} else if (mc_control & 2) {
 		fvc_bn = 5;
-	}	else if(mc_control & 4) {
+	} else if (mc_control & 4) {
 		fvc_bn = 6;
 	}
 
@@ -3808,7 +3727,7 @@
 	rp = mc_channel_bank_timing & 0xF;
 
 	// Print 1, 2 or 3 Channels
-	if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {
+	if (mc_control == 1 || mc_control == 2 || mc_control == 4) {
 		chan = 1;
 	} else if (mc_control == 7) {
 		chan = 3;
@@ -3816,13 +3735,11 @@
 		chan = 2;
 	}
 	print_ram_line(cas, rcd, rp, ras, chan);
-
 }
 
 static void poll_timings_ct(void)
 {
-
-	unsigned long mcr,mdr;
+	unsigned long mcr, mdr;
 	float cas;
 	int rcd, rp, ras;
 
@@ -3857,7 +3774,6 @@
 
 	// Print
 	print_ram_line(cas, rcd, rp, ras, 1);
-
 }
 
 /* ------------------ Let's continue ------------------ */
@@ -3865,169 +3781,168 @@
 
 struct pci_memory_controller controllers[] = {
 	/* Default unknown chipset */
-	{ 0, 0, "","",                    0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0,      0,      "",                      "",               0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* AMD */
-	{ 0x1022, 0x7006, "AMD 751","SDRAM PC-100",   0, poll_fsb_nothing, poll_timings_nothing, setup_amd751, poll_nothing },
-	{ 0x1022, 0x700c, "AMD 762","DDR-SDRAM", 		  0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_nothing },
-	{ 0x1022, 0x700e, "AMD 761","DDR-SDRAM", 		  0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x, poll_nothing },
+	{ 0x1022, 0x7006, "AMD 751",               "SDRAM PC-100",   0, poll_fsb_nothing, poll_timings_nothing, setup_amd751,  poll_nothing },
+	{ 0x1022, 0x700c, "AMD 762",               "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x,  poll_nothing },
+	{ 0x1022, 0x700e, "AMD 761",               "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_amd76x,  poll_nothing },
 
 	/* SiS */
-	{ 0x1039, 0x0600, "SiS 600","EDO/SDRAM",   			0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0620, "SiS 620","SDRAM",   					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x5600, "SiS 5600","SDRAM",  					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0645, "SiS 645","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0646, "SiS 645DX","DDR-SDRAM", 			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0630, "SiS 630","SDRAM",   					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0650, "SiS 650","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0651, "SiS 651","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0730, "SiS 730","SDRAM",   					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0735, "SiS 735","DDR-SDRAM",   			0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0740, "SiS 740","DDR-SDRAM",   			0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0745, "SiS 745","DDR-SDRAM",   			0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0748, "SiS 748","DDR-SDRAM",   			0, poll_fsb_amd32, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0655, "SiS 655","DDR-SDRAM",				0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0656, "SiS 656","DDR/DDR2-SDRAM",		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0648, "SiS 648","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0649, "SiS 649","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0661, "SiS 661","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0671, "SiS 671","DDR2-SDRAM",   		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0672, "SiS 672","DDR2-SDRAM",   		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0600, "SiS 600",               "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0620, "SiS 620",               "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x5600, "SiS 5600",              "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0645, "SiS 645",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0646, "SiS 645DX",             "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0630, "SiS 630",               "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0650, "SiS 650",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0651, "SiS 651",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0730, "SiS 730",               "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0735, "SiS 735",               "DDR-SDRAM",      0, poll_fsb_amd32,   poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0740, "SiS 740",               "DDR-SDRAM",      0, poll_fsb_amd32,   poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0745, "SiS 745",               "DDR-SDRAM",      0, poll_fsb_amd32,   poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0748, "SiS 748",               "DDR-SDRAM",      0, poll_fsb_amd32,   poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0655, "SiS 655",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0656, "SiS 656",               "DDR/DDR2-SDRAM", 0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0648, "SiS 648",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0649, "SiS 649",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0661, "SiS 661",               "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0671, "SiS 671",               "DDR2-SDRAM",     0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1039, 0x0672, "SiS 672",               "DDR2-SDRAM",     0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* ALi */
-	{ 0x10b9, 0x1531, "ALi Aladdin 4","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x10b9, 0x1541, "ALi Aladdin 5","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x10b9, 0x1644, "ALi Aladdin M1644","SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x10b9, 0x1531, "ALi Aladdin 4",         "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x10b9, 0x1541, "ALi Aladdin 5",         "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x10b9, 0x1644, "ALi Aladdin M1644",     "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* ATi */
-	{ 0x1002, 0x5830, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1002, 0x5831, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1002, 0x5832, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1002, 0x5833, "ATi Radeon 9100 IGP","DDR-SDRAM", 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1002, 0x5954, "ATi Xpress 200","DDR-SDRAM", 		 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1002, 0x5A41, "ATi Xpress 200","DDR-SDRAM",			 0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5830, "ATi Radeon 9100 IGP",   "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5831, "ATi Radeon 9100 IGP",   "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5832, "ATi Radeon 9100 IGP",   "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5833, "ATi Radeon 9100 IGP",   "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5954, "ATi Xpress 200",        "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1002, 0x5A41, "ATi Xpress 200",        "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* nVidia */
-	{ 0x10de, 0x01A4, "nVidia nForce","DDR-SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x10de, 0x01E0, "nVidia nForce2 SPP","",		 0, poll_fsb_nf2, poll_timings_nf2, setup_nothing, poll_nothing },
-	{ 0x10de, 0x0071, "nForce4 SLI","", 					 0, poll_fsb_nf4ie, poll_timings_nf4ie, setup_nothing, poll_nothing },
+	{ 0x10de, 0x01A4, "nVidia nForce",         "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x10de, 0x01E0, "nVidia nForce2 SPP",    "",               0, poll_fsb_nf2,     poll_timings_nf2,     setup_nothing, poll_nothing },
+	{ 0x10de, 0x0071, "nForce4 SLI",           "",               0, poll_fsb_nf4ie,   poll_timings_nf4ie,   setup_nothing, poll_nothing },
 
 	/* VIA */
-	{ 0x1106, 0x0305, "VIA KT133/KT133A","SDRAM",    			0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0391, "VIA KX133","SDRAM",    						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0501, "VIA MVP4","EDO/SDRAM",    					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0585, "VIA VP/VPX","EDO/SDRAM", 				  0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0595, "VIA VP2","EDO/SDRAM",  						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0597, "VIA VP3","EDO/SDRAM",  						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0598, "VIA MVP3","EDO/SDRAM",  						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0691, "VIA Apollo Pro 133(A)","SDRAM",  	0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0693, "VIA Apollo Pro+","SDRAM",  				0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0601, "VIA PLE133","SDRAM",  							0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3099, "VIA KT266(A)/KT333","DDR-SDRAM",		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3189, "VIA KT400(A)/600","DDR-SDRAM",			0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0269, "VIA KT880","DDR-SDRAM", 						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3205, "VIA KM400","DDR-SDRAM", 						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3116, "VIA KM266","DDR-SDRAM", 						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3156, "VIA KN266","DDR-SDRAM", 						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3123, "VIA CLE266","DDR-SDRAM", 					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x0198, "VIA PT800","DDR-SDRAM", 						0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1106, 0x3258, "VIA PT880","DDR2-SDRAM", 					0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0305, "VIA KT133/KT133A",      "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0391, "VIA KX133",             "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0501, "VIA MVP4",              "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0585, "VIA VP/VPX",            "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0595, "VIA VP2",               "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0597, "VIA VP3",               "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0598, "VIA MVP3",              "EDO/SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0691, "VIA Apollo Pro 133(A)", "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0693, "VIA Apollo Pro+",       "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0601, "VIA PLE133",            "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3099, "VIA KT266(A)/KT333",    "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3189, "VIA KT400(A)/600",      "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0269, "VIA KT880",             "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3205, "VIA KM400",             "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3116, "VIA KM266",             "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3156, "VIA KN266",             "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3123, "VIA CLE266",            "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x0198, "VIA PT800",             "DDR-SDRAM",      0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x1106, 0x3258, "VIA PT880",             "DDR2-SDRAM",     0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* Serverworks */
-	{ 0x1166, 0x0008, "CNB20HE","SDRAM",   0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing },
-	{ 0x1166, 0x0009, "CNB20LE","SDRAM",   0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20, poll_nothing },
+	{ 0x1166, 0x0008, "CNB20HE",               "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20,   poll_nothing },
+	{ 0x1166, 0x0009, "CNB20LE",               "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_cnb20,   poll_nothing },
 
 	/* Intel */
-	{ 0x8086, 0x1130, "Intel i815","SDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x122d, "Intel i430FX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x1235, "Intel i430MX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x1237, "Intel i440FX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x1250, "Intel i430HX","EDO DRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x1A21, "Intel i840","RDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_i840, poll_nothing },
-	{ 0x8086, 0x1A30, "Intel i845","SDR/DDR",		0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_nothing },
-	{ 0x8086, 0x2560, "Intel i845E/G/PE/GE","",	0, poll_fsb_p4, poll_timings_nothing, setup_i845, poll_nothing },
-	{ 0x8086, 0x2500, "Intel i820","RDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_i820, poll_nothing },
-	{ 0x8086, 0x2530, "Intel i850","RDRAM",  		0, poll_fsb_p4, poll_timings_nothing, setup_i850, poll_nothing },
-	{ 0x8086, 0x2531, "Intel i860","RDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_i860, poll_nothing },
-	{ 0x8086, 0x7030, "Intel i430VX","SDRAM", 	0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7100, "Intel i430TX","SDRAM", 	0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7120, "Intel i810","SDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7122, "Intel i810","SDRAM",  		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7124, "Intel i810E","SDRAM", 		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7180, "Intel i440[LE]X","SDRAM",0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7190, "Intel i440BX","SDRAM",		0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x7192, "Intel i440BX","SDRAM", 	0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x71A0, "Intel i440GX","SDRAM", 	0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_nothing },
-	{ 0x8086, 0x71A2, "Intel i440GX","SDRAM",  	0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx, poll_nothing },
-	{ 0x8086, 0x84C5, "Intel i450GX","SDRAM", 	0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x2540, "Intel E7500","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_nothing },
-	{ 0x8086, 0x254C, "Intel E7501","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E750x, setup_iE7xxx, poll_nothing },
-	{ 0x8086, 0x255d, "Intel E7205","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_nothing },
-  { 0x8086, 0x3592, "Intel E7320","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing },
-  { 0x8086, 0x2588, "Intel E7221","DDR-SDRAM",0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
-  { 0x8086, 0x3590, "Intel E7520","DDR-SDRAM",0, poll_fsb_p4, poll_timings_E7520, setup_iE7520, poll_nothing },
-  { 0x8086, 0x2600, "Intel E8500","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x8086, 0x2570, "Intel i848/i865","", 		0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing },
-	{ 0x8086, 0x2578, "Intel i875P","",     		0, poll_fsb_i875, poll_timings_i875, setup_i875, poll_nothing },
-	{ 0x8086, 0x2550, "Intel E7505","DDR-SDRAM",0, poll_fsb_p4, poll_timings_nothing, setup_iE7xxx, poll_nothing },
-	{ 0x8086, 0x3580, "Intel i852P/i855G","",		0, poll_fsb_i855, poll_timings_i852, setup_nothing, poll_nothing },
-	{ 0x8086, 0x3340, "Intel i855PM","",    		0, poll_fsb_i855, poll_timings_i855, setup_nothing, poll_nothing },
-	{ 0x8086, 0x2580, "Intel i915P/G","",   		0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x2590, "Intel i915PM/GM","", 		0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x2584, "Intel i925X/XE","",  		0, poll_fsb_i925, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x2770, "Intel i945P/G","", 	 		0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x27A0, "Intel i945GM/PM","", 		0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x27AC, "Intel i945GME","", 	 		0, poll_fsb_i945gme, poll_timings_i925, setup_i925, poll_nothing },
-	{ 0x8086, 0x2774, "Intel i955X","", 		 		0, poll_fsb_i945, poll_timings_i925, setup_i925, poll_nothing},
-	{ 0x8086, 0x277C, "Intel i975X","", 		 		0, poll_fsb_i975, poll_timings_i925, setup_i925, poll_nothing},
-	{ 0x8086, 0x2970, "Intel i946PL/GZ","", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
-	{ 0x8086, 0x2990, "Intel Q963/Q965","", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
-	{ 0x8086, 0x29A0, "Intel P965/G965","", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
-	{ 0x8086, 0x2A00, "Intel GM965/GL960","", 	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
-	{ 0x8086, 0x2A10, "Intel GME965/GLE960","",	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
-	{ 0x8086, 0x2A40, "Intel PM/GM45/47","",		0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
-	{ 0x8086, 0x29B0, "Intel Q35","", 	 		 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x29C0, "Intel P35/G33","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x29D0, "Intel Q33","",	  	 			0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x29E0, "Intel X38/X48","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x29F0, "Intel 3200/3210","", 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x2E10, "Intel Q45/Q43","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x2E20, "Intel P45/G45","",	  		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x2E30, "Intel G41","", 	 				0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0x8086, 0x4001, "Intel 5400A","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x4003, "Intel 5400B","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x25D8, "Intel 5000P","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x25D4, "Intel 5000V","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x25C0, "Intel 5000X","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x25D0, "Intel 5000Z","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
-	{ 0x8086, 0x5020, "Intel EP80579","",    		0, poll_fsb_p4, 	poll_timings_EP80579, setup_nothing, poll_nothing },
-	{ 0x8086, 0x8100, "Intel US15W","",					0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
-	{ 0x8086, 0x8101, "Intel UL11L/US15L","", 	0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
+	{ 0x8086, 0x1130, "Intel i815",            "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x122d, "Intel i430FX",          "EDO DRAM",       0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x1235, "Intel i430MX",          "EDO DRAM",       0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x1237, "Intel i440FX",          "EDO DRAM",       0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x1250, "Intel i430HX",          "EDO DRAM",       0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x1A21, "Intel i840",            "RDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_i840,    poll_nothing },
+	{ 0x8086, 0x1A30, "Intel i845",            "SDR/DDR",        0, poll_fsb_p4,      poll_timings_nothing, setup_i845,    poll_nothing },
+	{ 0x8086, 0x2560, "Intel i845E/G/PE/GE",   "",               0, poll_fsb_p4,      poll_timings_nothing, setup_i845,    poll_nothing },
+	{ 0x8086, 0x2500, "Intel i820",            "RDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_i820,    poll_nothing },
+	{ 0x8086, 0x2530, "Intel i850",            "RDRAM",          0, poll_fsb_p4,      poll_timings_nothing, setup_i850,    poll_nothing },
+	{ 0x8086, 0x2531, "Intel i860",            "RDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_i860,    poll_nothing },
+	{ 0x8086, 0x7030, "Intel i430VX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7100, "Intel i430TX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7120, "Intel i810",            "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7122, "Intel i810",            "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7124, "Intel i810E",           "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7180, "Intel i440[LE]X",       "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7190, "Intel i440BX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x7192, "Intel i440BX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x71A0, "Intel i440GX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx,  poll_nothing },
+	{ 0x8086, 0x71A2, "Intel i440GX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_i440gx,  poll_nothing },
+	{ 0x8086, 0x84C5, "Intel i450GX",          "SDRAM",          0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x2540, "Intel E7500",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_E750x,   setup_iE7xxx,  poll_nothing },
+	{ 0x8086, 0x254C, "Intel E7501",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_E750x,   setup_iE7xxx,  poll_nothing },
+	{ 0x8086, 0x255d, "Intel E7205",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_iE7xxx,  poll_nothing },
+	{ 0x8086, 0x3592, "Intel E7320",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_E7520,   setup_iE7520,  poll_nothing },
+	{ 0x8086, 0x2588, "Intel E7221",           "DDR-SDRAM",      0, poll_fsb_i925,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x3590, "Intel E7520",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_E7520,   setup_iE7520,  poll_nothing },
+	{ 0x8086, 0x2600, "Intel E8500",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_nothing, poll_nothing },
+	{ 0x8086, 0x2570, "Intel i848/i865",       "",               0, poll_fsb_i875,    poll_timings_i875,    setup_i875,    poll_nothing },
+	{ 0x8086, 0x2578, "Intel i875P",           "",               0, poll_fsb_i875,    poll_timings_i875,    setup_i875,    poll_nothing },
+	{ 0x8086, 0x2550, "Intel E7505",           "DDR-SDRAM",      0, poll_fsb_p4,      poll_timings_nothing, setup_iE7xxx,  poll_nothing },
+	{ 0x8086, 0x3580, "Intel i852P/i855G",     "",               0, poll_fsb_i855,    poll_timings_i852,    setup_nothing, poll_nothing },
+	{ 0x8086, 0x3340, "Intel i855PM",          "",               0, poll_fsb_i855,    poll_timings_i855,    setup_nothing, poll_nothing },
+	{ 0x8086, 0x2580, "Intel i915P/G",         "",               0, poll_fsb_i925,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x2590, "Intel i915PM/GM",       "",               0, poll_fsb_i925,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x2584, "Intel i925X/XE",        "",               0, poll_fsb_i925,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x2770, "Intel i945P/G",         "",               0, poll_fsb_i945,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x27A0, "Intel i945GM/PM",       "",               0, poll_fsb_i945,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x27AC, "Intel i945GME",         "",               0, poll_fsb_i945gme, poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x2774, "Intel i955X",           "",               0, poll_fsb_i945,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x277C, "Intel i975X",           "",               0, poll_fsb_i975,    poll_timings_i925,    setup_i925,    poll_nothing },
+	{ 0x8086, 0x2970, "Intel i946PL/GZ",       "",               0, poll_fsb_i965,    poll_timings_i965,    setup_p35,     poll_nothing },
+	{ 0x8086, 0x2990, "Intel Q963/Q965",       "",               0, poll_fsb_i965,    poll_timings_i965,    setup_p35,     poll_nothing },
+	{ 0x8086, 0x29A0, "Intel P965/G965",       "",               0, poll_fsb_i965,    poll_timings_i965,    setup_p35,     poll_nothing },
+	{ 0x8086, 0x2A00, "Intel GM965/GL960",     "",               0, poll_fsb_im965,   poll_timings_im965,   setup_p35,     poll_nothing },
+	{ 0x8086, 0x2A10, "Intel GME965/GLE960",   "",               0, poll_fsb_im965,   poll_timings_im965,   setup_p35,     poll_nothing },
+	{ 0x8086, 0x2A40, "Intel PM/GM45/47",      "",               0, poll_fsb_im965,   poll_timings_im965,   setup_p35,     poll_nothing },
+	{ 0x8086, 0x29B0, "Intel Q35",             "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x29C0, "Intel P35/G33",         "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x29D0, "Intel Q33",             "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x29E0, "Intel X38/X48",         "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x29F0, "Intel 3200/3210",       "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x2E10, "Intel Q45/Q43",         "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x2E20, "Intel P45/G45",         "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x2E30, "Intel G41",             "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0x8086, 0x4001, "Intel 5400A",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x4003, "Intel 5400B",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x25D8, "Intel 5000P",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x25D4, "Intel 5000V",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x25C0, "Intel 5000X",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x25D0, "Intel 5000Z",           "",               0, poll_fsb_5400,    poll_timings_5400,    setup_E5400,   poll_nothing },
+	{ 0x8086, 0x5020, "Intel EP80579",         "",               0, poll_fsb_p4,      poll_timings_EP80579, setup_nothing, poll_nothing },
+	{ 0x8086, 0x8100, "Intel US15W",           "",               0, poll_fsb_us15w,   poll_timings_us15w,   setup_nothing, poll_nothing },
+	{ 0x8086, 0x8101, "Intel UL11L/US15L",     "",               0, poll_fsb_us15w,   poll_timings_us15w,   setup_nothing, poll_nothing },
 
 	/* INTEL IMC (Integrated Memory Controllers) */
-	{ 0xFFFF, 0x0001, "Core IMC","", 	 				0, poll_fsb_nhm, 	poll_timings_nhm, setup_nhm, poll_nothing},
-	{ 0xFFFF, 0x0002, "Core IMC","", 	 				0, poll_fsb_nhm32, 	poll_timings_nhm, setup_nhm32, poll_nothing},
-	{ 0xFFFF, 0x0003, "Core IMC","", 	 				0, poll_fsb_wmr, 	poll_timings_wmr, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0004, "SNB IMC","", 	 				0, poll_fsb_snb, 	poll_timings_snb, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0005, "SNB-E IMC","",		 	 		0, poll_fsb_snbe, poll_timings_snbe, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0006, "IVB IMC","",			 	 		0, poll_fsb_ivb, 	poll_timings_snb, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0007, "HSW IMC","",			 	 		0, poll_fsb_ivb, 	poll_timings_hsw, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0008, "PineView IMC","", 			0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
-	{ 0xFFFF, 0x0009, "CedarTrail IMC","",		0, poll_fsb_ct, poll_timings_ct, setup_nothing, poll_nothing},
-	{ 0xFFFF, 0x000A, "BayTrail IMC","",		0, poll_fsb_ct, poll_timings_ct, setup_nothing, poll_nothing}, // same as CedarTrail IMC
+	{ 0xFFFF, 0x0001, "Core IMC",              "",               0, poll_fsb_nhm,     poll_timings_nhm,     setup_nhm,     poll_nothing },
+	{ 0xFFFF, 0x0002, "Core IMC",              "",               0, poll_fsb_nhm32,   poll_timings_nhm,     setup_nhm32,   poll_nothing },
+	{ 0xFFFF, 0x0003, "Core IMC",              "",               0, poll_fsb_wmr,     poll_timings_wmr,     setup_wmr,     poll_nothing },
+	{ 0xFFFF, 0x0004, "SNB IMC",               "",               0, poll_fsb_snb,     poll_timings_snb,     setup_wmr,     poll_nothing },
+	{ 0xFFFF, 0x0005, "SNB-E IMC",             "",               0, poll_fsb_snbe,    poll_timings_snbe,    setup_wmr,     poll_nothing },
+	{ 0xFFFF, 0x0006, "IVB IMC",               "",               0, poll_fsb_ivb,     poll_timings_snb,     setup_wmr,     poll_nothing },
+	{ 0xFFFF, 0x0007, "HSW IMC",               "",               0, poll_fsb_ivb,     poll_timings_hsw,     setup_wmr,     poll_nothing },
+	{ 0xFFFF, 0x0008, "PineView IMC",          "",               0, poll_fsb_p35,     poll_timings_p35,     setup_p35,     poll_nothing },
+	{ 0xFFFF, 0x0009, "CedarTrail IMC",        "",               0, poll_fsb_ct,      poll_timings_ct,      setup_nothing, poll_nothing },
+	{ 0xFFFF, 0x000A, "BayTrail IMC",          "",               0, poll_fsb_ct,      poll_timings_ct,      setup_nothing, poll_nothing }, // same as CedarTrail IMC
 
 	/* AMD IMC (Integrated Memory Controllers) */
-	{ 0xFFFF, 0x0100, "AMD K8 IMC","",				0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_nothing },
-	{ 0xFFFF, 0x0101, "AMD K10 IMC","",			  0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing },
-	{ 0xFFFF, 0x0102, "AMD K12 IMC","",			  0, poll_fsb_k12, poll_timings_k12, setup_apu, poll_nothing },
-	{ 0xFFFF, 0x0103, "AMD K14 IMC","",				0, poll_fsb_k14, poll_timings_k14, setup_apu, poll_nothing },
-	{ 0xFFFF, 0x0104, "AMD K15 IMC","",				0, poll_fsb_k15, poll_timings_k15, setup_apu, poll_nothing },
-	{ 0xFFFF, 0x0105, "AMD K16 IMC","",				0, poll_fsb_k16, poll_timings_k16, setup_apu, poll_nothing }
+	{ 0xFFFF, 0x0100, "AMD K8 IMC",            "",               0, poll_fsb_amd64,   poll_timings_amd64,   setup_amd64,   poll_nothing },
+	{ 0xFFFF, 0x0101, "AMD K10 IMC",           "",               0, poll_fsb_k10,     poll_timings_k10,     setup_k10,     poll_nothing },
+	{ 0xFFFF, 0x0102, "AMD K12 IMC",           "",               0, poll_fsb_k12,     poll_timings_k12,     setup_apu,     poll_nothing },
+	{ 0xFFFF, 0x0103, "AMD K14 IMC",           "",               0, poll_fsb_k14,     poll_timings_k14,     setup_apu,     poll_nothing },
+	{ 0xFFFF, 0x0104, "AMD K15 IMC",           "",               0, poll_fsb_k15,     poll_timings_k15,     setup_apu,     poll_nothing },
+	{ 0xFFFF, 0x0105, "AMD K16 IMC",           "",               0, poll_fsb_k16,     poll_timings_k16,     setup_apu,     poll_nothing }
 };
 
 static void print_memory_controller(void)
 {
-
 	/* Print memory controller info */
 	if (ctrl.index == 0) {
 		return;
@@ -4083,13 +3998,11 @@
 	*/
 
 
-
 	/* Print advanced caracteristics  */
 	col2 = 0;
 
 	controllers[ctrl.index].poll_fsb();
 	controllers[ctrl.index].poll_timings();
-
 }
 
 
@@ -4103,20 +4016,20 @@
 	result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_DEVICE_ID, 2, &device);
 
 	// Detect IMC by CPUID
-	if(imc_type) { vendor = 0xFFFF; device = imc_type; }
-	if(v->fail_safe & 1) { vendor = 0xFFFF; device = 0xFFFF; }
+	if (imc_type) { vendor = 0xFFFF; device = imc_type; }
+	if (v->fail_safe & 1) { vendor = 0xFFFF; device = 0xFFFF; }
 
 	//hprint(11,0,vendor); hprint(11,10,device);
 
 	ctrl.index = 0;
-		if (result == 0 || imc_type) {
-			for(i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
-				if ((controllers[i].vendor == vendor) && (controllers[i].device == device)) {
-					ctrl.index = i;
-					break;
-				}
+	if (result == 0 || imc_type) {
+		for (i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
+			if ((controllers[i].vendor == vendor) && (controllers[i].device == device)) {
+				ctrl.index = i;
+				break;
 			}
 		}
+	}
 
 	controllers[ctrl.index].setup_ecc();
 	/* Don't enable ECC polling by default unless it has
@@ -4125,8 +4038,7 @@
 	//set_ecc_polling(-1);
 	print_memory_controller();
 
-	if(imc_type) { print_dmi_startup_info(); }
-
+	if (imc_type) { print_dmi_startup_info(); }
 }
 
 void poll_errors(void)
@@ -4152,4 +4064,3 @@
 	}
 }
 */
-
diff --git a/coreboot.c b/coreboot.c
index b3c01bd..0b38d63 100644
--- a/coreboot.c
+++ b/coreboot.c
@@ -49,15 +49,14 @@
 			sum -= 0xFFFF;
 	}
 	return (~sum) & 0xFFFF;
-
 }
 
 #define for_each_lbrec(head, rec) \
-	for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
-		(((char *)rec) < (((char *)head) + sizeof(*head) + head->table_bytes))  && \
-		(rec->size >= 1) && \
-		((((char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) + head->table_bytes)); \
-		rec = (struct lb_record *)(((char *)rec) + rec->size))
+	for (rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
+	     (((char *)rec) < (((char *)head) + sizeof(*head) + head->table_bytes))  && \
+	     (rec->size >= 1) && \
+	     ((((char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) + head->table_bytes)); \
+	     rec = (struct lb_record *)(((char *)rec) + rec->size))
 
 
 static int count_lb_records(struct lb_header *head)
@@ -75,7 +74,7 @@
 {
 	unsigned long addr;
 	/* For now be stupid.... */
-	for(addr = start; addr < end; addr += 16) {
+	for (addr = start; addr < end; addr += 16) {
 		struct lb_header *head = (struct lb_header *)addr;
 		struct lb_record *recs = (struct lb_record *)(addr + sizeof(*head));
 		if (memcmp(head->signature, "LBIO", 4) != 0)
@@ -85,12 +84,12 @@
 		if (ip_compute_csum((unsigned char *)head, sizeof(*head)) != 0)
 			continue;
 		if (ip_compute_csum((unsigned char *)recs, head->table_bytes)
-			!= head->table_checksum)
+		    != head->table_checksum)
 			continue;
 		if (count_lb_records(head) != head->table_entries)
 			continue;
 		return head;
-	};
+	}
 	return 0;
 }
 
@@ -143,13 +142,13 @@
 		return 0;
 	}
 
-	 /* coreboot also can forward the table to the high tables area. */
-	 rec = (struct lb_record *)(((char *)head) + sizeof(*head));
-	 if (rec->tag == LB_TAG_FORWARD) {
-		 forward = (struct lb_forward *)rec;
-		 head = (struct lb_header *)(unsigned long)(forward->forward);
-		 if (!head) { return 0;	}
-	 }
+	/* coreboot also can forward the table to the high tables area. */
+	rec = (struct lb_record *)(((char *)head) + sizeof(*head));
+	if (rec->tag == LB_TAG_FORWARD) {
+		forward = (struct lb_forward *)rec;
+		head = (struct lb_header *)(unsigned long)(forward->forward);
+		if (!head) { return 0; }
+	}
 
 	mem = 0;
 	for_each_lbrec(head, rec) {
@@ -165,7 +164,7 @@
 	if (entries == 0)
 		return 1;
 	mem_info.e820_nr = 0;
-	for(i = 0; i < entries; i++) {
+	for (i = 0; i < entries; i++) {
 		unsigned long long start;
 		unsigned long long size;
 		unsigned long type;
@@ -174,7 +173,7 @@
 		}
 		start = mem->map[i].start;
 		size = mem->map[i].size;
-		type = (mem->map[i].type == LB_MEM_RAM)?E820_RAM: E820_RESERVED;
+		type = (mem->map[i].type == LB_MEM_RAM) ? E820_RAM : E820_RESERVED;
 		mem_info.e820[mem_info.e820_nr].addr = start;
 		mem_info.e820[mem_info.e820_nr].size = size;
 		mem_info.e820[mem_info.e820_nr].type = type;
diff --git a/cpuid.c b/cpuid.c
index 250a7aa..8816d0f 100644
--- a/cpuid.c
+++ b/cpuid.c
@@ -16,17 +16,17 @@
 
 	/* Get max std cpuid & vendor ID */
 	cpuid(0x0, &cpu_id.max_cpuid, &cpu_id.vend_id.uint32_array[0],
-	    &cpu_id.vend_id.uint32_array[2], &cpu_id.vend_id.uint32_array[1]);
+	      &cpu_id.vend_id.uint32_array[2], &cpu_id.vend_id.uint32_array[1]);
 	cpu_id.vend_id.char_array[11] = 0;
 
 	/* Get processor family information & feature flags */
 	if (cpu_id.max_cpuid >= 1) {
-	    cpuid(0x00000001, &cpu_id.vers.flat, &cpu_id.info.flat,
-		&cpu_id.fid.uint32_array[1], &cpu_id.fid.uint32_array[0]);
+		cpuid(0x00000001, &cpu_id.vers.flat, &cpu_id.info.flat,
+		      &cpu_id.fid.uint32_array[1], &cpu_id.fid.uint32_array[0]);
 	}
 
 	/* Get the digital thermal sensor & power management status bits */
-	if(cpu_id.max_cpuid >= 6)	{
+	if (cpu_id.max_cpuid >= 6) {
 		cpuid(0x00000006, &cpu_id.dts_pmp, &dummy[0], &dummy[1], &dummy[2]);
 	}
 
@@ -35,53 +35,52 @@
 
 	/* Get extended feature flags, only save EDX */
 	if (cpu_id.max_xcpuid >= 0x80000001) {
-	    cpuid(0x80000001, &dummy[0], &dummy[1],
-		&dummy[2], &cpu_id.fid.uint32_array[2]);
+		cpuid(0x80000001, &dummy[0], &dummy[1],
+		      &dummy[2], &cpu_id.fid.uint32_array[2]);
 	}
 
 	/* Get the brand ID */
 	if (cpu_id.max_xcpuid >= 0x80000004) {
-	    v = (unsigned int *)&cpu_id.brand_id;
-	    cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
-	    cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
-	    cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
-	    cpu_id.brand_id.char_array[47] = 0;
+		v = (unsigned int *)&cpu_id.brand_id;
+		cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
+		cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
+		cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
+		cpu_id.brand_id.char_array[47] = 0;
 	}
-        /*
-         * Intel chips right-justify this string for some dumb reason;
-         * undo that brain damage:
-         */
-        p = q = &cpu_id.brand_id.char_array[0];
-        while (*p == ' ')
-                p++;
-        if (p != q) {
-                while (*p)
-                        *q++ = *p++;
-                while (q <= &cpu_id.brand_id.char_array[48])
-                        *q++ = '\0';    /* Zero-pad the rest */
+	/*
+	 * Intel chips right-justify this string for some dumb reason;
+	 * undo that brain damage:
+	 */
+	p = q = &cpu_id.brand_id.char_array[0];
+	while (*p == ' ')
+		p++;
+	if (p != q) {
+		while (*p)
+			*q++ = *p++;
+		while (q <= &cpu_id.brand_id.char_array[48])
+			*q++ = '\0';    /* Zero-pad the rest */
 	}
 
 	/* Get cache information */
-	switch(cpu_id.vend_id.char_array[0]) {
-        case 'A':
-            /* AMD Processors */
-	    /* The cache information is only in ecx and edx so only save
-	     * those registers */
-	    if (cpu_id.max_xcpuid >= 0x80000005) {
-		cpuid(0x80000005, &dummy[0], &dummy[1],
-		    &cpu_id.cache_info.uint[0], &cpu_id.cache_info.uint[1]);
-	    }
-	    if (cpu_id.max_xcpuid >= 0x80000006) {
-		cpuid(0x80000006, &dummy[0], &dummy[1],
-		    &cpu_id.cache_info.uint[2], &cpu_id.cache_info.uint[3]);
-	    }
-	    break;
+	switch (cpu_id.vend_id.char_array[0]) {
+	case 'A':
+		/* AMD Processors */
+		/* The cache information is only in ecx and edx so only save
+		 * those registers */
+		if (cpu_id.max_xcpuid >= 0x80000005) {
+			cpuid(0x80000005, &dummy[0], &dummy[1],
+			      &cpu_id.cache_info.uint[0], &cpu_id.cache_info.uint[1]);
+		}
+		if (cpu_id.max_xcpuid >= 0x80000006) {
+			cpuid(0x80000006, &dummy[0], &dummy[1],
+			      &cpu_id.cache_info.uint[2], &cpu_id.cache_info.uint[3]);
+		}
+		break;
 	case 'G':
-                /* Intel Processors, Need to do this in init.c */
-	    break;
+		/* Intel Processors, Need to do this in init.c */
+		break;
 	}
 
 	/* Turn off mon bit since monitor based spin wait may not be reliable */
 	cpu_id.fid.bits.mon = 0;
-
 }
diff --git a/error.c b/error.c
index 165943f..a063579 100644
--- a/error.c
+++ b/error.c
@@ -33,7 +33,6 @@
  */
 void error(ulong *adr, ulong good, ulong bad)
 {
-
 	ulong xor;
 
 	xor = good ^ bad;
@@ -41,7 +40,7 @@
 #ifdef USB_WAR
 	/* Skip any errrors that appear to be due to the BIOS using location
 	 * 0x4e0 for USB keyboard support.  This often happens with Intel
-   * 810, 815 and 820 chipsets.  It is possible that we will skip
+	 * 810, 815 and 820 chipsets.  It is possible that we will skip
 	 * a real error but the odds are very low.
 	 */
 	if ((ulong)adr == 0x4e0 || (ulong)adr == 0x410) {
@@ -96,18 +95,17 @@
 
 static void update_err_counts(void)
 {
-	if (beepmode){
+	if (beepmode) {
 		beep(600);
 		beep(1000);
 	}
 
 	if (v->pass && v->ecount == 0) {
 		cprint(LINE_MSG, COL_MSG,
-			"                                            ");
+		       "                                            ");
 	}
 	++(v->ecount);
 	tseq[test].errors++;
-
 }
 
 static void print_err_counts(void)
@@ -125,10 +123,10 @@
 	/* Paint the error messages on the screen red to provide a vivid */
 	/* indicator that an error has occured */
 	if ((v->printmode == PRINTMODE_ADDRESSES ||
-			v->printmode == PRINTMODE_PATTERNS) &&
-			v->msg_line < 24) {
-		for(i=0, pp=(char *)((SCREEN_ADR+v->msg_line*160+1));
-				 i<76; i++, pp+=2) {
+	     v->printmode == PRINTMODE_PATTERNS) &&
+	    v->msg_line < 24) {
+		for (i=0, pp=(char *)((SCREEN_ADR+v->msg_line*160+1));
+		     i<76; i++, pp+=2) {
 			*pp = 0x47;
 		}
 	}
@@ -146,7 +144,7 @@
 
 	update_err_counts();
 
-	switch(v->printmode) {
+	switch (v->printmode) {
 	case PRINTMODE_SUMMARY:
 		/* Don't do anything for a parity error. */
 		if (type == 3) {
@@ -177,7 +175,7 @@
 			v->erri.low_addr.offset = offset;
 			flag++;
 		} else if (v->erri.low_addr.page == page &&
-				v->erri.low_addr.offset > offset) {
+		           v->erri.low_addr.offset > offset) {
 			v->erri.low_addr.offset = offset;
 			v->erri.high_addr.offset = offset;
 			flag++;
@@ -186,7 +184,7 @@
 			flag++;
 		}
 		if (v->erri.high_addr.page == page &&
-				v->erri.high_addr.offset < offset) {
+		    v->erri.high_addr.offset < offset) {
 			v->erri.high_addr.offset = offset;
 			flag++;
 		}
@@ -211,10 +209,10 @@
 		}
 		v->erri.ebits |= xor;
 
-	 	/* Calc max contig errors */
+		/* Calc max contig errors */
 		len = 1;
 		if ((ulong)adr == (ulong)v->erri.eadr+4 ||
-				(ulong)adr == (ulong)v->erri.eadr-4 ) {
+		    (ulong)adr == (ulong)v->erri.eadr-4) {
 			len++;
 		}
 		if (len > v->erri.maxl) {
@@ -234,79 +232,79 @@
 			cprint(LINE_HEADER+5, 1,  " Max Contiguous Errors:");
 			x = 24;
 			if (dmi_initialized) {
-			  for ( i=0; i < MAX_DMI_MEMDEVS;){
-			    n = LINE_HEADER+7;
-			    for (j=0; j<4; j++) {
-				if (dmi_err_cnts[i] >= 0) {
-					dprint(n, x, i, 2, 0);
-					cprint(n, x+2, ": 0");
+				for (i=0; i < MAX_DMI_MEMDEVS; ) {
+					n = LINE_HEADER+7;
+					for (j=0; j<4; j++) {
+						if (dmi_err_cnts[i] >= 0) {
+							dprint(n, x, i, 2, 0);
+							cprint(n, x+2, ": 0");
+						}
+						i++;
+						n++;
+					}
+					x += 10;
 				}
-				i++;
-				n++;
-			    }
-			    x += 10;
-			  }
 			}
 
 			cprint(LINE_HEADER+0, 64,   "Test  Errors");
 			v->erri.hdr_flag++;
 		}
 		if (flag) {
-		  /* Calc bits in error */
-		  for (i=0, n=0; i<32; i++) {
-			if (v->erri.ebits>>i & 1) {
-				n++;
-			}
-		  }
-		  page = v->erri.low_addr.page;
-		  offset = v->erri.low_addr.offset;
-		  mb = page >> 8;
-		  hprint(LINE_HEADER+1, 25, page);
-		  hprint2(LINE_HEADER+1, 33, offset, 3);
-		  cprint(LINE_HEADER+1, 36, " -      . MB");
-		  dprint(LINE_HEADER+1, 39, mb, 5, 0);
-		  dprint(LINE_HEADER+1, 45, ((page & 0xF)*10)/16, 1, 0);
-		  page = v->erri.high_addr.page;
-		  offset = v->erri.high_addr.offset;
-		  mb = page >> 8;
-		  hprint(LINE_HEADER+2, 25, page);
-		  hprint2(LINE_HEADER+2, 33, offset, 3);
-		  cprint(LINE_HEADER+2, 36, " -      . MB");
-		  dprint(LINE_HEADER+2, 39, mb, 5, 0);
-		  dprint(LINE_HEADER+2, 45, ((page & 0xF)*10)/16, 1, 0);
-		  hprint(LINE_HEADER+3, 25, v->erri.ebits);
-		  dprint(LINE_HEADER+4, 25, n, 2, 1);
-		  dprint(LINE_HEADER+4, 34, v->erri.min_bits, 2, 1);
-		  dprint(LINE_HEADER+4, 42, v->erri.max_bits, 2, 1);
-		  dprint(LINE_HEADER+4, 50, v->erri.tbits/v->ecount, 2, 1);
-		  dprint(LINE_HEADER+5, 25, v->erri.maxl, 7, 1);
-		  x = 28;
-		  for ( i=0; i < MAX_DMI_MEMDEVS;){
-		  	n = LINE_HEADER+7;
-			for (j=0; j<4; j++) {
-				if (dmi_err_cnts[i] > 0) {
-					dprint (n, x, dmi_err_cnts[i], 7, 1);
+			/* Calc bits in error */
+			for (i=0, n=0; i<32; i++) {
+				if (v->erri.ebits>>i & 1) {
+					n++;
 				}
-				i++;
-				n++;
 			}
-			x += 10;
-		  }
+			page = v->erri.low_addr.page;
+			offset = v->erri.low_addr.offset;
+			mb = page >> 8;
+			hprint(LINE_HEADER+1, 25, page);
+			hprint2(LINE_HEADER+1, 33, offset, 3);
+			cprint(LINE_HEADER+1, 36, " -      . MB");
+			dprint(LINE_HEADER+1, 39, mb, 5, 0);
+			dprint(LINE_HEADER+1, 45, ((page & 0xF)*10)/16, 1, 0);
+			page = v->erri.high_addr.page;
+			offset = v->erri.high_addr.offset;
+			mb = page >> 8;
+			hprint(LINE_HEADER+2, 25, page);
+			hprint2(LINE_HEADER+2, 33, offset, 3);
+			cprint(LINE_HEADER+2, 36, " -      . MB");
+			dprint(LINE_HEADER+2, 39, mb, 5, 0);
+			dprint(LINE_HEADER+2, 45, ((page & 0xF)*10)/16, 1, 0);
+			hprint(LINE_HEADER+3, 25, v->erri.ebits);
+			dprint(LINE_HEADER+4, 25, n, 2, 1);
+			dprint(LINE_HEADER+4, 34, v->erri.min_bits, 2, 1);
+			dprint(LINE_HEADER+4, 42, v->erri.max_bits, 2, 1);
+			dprint(LINE_HEADER+4, 50, v->erri.tbits/v->ecount, 2, 1);
+			dprint(LINE_HEADER+5, 25, v->erri.maxl, 7, 1);
+			x = 28;
+			for (i=0; i < MAX_DMI_MEMDEVS; ) {
+				n = LINE_HEADER+7;
+				for (j=0; j<4; j++) {
+					if (dmi_err_cnts[i] > 0) {
+						dprint (n, x, dmi_err_cnts[i], 7, 1);
+					}
+					i++;
+					n++;
+				}
+				x += 10;
+			}
 
-		  for (i=0; tseq[i].msg != NULL; i++) {
-			dprint(LINE_HEADER+1+i, 66, i, 2, 0);
-			dprint(LINE_HEADER+1+i, 68, tseq[i].errors, 8, 0);
-	  	  }
+			for (i=0; tseq[i].msg != NULL; i++) {
+				dprint(LINE_HEADER+1+i, 66, i, 2, 0);
+				dprint(LINE_HEADER+1+i, 68, tseq[i].errors, 8, 0);
+			}
 		}
 		if (v->erri.cor_err) {
-		  dprint(LINE_HEADER+6, 25, v->erri.cor_err, 8, 1);
+			dprint(LINE_HEADER+6, 25, v->erri.cor_err, 8, 1);
 		}
 		break;
 
 	case PRINTMODE_ADDRESSES:
 		/* Don't display duplicate errors */
 		if ((ulong)adr == (ulong)v->erri.eadr &&
-				 xor == v->erri.exor) {
+		    xor == v->erri.exor) {
 			return;
 		}
 		if (v->erri.hdr_flag == 0) {
@@ -321,7 +319,7 @@
 		check_input();
 		scroll();
 
-		if ( type == 2 || type == 3) {
+		if (type == 2 || type == 3) {
 			page = (ulong)adr;
 			offset = good;
 		} else {
@@ -340,7 +338,7 @@
 		if (type == 3) {
 			/* ECC error */
 			cprint(v->msg_line, 36,
-			  bad?"corrected           ": "uncorrected         ");
+			       bad ? "corrected           " : "uncorrected         ");
 			hprint2(v->msg_line, 60, syn, 4);
 			cprint(v->msg_line, 68, "ECC");
 			dprint(v->msg_line, 74, chan, 2, 0);
@@ -351,7 +349,7 @@
 			hprint(v->msg_line, 46, bad);
 			hprint(v->msg_line, 56, xor);
 			dprint(v->msg_line, 66, v->ecount, 5, 0);
-			dprint(v->msg_line, 74, smp_my_cpu_num(), 2,1);
+			dprint(v->msg_line, 74, smp_my_cpu_num(), 2, 1);
 			v->erri.exor = xor;
 		}
 		v->erri.eadr = (ulong)adr;
@@ -368,7 +366,7 @@
 			return;
 		}
 		/* Only do patterns for data errors */
-		if ( type != 0) {
+		if (type != 0) {
 			return;
 		}
 		/* Process the address in the pattern administration */
@@ -391,7 +389,7 @@
  * Print an ecc error
  */
 void print_ecc_err(unsigned long page, unsigned long offset,
-	int corrected, unsigned short syndrome, int channel)
+                   int corrected, unsigned short syndrome, int channel)
 {
 	++(v->ecc_ecount);
 	syn = syndrome;
@@ -421,41 +419,40 @@
  */
 void printpatn (void)
 {
-       int idx=0;
-       int x;
+	int idx=0;
+	int x;
 
 	/* Check for keyboard input */
 	check_input();
 
-       if (v->numpatn == 0)
-               return;
+	if (v->numpatn == 0)
+		return;
 
-       scroll();
+	scroll();
 
-       cprint (v->msg_line, 0, "badram=");
-       x=7;
+	cprint (v->msg_line, 0, "badram=");
+	x=7;
 
-       for (idx = 0; idx < v->numpatn; idx++) {
-
-               if (x > 80-22) {
-                       scroll();
-                       x=7;
-               }
-               cprint (v->msg_line, x, "0x");
-               hprint (v->msg_line, x+2,  v->patn[idx].adr );
-               cprint (v->msg_line, x+10, ",0x");
-               hprint (v->msg_line, x+13, v->patn[idx].mask);
-               if (idx+1 < v->numpatn)
-                       cprint (v->msg_line, x+21, ",");
-               x+=22;
-       }
+	for (idx = 0; idx < v->numpatn; idx++) {
+		if (x > 80-22) {
+			scroll();
+			x=7;
+		}
+		cprint (v->msg_line, x, "0x");
+		hprint (v->msg_line, x+2,  v->patn[idx].adr );
+		cprint (v->msg_line, x+10, ",0x");
+		hprint (v->msg_line, x+13, v->patn[idx].mask);
+		if (idx+1 < v->numpatn)
+			cprint (v->msg_line, x+21, ",");
+		x+=22;
+	}
 }
 
 /*
  * Show progress by displaying elapsed time and update bar graphs
  */
 short spin_idx[MAX_CPUS];
-char spin[4] = {'|','/','-','\\'};
+char spin[4] = {'|', '/', '-', '\\'};
 
 void do_tick(int me)
 {
@@ -515,7 +512,7 @@
 		}
 	} else {
 		pct = 0;
-        }
+	}
 	dprint(1, COL_MID+4, pct, 3, 0);
 	i = (BAR_SIZE * pct) / 100;
 	while (i > v->pptr) {
@@ -533,7 +530,7 @@
 		/* If there are no errors within 1mb of start - end addresses */
 		h = v->pmap[v->msegs - 1].end - 0x100;
 		if (v->erri.low_addr.page >  0x100 &&
-				 v->erri.high_addr.page < h) {
+		    v->erri.high_addr.page < h) {
 			pct += 8;
 		}
 
@@ -552,7 +549,6 @@
 				}
 			}
 			pct += n*2;
-
 		}
 
 		/* Only some bits in error */
@@ -582,22 +578,20 @@
 	 * is supported
 	 */
 	if (cpu_id.fid.bits.rdtsc) {
-		asm __volatile__(
-			"rdtsc":"=a" (l),"=d" (h));
+		asm __volatile__ (
+			"rdtsc" : "=a" (l), "=d" (h));
 		asm __volatile__ (
 			"subl %2,%0\n\t"
 			"sbbl %3,%1"
-			:"=a" (l), "=d" (h)
-			:"g" (v->startl), "g" (v->starth),
-			"0" (l), "1" (h));
+			: "=a" (l), "=d" (h)
+			: "g" (v->startl), "g" (v->starth),
+			  "0" (l), "1" (h));
 		t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000;
 		t += (l / v->clks_msec) / 1000;
 		i = t % 60;
 		j = i % 10;
 
-		if(j != v->each_sec)
-		{
-
+		if (j != v->each_sec) {
 			dprint(LINE_TIME, COL_TIME+9, i % 10, 1, 0);
 			dprint(LINE_TIME, COL_TIME+8, i / 10, 1, 0);
 			t /= 60;
@@ -607,13 +601,11 @@
 			t /= 60;
 			dprint(LINE_TIME, COL_TIME, t, 4, 0);
 
-			if(v->check_temp > 0 && !(v->fail_safe & 4))
-				{
-					coretemp();
-				}
+			if (v->check_temp > 0 && !(v->fail_safe & 4)) {
+				coretemp();
+			}
 			v->each_sec = j;
 		}
-
 	}
 
 
diff --git a/extra.c b/extra.c
index ff580f2..f837da9 100644
--- a/extra.c
+++ b/extra.c
@@ -17,25 +17,24 @@
 struct memory_controller {
 	unsigned vendor;
 	unsigned device;
-	int worked;
-	void (*change_timing)(int cas, int rcd, int rp, int ras);
+	int      worked;
+	void     (*change_timing)(int cas, int rcd, int rp, int ras);
 };
 
 static struct memory_controller mem_ctr[] = {
-
 	/* AMD 64*/
-	{ 0x1022, 0x1100,  1, change_timing_amd64}, //AMD64 hypertransport link
+	{ 0x1022, 0x1100, 1, change_timing_amd64 }, //AMD64 hypertransport link
 
 	/* nVidia */
-	{ 0x10de, 0x01E0,  0, change_timing_nf2},  // nforce2
+	{ 0x10de, 0x01E0, 0, change_timing_nf2   }, // nforce2
 
 	/* Intel */
-	{ 0x8086, 0x2570,  0, change_timing_i875}, //Intel i848/i865
-	{ 0x8086, 0x2578,  0, change_timing_i875}, //Intel i875P
-	{ 0x8086, 0x2580,  0, change_timing_i925}, //Intel i915P/G
-	{ 0x8086, 0x2584,  0, change_timing_i925}, //Intel i925X
-	{ 0x8086, 0x2770,  0, change_timing_i925}, //Intel Lakeport
-	{ 0x8086, 0x3580,  0, change_timing_i852}, //Intel i852GM - i855GM/GME (But not i855PM)
+	{ 0x8086, 0x2570, 0, change_timing_i875  }, //Intel i848/i865
+	{ 0x8086, 0x2578, 0, change_timing_i875  }, //Intel i875P
+	{ 0x8086, 0x2580, 0, change_timing_i925  }, //Intel i915P/G
+	{ 0x8086, 0x2584, 0, change_timing_i925  }, //Intel i925X
+	{ 0x8086, 0x2770, 0, change_timing_i925  }, //Intel Lakeport
+	{ 0x8086, 0x3580, 0, change_timing_i852  }, //Intel i852GM - i855GM/GME (But not i855PM)
 };
 
 struct drc {
@@ -64,16 +63,15 @@
 
 	pci_conf_read(0, 24, 0, 0x00, 4, &a64);
 
-	if( a64 == 0x11001022) 	{
+	if (a64 == 0x11001022) {
 		ctrl = 0;
 		return;
 	}
 
 	if (result == 0) {
-		for(i = 1; i < sizeof(mem_ctr)/sizeof(mem_ctr[0]); i++) {
+		for (i = 1; i < sizeof(mem_ctr)/sizeof(mem_ctr[0]); i++) {
 			if ((mem_ctr[i].vendor == vendor) &&
-				(mem_ctr[i].device == device))
-			{
+			    (mem_ctr[i].device == device)) {
 				ctrl = i;
 				return;
 			}
@@ -84,25 +82,21 @@
 
 void a64_parameter(void)
 {
-
 	ulong dramtlr;
 
-	if ( 0 == pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr) )
-	{
+	if (0 == pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr) ) {
 		a64.t_rct = 7 + ((dramtlr>>4) & 0x0F);
 		a64.t_rrd = 0 + ((dramtlr>>16) & 0x7);
 		a64.t_wr  = 2 + ((dramtlr>>28) & 0x1);
 	}
 
-	if ( 0 == pci_conf_read(0, 24, 2, 0x8C, 4, &dramtlr) )
-	{
+	if (0 == pci_conf_read(0, 24, 2, 0x8C, 4, &dramtlr) ) {
 		a64.t_rwt = 1 + ((dramtlr>>4) & 0x07);
 		a64.t_wrt = 1 +  (dramtlr      & 0x1);
 		a64.t_ref = 1 + ((dramtlr>>11) & 0x3);
 	}
 
-	if ( 0 == pci_conf_read(0, 24, 2, 0x90, 4, &dramtlr) )
-	{
+	if (0 == pci_conf_read(0, 24, 2, 0x90, 4, &dramtlr) ) {
 		a64.t_en2t = 1 + ((dramtlr>>28) & 0x1);
 		a64.t_rwqb = 2 << ((dramtlr>>14) & 0x3);
 	}
@@ -113,8 +107,7 @@
 void change_timing(int cas, int rcd, int rp, int ras)
 {
 	find_memctr();
-	if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0])))
-	{
+	if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0]))) {
 		return;
 	}
 
@@ -126,13 +119,11 @@
 {
 	int rwt=0, wrt=0, ref=0, en2t=0, rct=0, rrd=0, rwqb=0, wr = 0, flag=0;
 
-	if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0])))
-	{
+	if ((ctrl == -1) || ( ctrl > sizeof(mem_ctr)/sizeof(mem_ctr[0]))) {
 		return;
 	}
 
-	if (mem_ctr[ctrl].worked)
-	{
+	if (mem_ctr[ctrl].worked) {
 		a64_parameter();
 		cprint(POP_Y+1, POP_X+4, "AMD64 options");
 
@@ -146,11 +137,10 @@
 		dprint(POP_Y+5, POP_X+24, a64.t_rwqb, 2, 0);
 
 		cprint(POP_Y+6, POP_X+4, "(4) Refresh Rate  : ");
-		switch ( a64.t_ref)
-		{
-		case 1 : cprint(POP_Y+6, POP_X+23, "15.6us"); break;
-		case 2 : cprint(POP_Y+6, POP_X+23, " 7.8us"); break;
-		case 3 : cprint(POP_Y+6, POP_X+23, " 3.9us"); break;
+		switch (a64.t_ref) {
+		case 1: cprint(POP_Y+6, POP_X+23, "15.6us"); break;
+		case 2: cprint(POP_Y+6, POP_X+23, " 7.8us"); break;
+		case 3: cprint(POP_Y+6, POP_X+23, " 3.9us"); break;
 		}
 		cprint(POP_Y+7, POP_X+4,  "(5) Command Rate  :");
 		dprint(POP_Y+7, POP_X+24, a64.t_en2t, 2, 0);
@@ -165,12 +155,11 @@
 		cprint(POP_Y+10, POP_X+4, "(8) Write Recovery: ");
 		dprint(POP_Y+10, POP_X+24, a64.t_wr, 2, 0);
 
-		cprint(POP_Y+11, POP_X+4,"(0) Cancel   ");
+		cprint(POP_Y+11, POP_X+4, "(0) Cancel   ");
 
-		while(!flag)
+		while (!flag)
 		{
-			switch(get_key())
-			{
+			switch (get_key()) {
 			case 2:
 				popclear();
 				// read-to-write delay
@@ -180,7 +169,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_rwt, 4, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				rwt = getval(POP_Y+7, POP_X+12, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 3:
@@ -192,7 +181,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_wrt, 4, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				wrt = getval(POP_Y+7, POP_X+12, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 4:
@@ -204,7 +193,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_rwqb, 2, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				rwqb = getval(POP_Y+7, POP_X+11, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 5:
@@ -212,17 +201,17 @@
 				// refresh rate
 				cprint(POP_Y+3, POP_X+4, "Refresh rate ");
 				cprint(POP_Y+4, POP_X+4, "Current: ");
-				switch ( a64.t_ref){
-				case 1 : cprint(POP_Y+4, POP_X+14, "15.6us"); break;
-				case 2 : cprint(POP_Y+4, POP_X+14, "7.8us "); break;
-				case 3 : cprint(POP_Y+4, POP_X+14, "3.9us "); break;
+				switch (a64.t_ref) {
+				case 1: cprint(POP_Y+4, POP_X+14, "15.6us"); break;
+				case 2: cprint(POP_Y+4, POP_X+14, "7.8us "); break;
+				case 3: cprint(POP_Y+4, POP_X+14, "3.9us "); break;
 				}
 				cprint(POP_Y+6, POP_X+4, "New: ");
 				cprint(POP_Y+7, POP_X+4, "(1) 15.6us");
 				cprint(POP_Y+8, POP_X+4, "(2) 7.8us ");
 				cprint(POP_Y+9, POP_X+4, "(3) 3.9us ");
 				ref = getval(POP_Y+6, POP_X+11, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 6:
@@ -232,7 +221,7 @@
 				cprint(POP_Y+5, POP_X+4, "(1) 1T "); //only supoprted by CG revision and later
 				cprint(POP_Y+6, POP_X+4, "(2) 2T ");
 				en2t = getval(POP_Y+3, POP_X+22, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 7:
@@ -244,7 +233,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_rct, 4, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				rct = getval(POP_Y+7, POP_X+12, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 8:
@@ -256,7 +245,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_rrd, 2, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				rrd = getval(POP_Y+7, POP_X+12, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 9:
@@ -268,7 +257,7 @@
 				dprint(POP_Y+5, POP_X+14, a64.t_wr, 2, 0);
 				cprint(POP_Y+7, POP_X+4, "New: ");
 				wr = getval(POP_Y+7, POP_X+12, 0);
-				amd64_tweak(rwt, wrt, ref,en2t, rct, rrd, rwqb, wr);
+				amd64_tweak(rwt, wrt, ref, en2t, rct, rrd, rwqb, wr);
 				break;
 
 			case 11:
@@ -283,12 +272,11 @@
 
 void get_option()
 {
-	int cas =0, rp=0, rcd=0, ras=0, sflag = 0 ;
+	int cas =0, rp=0, rcd=0, ras=0, sflag = 0;
 
-	while(!sflag)
+	while (!sflag)
 	{
-		switch(get_key())
-		{
+		switch (get_key()) {
 		case 2:
 			popclear();
 			cas = get_cas();
@@ -360,12 +348,11 @@
 
 void get_option_1()
 {
-	int rp=0, rcd=0, ras=0, sflag = 0 ;
+	int rp=0, rcd=0, ras=0, sflag = 0;
 
-	while(!sflag)
+	while (!sflag)
 	{
-		switch(get_key())
-		{
+		switch (get_key()) {
 		case 2:
 			popclear();
 			cprint(POP_Y+3, POP_X+8, "tRCD: ");
@@ -425,28 +412,24 @@
 
 void get_menu(void)
 {
-	int menu ;
+	int menu;
 
 	find_memctr();
 
-	switch(ctrl)
-	{
-	case 0: menu = 2;	break;
+	switch (ctrl) {
+	case 0: menu = 2; break;
 	case 1:
 	case 2:
 	case 3:
-	case 4:	menu = 0;	break;
-	case 5: menu = 1;	break;
-	case 6: menu = 0;	break;
-	default: menu = -1;	break;
+	case 4: menu = 0; break;
+	case 5: menu = 1; break;
+	case 6: menu = 0; break;
+	default: menu = -1; break;
 	}
 
-	if (menu == -1)
-	{
+	if (menu == -1) {
 		popclear();
-	}
-	else if (menu == 0)
-	{
+	} else if (menu == 0) {
 		cprint(POP_Y+1, POP_X+2, "Modify Timing:");
 		cprint(POP_Y+3, POP_X+5, "(1) Modify All   ");
 		cprint(POP_Y+4, POP_X+5, "(2) Modify tCAS  ");
@@ -455,10 +438,8 @@
 		cprint(POP_Y+7, POP_X+5, "(5) Modify tRAS  ");
 		cprint(POP_Y+8, POP_X+5, "(0) Cancel");
 		wait_keyup();
-	 	get_option();
-	}
-	else if (menu == 1)
-	{
+		get_option();
+	} else if (menu == 1) {
 		cprint(POP_Y+1, POP_X+2, "Modify Timing:");
 		cprint(POP_Y+3, POP_X+5, "(1) Modify All   ");
 		cprint(POP_Y+4, POP_X+5, "(2) Modify tRCD  ");
@@ -466,10 +447,8 @@
 		cprint(POP_Y+6, POP_X+5, "(4) Modify tRAS  ");
 		cprint(POP_Y+7, POP_X+5, "(0) Cancel");
 		wait_keyup();
-	 	get_option();
-	}
-	else  // AMD64 special menu
-	{
+		get_option();
+	} else { // AMD64 special menu
 		cprint(POP_Y+1, POP_X+2, "Modify Timing:");
 		cprint(POP_Y+3, POP_X+5, "(1) Modify All   ");
 		cprint(POP_Y+4, POP_X+5, "(2) Modify tRCD  ");
@@ -478,7 +457,7 @@
 		cprint(POP_Y+7, POP_X+5, "(5) AMD64 Options");
 		cprint(POP_Y+8, POP_X+5, "(0) Cancel");
 		wait_keyup();
-	 	get_option_1();
+		get_option_1();
 	}
 }
 
@@ -488,12 +467,11 @@
 	ulong drc, ddr;
 	long *ptr;
 
-	switch(ctrl)
-	{
+	switch (ctrl) {
 	case 0: ddr = 1; break;
 	case 1:
 	case 2:
-	case 3:	ddr = 1; break;
+	case 3: ddr = 1; break;
 	case 4:
 		pci_conf_read( 0, 0, 0, 0x44, 4, &ddr);
 		ddr &= 0xFFFFC000;
@@ -508,26 +486,21 @@
 	default: ddr = 1;
 	}
 
-	if (ddr == 1)
-	{
+	if (ddr == 1) {
 		cprint(POP_Y+3, POP_X+8, "tCAS:  ");
 		cprint(POP_Y+5, POP_X+8, "(1) CAS 2.5 ");
 		cprint(POP_Y+6, POP_X+8, "(2) CAS 2   ");
-		if(!i852) {
+		if (!i852) {
 			cprint(POP_Y+7, POP_X+8, "(3) CAS 3   ");
 		}
 		cas = getval(POP_Y+3, POP_X+15, 0);
-	}
-	else if (ddr == 2)
-	{
+	} else if (ddr == 2) {
 		cprint(POP_Y+3, POP_X+8, "tCAS:  ");
 		cprint(POP_Y+5, POP_X+8, "(1) CAS 4 ");
 		cprint(POP_Y+6, POP_X+8, "(2) CAS 3 ");
 		cprint(POP_Y+7, POP_X+8, "(3) CAS 5 ");
 		cas = getval(POP_Y+3, POP_X+15, 0);
-	}
-	else
-	{
+	} else {
 		cas = -1;
 	}
 
@@ -539,8 +512,8 @@
 // here we go for the exciting timing change part...   //
 /////////////////////////////////////////////////////////
 
-void change_timing_i852(int cas, int rcd, int rp, int ras) {
-
+void change_timing_i852(int cas, int rcd, int rp, int ras)
+{
 	ulong dramtlr;
 	ulong int1, int2;
 
@@ -550,7 +523,7 @@
 	int1 = dramtlr & 0xFF9F;
 	if      (cas == 2) { int2 = int1 ^ 0x20; }
 	else if (cas == 1) { int2 = int1; }
-	else		   { int2 = dramtlr; }
+	else               { int2 = dramtlr; }
 
 
 	// RAS-To-CAS (tRCD)
@@ -558,7 +531,7 @@
 	if      (rcd == 2) { int2 = int1 ^ 0x8; }
 	else if (rcd == 3) { int2 = int1 ^ 0x4; }
 	else if (rcd == 4) { int2 = int1; }
-	// else		   { int2 = int2; }
+	// else            { int2 = int2; }
 
 
 	// RAS Precharge (tRP)
@@ -566,16 +539,16 @@
 	if      (rp == 2) { int2 = int1 ^ 0x2; }
 	else if (rp == 3) { int2 = int1 ^ 0x1; }
 	else if (rp == 4) { int2 = int1; }
-	// else		  { int2 = int2; }
+	// else           { int2 = int2; }
 
 
 	// RAS Active to precharge (tRAS)
 	int1 = int2 & 0xF9FF;
-	if      (ras == 5)  { int2 = int1 ^ 0x0600; }
-	else if (ras == 6)  { int2 = int1 ^ 0x0400; }
-	else if (ras == 7)  { int2 = int1 ^ 0x0200; }
-	else if (ras == 8)  { int2 = int1; }
-	// else		    { int2 = int2; }
+	if      (ras == 5) { int2 = int1 ^ 0x0600; }
+	else if (ras == 6) { int2 = int1 ^ 0x0400; }
+	else if (ras == 7) { int2 = int1 ^ 0x0200; }
+	else if (ras == 8) { int2 = int1; }
+	// else            { int2 = int2; }
 
 	pci_conf_write(0, 0, 1, 0x60, 4, int2);
 	__delay(500);
@@ -599,7 +572,7 @@
 	else if (rcd == 3) { temp = int1 ^ 0x60; }
 	else if (rcd == 4) { temp = int1 ^ 0x50; }
 	else if (rcd == 5) { temp = int1 ^ 0x40; }
-	// else		   { temp = temp;}
+	// else            { temp = temp; }
 
 	//RAS precharge (tRP)
 	int1 = temp | 0x7;
@@ -607,12 +580,11 @@
 	else if (rp == 3) { temp = int1 ^ 0x6; }
 	else if (rp == 4) { temp = int1 ^ 0x5; }
 	else if (rp == 5) { temp = int1 ^ 0x4; }
-	// else		  { temp = temp;}
+	// else           { temp = temp; }
 
-	if (mem_ctr[ctrl].device == 0x2770 )	// Lakeport?
-	{
+	if (mem_ctr[ctrl].device == 0x2770) {   // Lakeport?
 		// RAS Active to precharge (tRAS)
-		int1 = temp | 0xF80000;	// bits 23:19
+		int1 = temp | 0xF80000; // bits 23:19
 		if      (ras == 4)  { temp = int1 ^ 0xD80000; }
 		else if (ras == 5)  { temp = int1 ^ 0xD00000; }
 		else if (ras == 6)  { temp = int1 ^ 0xC80000; }
@@ -625,12 +597,10 @@
 		else if (ras == 13) { temp = int1 ^ 0x900000; }
 		else if (ras == 14) { temp = int1 ^ 0x880000; }
 		else if (ras == 15) { temp = int1 ^ 0x800000; }
-		// else		    { temp = temp;}
-	}
-	else
-	{
+		// else             { temp = temp; }
+	} else {
 		// RAS Active to precharge (tRAS)
-		int1 = temp | 0xF00000;	// bits 23:20
+		int1 = temp | 0xF00000; // bits 23:20
 		if      (ras == 4)  { temp = int1 ^ 0xB00000; }
 		else if (ras == 5)  { temp = int1 ^ 0xA00000; }
 		else if (ras == 6)  { temp = int1 ^ 0x900000; }
@@ -643,7 +613,7 @@
 		else if (ras == 13) { temp = int1 ^ 0x200000; }
 		else if (ras == 14) { temp = int1 ^ 0x100000; }
 		else if (ras == 15) { temp = int1 ^ 0x000000; }
-		// else		    { temp = temp;}
+		// else		    { temp = temp; }
 	}
 
 	// CAS Latency (tCAS)
@@ -651,7 +621,7 @@
 	if      (cas == 1) { temp = int1 ^ 0x200; }   // cas 2.5
 	else if (cas == 2) { temp = int1 ^ 0x100; }
 	else if (cas == 3) { temp = int1 ^ 0x300; }
-	// else		   { temp = temp;}
+	// else            { temp = temp; }
 
 	*ptr = temp;
 	__delay(500);
@@ -676,7 +646,7 @@
 	else if (rcd == 3) { temp = int1 ^ 0x60; }
 	else if (rcd == 4) { temp = int1 ^ 0x50; }
 	else if (rcd == 5) { temp = int1 ^ 0x40; }
-	// else		   { temp = temp;}
+	// else            { temp = temp; }
 
 	//RAS precharge (tRP)
 	int1 = temp | 0x7;
@@ -684,7 +654,7 @@
 	else if (rp == 3) { temp = int1 ^ 0x6; }
 	else if (rp == 4) { temp = int1 ^ 0x5; }
 	else if (rp == 5) { temp = int1 ^ 0x4; }
-	// else		  { temp = temp;}
+	// else           { temp = temp; }
 
 
 	// CAS Latency (tCAS)
@@ -692,15 +662,15 @@
 	if      (cas == 1) { temp = int1 ^ 0x200; }   // cas 2.5
 	else if (cas == 2) { temp = int1 ^ 0x100; }
 	else if (cas == 3) { temp = int1 ^ 0x300; }
-	// else		   { temp = temp;}
+	// else            { temp = temp; }
 
 	*ptr = temp;
 	__delay(500);
 	return;
 }
 
-void change_timing_i875(int cas, int rcd, int rp, int ras){
-
+void change_timing_i875(int cas, int rcd, int rp, int ras)
+{
 	ulong int1, dev6, temp;
 	long *ptr;
 
@@ -717,7 +687,7 @@
 	else if (rcd == 3) { temp = int1 ^ 0x8; }
 	else if (rcd == 4) { temp = int1 ^ 0xC; }
 	else if (rcd == 5) { temp = int1 ^ 0xC; }
-	// else		   { temp = temp;}
+	// else            { temp = temp; }
 
 
 	//RAS precharge (tRP)
@@ -726,7 +696,7 @@
 	else if (rp == 3) { temp = int1 ^ 0x2; }
 	else if (rp == 4) { temp = int1 ^ 0x3; }
 	else if (rp == 5) { temp = int1 ^ 0x3; }
-	// else		  { temp = temp;}
+	// else           { temp = temp; }
 
 
 	// RAS Active to precharge (tRAS)
@@ -737,14 +707,14 @@
 	else if (ras == 8)  { temp = int1 ^ 0x280; }
 	else if (ras == 9)  { temp = int1 ^ 0x300; }
 	else if (ras == 10) { temp = int1 ^ 0x380; }
-	// else		    { temp = temp;}
+	// else             { temp = temp; }
 
 	// CAS Latency (tCAS)
 	int1 = temp | 0x60;
 	if      (cas == 1) { temp = int1 ^ 0x60; }   // cas 2.5
 	else if (cas == 2) { temp = int1 ^ 0x40; }
 	else if (cas == 3) { temp = int1 ^ 0x20; }
-	// else		   { temp = temp; }
+	// else            { temp = temp; }
 
 	*ptr = temp;
 	__delay(500);
@@ -752,8 +722,8 @@
 }
 
 
-void change_timing_nf2(int cas, int rcd, int rp, int ras) {
-
+void change_timing_nf2(int cas, int rcd, int rp, int ras)
+{
 	ulong dramtlr, dramtlr2;
 	ulong int1, int2;
 
@@ -766,7 +736,7 @@
 	if      (cas == 1) { int2 = int1 ^ 0x10; }  // cas = 2.5
 	else if (cas == 2) { int2 = int1 ^ 0x50; }
 	else if (cas == 3) { int2 = int1 ^ 0x40; }
-	else		   { int2 = dramtlr2; }
+	else               { int2 = dramtlr2; }
 
 	pci_conf_write(0, 0, 1, 0xA0, 4, int2);
 
@@ -778,7 +748,7 @@
 	else if (rcd == 4) { int2 = int1 ^ 0x300000; }
 	else if (rcd == 5) { int2 = int1 ^ 0x200000; }
 	else if (rcd == 6) { int2 = int1 ^ 0x100000; }
-	else		   { int2 = dramtlr;}
+	else               { int2 = dramtlr; }
 
 
 	// RAS Precharge (tRP)
@@ -788,7 +758,7 @@
 	else if (rp == 4) { int2 = int1 ^ 0x30000000; }
 	else if (rp == 5) { int2 = int1 ^ 0x20000000; }
 	else if (rp == 6) { int2 = int1 ^ 0x10000000; }
-	// else		  { int2 = int2;}
+	// else           { int2 = int2; }
 
 
 	// RAS Active to precharge (tRAS)
@@ -805,7 +775,7 @@
 	else if (ras == 12) { int2 = int1 ^ 0x18000; }
 	else if (ras == 13) { int2 = int1 ^ 0x10000; }
 	else if (ras == 14) { int2 = int1 ^ 0x08000; }
-	// else		    { int2 = int2;}
+	// else             { int2 = int2; }
 
 
 	pci_conf_write(0, 0, 1, 0x90, 4, int2);
@@ -813,8 +783,8 @@
 }
 
 
-void change_timing_amd64(int cas, int rcd, int rp, int ras) {
-
+void change_timing_amd64(int cas, int rcd, int rp, int ras)
+{
 	ulong dramtlr;
 	ulong int1= 0x0;
 
@@ -828,7 +798,7 @@
 	else if (rcd == 5) { dramtlr = int1 ^ 0x2000; }
 	else if (rcd == 6) { dramtlr = int1 ^ 0x1000; }
 	else if (rcd == 1) { dramtlr = int1 ^ 0x6000; }
-	// else		   { dramtlr = dramtlr;}
+	// else            { dramtlr = dramtlr; }
 
 
 	//RAS precharge (tRP)
@@ -839,7 +809,7 @@
 	else if (rp == 4) { dramtlr = int1 ^ 0x3000000; }
 	else if (rp == 5) { dramtlr = int1 ^ 0x2000000; }
 	else if (rp == 6) { dramtlr = int1 ^ 0x1000000; }
-	// else		  { dramtlr = dramtlr;}
+	// else           { dramtlr = dramtlr; }
 
 
 	// RAS Active to precharge (tRAS)
@@ -854,16 +824,16 @@
 	else if (ras == 12) { dramtlr = int1 ^ 0x300000; }
 	else if (ras == 13) { dramtlr = int1 ^ 0x200000; }
 	else if (ras == 14) { dramtlr = int1 ^ 0x100000; }
-	// else		    { dramtlr = dramtlr;}
+	// else             { dramtlr = dramtlr; }
 
 
 	// CAS Latency (tCAS)
-	int1 = dramtlr | 0x7;	// some changes will cause the system hang, tried Draminit to no avail
-	if      (cas == 1) { dramtlr = int1 ^ 0x2; }   // cas 2.5
+	int1 = dramtlr | 0x7; // some changes will cause the system hang, tried Draminit to no avail
+	if      (cas == 1) { dramtlr = int1 ^ 0x2; } // cas 2.5
 	else if (cas == 2) { dramtlr = int1 ^ 0x6; }
 	else if (cas == 3) { dramtlr = int1 ^ 0x5; }
 	else if (cas == 4) { dramtlr = int1 ^ 0x7; } //cas 1.5 on a64
-	// else		   { dramtlr = dramtlr; }
+	// else            { dramtlr = dramtlr; }
 
 //	pci_conf_read(0, 24, 2, 0x90, 4, &dramcr);// use dram init
 	pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
@@ -877,14 +847,14 @@
 void __delay(ulong loops)
 {
 	int d0;
-	__asm__ __volatile__(
+	__asm__ __volatile__ (
 		"\tjmp 1f\n"
 		".align 16\n"
 		"1:\tjmp 2f\n"
 		".align 16\n"
 		"2:\tdecl %0\n\tjns 2b"
-		:"=&a" (d0)
-		:"0" (loops));
+		: "=&a" (d0)
+		: "0" (loops));
 }
 
 void amd64_tweak(int rwt, int wrt, int ref, int en2t, int rct, int rrd, int rwqb, int wr)
@@ -896,9 +866,9 @@
 
 	// Row Cycle time
 	int1 = dramtlr | 0xF0;
-	if      (rct == 7 ) { dramtlr = int1 ^ 0xF0; }
-	else if (rct == 8 ) { dramtlr = int1 ^ 0xE0; }
-	else if (rct == 9 ) { dramtlr = int1 ^ 0xD0; }
+	if      (rct == 7)  { dramtlr = int1 ^ 0xF0; }
+	else if (rct == 8)  { dramtlr = int1 ^ 0xE0; }
+	else if (rct == 9)  { dramtlr = int1 ^ 0xD0; }
 	else if (rct == 10) { dramtlr = int1 ^ 0xC0; }
 	else if (rct == 11) { dramtlr = int1 ^ 0xB0; }
 	else if (rct == 12) { dramtlr = int1 ^ 0xA0; }
@@ -910,20 +880,20 @@
 	else if (rct == 18) { dramtlr = int1 ^ 0x40; }
 	else if (rct == 19) { dramtlr = int1 ^ 0x30; }
 	else if (rct == 20) { dramtlr = int1 ^ 0x20; }
-	// else		    { dramtlr = dramtlr;}
+	// else             { dramtlr = dramtlr; }
 
 	//Active-avtive ras-ras delay
 	int1 = dramtlr | 0x70000;
 	if      (rrd == 2) { dramtlr = int1 ^ 0x50000; } // 2 bus clocks
 	else if (rrd == 3) { dramtlr = int1 ^ 0x40000; } // 3 bus clocks
 	else if (rrd == 4) { dramtlr = int1 ^ 0x30000; } // 4 bus clocks
-	// else		   { dramtlr = dramtlr;}
+	// else            { dramtlr = dramtlr; }
 
 	//Write recovery time
 	int1 = dramtlr | 0x10000000;
 	if      (wr == 2) { dramtlr = int1 ^ 0x10000000; } // 2 bus clocks
 	else if (wr == 3) { dramtlr = int1 ^ 0x00000000; } // 3 bus clocks
-	// else		  { dramtlr = dramtlr;}
+	// else           { dramtlr = dramtlr; }
 
 	pci_conf_write(0, 24, 2, 0x88, 4, dramtlr);
 	__delay(500);
@@ -935,7 +905,7 @@
 	int1 = dramtlr | 0x1;
 	if      (wrt == 2) { dramtlr = int1 ^ 0x0; }
 	else if (wrt == 1) { dramtlr = int1 ^ 0x1; }
-	// else		   { dramtlr = dramtlr;}
+	// else            { dramtlr = dramtlr; }
 
 	// Read-to Write delay
 	int1 = dramtlr | 0x70;
@@ -945,14 +915,14 @@
 	else if (rwt == 4) { dramtlr = int1 ^ 0x40; }
 	else if (rwt == 5) { dramtlr = int1 ^ 0x30; }
 	else if (rwt == 6) { dramtlr = int1 ^ 0x20; }
-	// else		   { dramtlr = dramtlr;}
+	// else            { dramtlr = dramtlr; }
 
 	//Refresh Rate
 	int1 = dramtlr | 0x1800;
 	if      (ref == 1) { dramtlr = int1 ^ 0x1800; } // 15.6us
 	else if (ref == 2) { dramtlr = int1 ^ 0x1000; } // 7.8us
 	else if (ref == 3) { dramtlr = int1 ^ 0x0800; } // 3.9us
-	// else		   { dramtlr = dramtlr;}
+	// else            { dramtlr = dramtlr; }
 
 	pci_conf_write(0, 24, 2, 0x8c, 4, dramtlr);
 	__delay(500);
@@ -964,7 +934,7 @@
 	int1 = dramtlr | 0x10000000;
 	if      (en2t == 2) { dramtlr = int1 ^ 0x00000000; } // 2T
 	else if (en2t == 1) { dramtlr = int1 ^ 0x10000000; } // 1T
-	// else		    { dramtlr = dramtlr;}
+	// else             { dramtlr = dramtlr; }
 
 	// Read Write queue bypass count
 	int1 = dramtlr | 0xC000;
@@ -972,10 +942,9 @@
 	else if (rwqb == 4)  { dramtlr = int1 ^ 0x8000; }
 	else if (rwqb == 8)  { dramtlr = int1 ^ 0x4000; }
 	else if (rwqb == 16) { dramtlr = int1 ^ 0x0000; }
-	// else		     { dramtlr = dramtlr;}
+	// else              { dramtlr = dramtlr; }
 
 	pci_conf_write(0, 24, 2, 0x90, 4, dramtlr);
 	__delay(500);
 	restart();
 }
-
diff --git a/init.c b/init.c
index 40c42a6..18f5299 100644
--- a/init.c
+++ b/init.c
@@ -63,76 +63,70 @@
 	unsigned char c;
 	volatile char *pp;
 
-	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
 		*pp = 0x1E;
 	}
-	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<3; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<3; i++, pp+=2) {
 		*pp = 0x9E;
 	}
-	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(55*2)+1); i<3; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+(18*160)+(55*2)+1); i<3; i++, pp+=2) {
 		*pp = 0x9E;
 	}
 
 	cprint(18, 18, "==> Press F1 to enter Fail-Safe Mode <==");
 
-	if(v->fail_safe & 2)
-	{
-	cprint(19, 15, "==> Press F2 to force Multi-Threading (SMP) <==");
+	if (v->fail_safe & 2) {
+		cprint(19, 15, "==> Press F2 to force Multi-Threading (SMP) <==");
 	}
 
 	/* save the starting time */
-	asm __volatile__(
-		"rdtsc":"=a" (sl),"=d" (sh));
+	asm __volatile__ (
+		"rdtsc" : "=a" (sl), "=d" (sh));
 
 	/* loop for n seconds */
 	while (1) {
-		asm __volatile__(
-			"rdtsc":"=a" (l),"=d" (h));
+		asm __volatile__ (
+			"rdtsc" : "=a" (l), "=d" (h));
 		asm __volatile__ (
 			"subl %2,%0\n\t"
 			"sbbl %3,%1"
-			:"=a" (l), "=d" (h)
-			:"g" (sl), "g" (sh),
-			"0" (l), "1" (h));
+			: "=a" (l), "=d" (h)
+			: "g" (sl), "g" (sh),
+			  "0" (l), "1" (h));
 
 		t = h * ((unsigned)0xffffffff / v->clks_msec);
 		t += (l / v->clks_msec);
 
 		/* Is the time up? */
-		if (t >= msec) { break;	}
+		if (t >= msec) { break; }
 
 		/* Is expected Scan code pressed? */
 		c = get_key();
 		c &= 0x7f;
 
 		/* F1 */
-		if(c == scs) { v->fail_safe |= 1;	break; }
+		if (c == scs) { v->fail_safe |= 1; break; }
 
 		/* F2 */
-		if(c == scs+1)
-		{
+		if (c == scs+1) {
 			v->fail_safe ^= 2;
 			break;
-
 		}
 
 		/* F3 */
-		if(c == scs+2)
-		{
-			if(v->fail_safe & 2) { v->fail_safe ^= 2; }
+		if (c == scs+2) {
+			if (v->fail_safe & 2) { v->fail_safe ^= 2; }
 			v->fail_safe |= 8;
 			break;
 		}
-
 	}
 
 	cprint(18, 18, "                                          ");
 	cprint(19, 15, "                                                ");
 
-	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
 		*pp = 0x17;
 	}
-
 }
 
 
@@ -158,13 +152,13 @@
 	serial_echo_print("\x1b[37m\x1b[44m");
 
 	/* Clear screen & set background to blue */
-	for(i=0, pp=(char *)(SCREEN_ADR); i<80*24; i++) {
+	for (i=0, pp=(char *)(SCREEN_ADR); i<80*24; i++) {
 		*pp++ = ' ';
 		*pp++ = 0x17;
 	}
 
 	/* Make the name background green */
-	for(i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+1); i<TITLE_WIDTH; i++, pp+=2) {
 		*pp = 0x20;
 	}
 	cprint(0, 0, MEMTEST_VERSION_STRING);
@@ -174,7 +168,7 @@
 	*pp = 0xA4;
 
 	/* Do reverse video for the bottom display line */
-	for(i=0, pp=(char *)(SCREEN_ADR+1+(24 * 160)); i<80; i++, pp+=2) {
+	for (i=0, pp=(char *)(SCREEN_ADR+1+(24 * 160)); i<80; i++, pp+=2) {
 		*pp = 0x71;
 	}
 
@@ -197,17 +191,17 @@
 	display_init();
 
 	cprint(5, 60, "| Time:   0:00:00");
-	cprint(1, COL_MID,"Pass   %");
-	cprint(2, COL_MID,"Test   %");
-	cprint(3, COL_MID,"Test #");
-	cprint(4, COL_MID,"Testing: ");
-	cprint(5, COL_MID,"Pattern: ");
+	cprint(1, COL_MID, "Pass   %");
+	cprint(2, COL_MID, "Test   %");
+	cprint(3, COL_MID, "Test #");
+	cprint(4, COL_MID, "Testing: ");
+	cprint(5, COL_MID, "Pattern: ");
 	cprint(1, 0, "CLK:           (32b Mode)");
 	cprint(2, 0, "L1 Cache: Unknown ");
 	cprint(3, 0, "L2 Cache: Unknown ");
-  cprint(4, 0, "L3 Cache:  None    ");
-  cprint(5, 0, "Memory  :         ");
-  cprint(6, 0, "------------------------------------------------------------------------------");
+	cprint(4, 0, "L3 Cache:  None    ");
+	cprint(5, 0, "Memory  :         ");
+	cprint(6, 0, "------------------------------------------------------------------------------");
 	cprint(7, 0, "Core#:");
 	cprint(8, 0, "State:");
 	cprint(9, 0, "Cores:    Active /    Total (Run: All) | Pass:       0        Errors:      0  ");
@@ -227,18 +221,18 @@
 	cprint(8, 39, "| Memory Type : Unknown");
 
 
-	for(i=0; i < 6; i++) {
+	for (i=0; i < 6; i++) {
 		cprint(i, COL_MID-2, "| ");
 	}
 
 	footer();
 
-  aprint(5, 10, v->test_pages);
+	aprint(5, 10, v->test_pages);
 
-  v->pass = 0;
-  v->msg_line = 0;
-  v->ecount = 0;
-  v->ecc_ecount = 0;
+	v->pass = 0;
+	v->msg_line = 0;
+	v->ecount = 0;
+	v->ecc_ecount = 0;
 	v->testsel = -1;
 	v->msg_line = LINE_SCROLL-1;
 	v->scroll_start = v->msg_line * 160;
@@ -259,7 +253,7 @@
 		tseq[i].errors = 0;
 	}
 	if (dmi_initialized) {
-		for (i=0; i < MAX_DMI_MEMDEVS; i++){
+		for (i=0; i < MAX_DMI_MEMDEVS; i++) {
 			if (dmi_err_cnts[i] > 0) {
 				dmi_err_cnts[i] = 0;
 			}
@@ -281,7 +275,7 @@
 
 	cpu_cache_speed();
 
-  /* Check fail safe */
+	/* Check fail safe */
 	failsafe(5000, 0x3B);
 
 	/* Initalize SMP */
@@ -294,37 +288,34 @@
 
 	dprint(9, 19, num_cpus, 2, 0);
 
-	if((v->fail_safe & 3) == 2)
-	{
-			cprint(LINE_CPU,9, "(SMP: Disabled)");
-			cprint(LINE_RAM,9, "Running...");
+	if ((v->fail_safe & 3) == 2) {
+		cprint(LINE_CPU, 9, "(SMP: Disabled)");
+		cprint(LINE_RAM, 9, "Running...");
 	}
 	// dprint(10, 5, found_cpus, 2, 0);
 
 	/* Find Memory Specs */
-	if(v->fail_safe & 1)
-		{
-			cprint(LINE_CPU, COL_SPEC, " **** FAIL SAFE **** FAIL SAFE **** ");
-			cprint(LINE_RAM, COL_SPEC, "   No detection, same reliability   ");
-		} else {
-			find_controller();
-			get_spd_spec();
-			if(num_cpus <= 16 && !(v->fail_safe & 4)) { coretemp(); }
-		}
+	if (v->fail_safe & 1) {
+		cprint(LINE_CPU, COL_SPEC, " **** FAIL SAFE **** FAIL SAFE **** ");
+		cprint(LINE_RAM, COL_SPEC, "   No detection, same reliability   ");
+	} else {
+		find_controller();
+		get_spd_spec();
+		if (num_cpus <= 16 && !(v->fail_safe & 4)) { coretemp(); }
+	}
 
-	if(v->check_temp > 0 && !(v->fail_safe & 4))
-	{
+	if (v->check_temp > 0 && !(v->fail_safe & 4)) {
 		cprint(LINE_CPU, 26, "|  CPU Temp");
 		cprint(LINE_CPU+1, 26, "|       C");
 	}
 
-		beep(600);
-		beep(1000);
+	beep(600);
+	beep(1000);
 
 	/* Record the start time */
-  asm __volatile__ ("rdtsc":"=a" (v->startl),"=d" (v->starth));
-  v->snapl = v->startl;
-  v->snaph = v->starth;
+	asm __volatile__ ("rdtsc" : "=a" (v->startl), "=d" (v->starth));
+	v->snapl = v->startl;
+	v->snaph = v->starth;
 	if (l1_cache == 0) { l1_cache = 64; }
 	if (l2_cache == 0) { l1_cache = 512; }
 	v->printmode=PRINTMODE_ADDRESSES;
@@ -342,14 +333,14 @@
 	struct cpuid4_ebx *ebx = (struct cpuid4_ebx *)&v[1];
 	struct cpuid4_ecx *ecx = (struct cpuid4_ecx *)&v[2];
 
-	switch(cpu_id.vend_id.char_array[0]) {
+	switch (cpu_id.vend_id.char_array[0]) {
 	/* AMD Processors */
 	case 'A':
 		//l1_cache = cpu_id.cache_info.amd.l1_i_sz;
 		l1_cache = cpu_id.cache_info.amd.l1_d_sz;
 		l2_cache = cpu_id.cache_info.amd.l2_sz;
 		l3_cache = cpu_id.cache_info.amd.l3_sz;
-    l3_cache *= 512;
+		l3_cache *= 512;
 		break;
 	case 'G':
 		/* Intel Processors */
@@ -359,181 +350,175 @@
 
 		/* Use CPUID(4) if it is available */
 		if (cpu_id.max_cpuid > 3) {
+			/* figure out how many cache leaves */
+			n = -1;
+			do {
+				++n;
+				/* Do cpuid(4) loop to find out num_cache_leaves */
+				cpuid_count(4, n, &v[0], &v[1], &v[2], &v[3]);
+			} while ((eax->ctype) != 0);
 
-		   /* figure out how many cache leaves */
-		    n = -1;
-		    do
-		    {
-					++n;
-					/* Do cpuid(4) loop to find out num_cache_leaves */
-					cpuid_count(4, n, &v[0], &v[1], &v[2], &v[3]);
-		    } while ((eax->ctype) != 0);
+			/* loop through all of the leaves */
+			for (i=0; i<n; i++) {
+				cpuid_count(4, i, &v[0], &v[1], &v[2], &v[3]);
 
-		    /* loop through all of the leaves */
-		    for (i=0; i<n; i++)
-		    {
-					cpuid_count(4, i, &v[0], &v[1], &v[2], &v[3]);
+				/* Check for a valid cache type */
+				if (eax->ctype == 1 || eax->ctype == 3) {
+					/* Compute the cache size */
+					size = (ecx->number_of_sets + 1) *
+					       (ebx->coherency_line_size + 1) *
+					       (ebx->physical_line_partition + 1) *
+					       (ebx->ways_of_associativity + 1);
+					size /= 1024;
 
-					/* Check for a valid cache type */
-					if (eax->ctype == 1 || eax->ctype == 3)
-					{
-
-			    	/* Compute the cache size */
-			    	size = (ecx->number_of_sets + 1) *
-            	              	  (ebx->coherency_line_size + 1) *
-              	            	  (ebx->physical_line_partition + 1) *
-                	          	  (ebx->ways_of_associativity + 1);
-			    	size /= 1024;
-
-				    switch (eax->level)
-				    {
-					  	case 1:
-								l1_cache += size;
-								break;
-					    case 2:
-								l2_cache += size;
-								break;
-					    case 3:
-								l3_cache += size;
-								break;
-					  }
+					switch (eax->level) {
+					case 1:
+						l1_cache += size;
+						break;
+					case 2:
+						l2_cache += size;
+						break;
+					case 3:
+						l3_cache += size;
+						break;
 					}
-		    }
-		    return;
+				}
+			}
+			return;
 		}
 
 		/* No CPUID(4) so we use the older CPUID(2) method */
 		/* Get number of times to iterate */
 		cpuid(2, &v[0], &v[1], &v[2], &v[3]);
 		n = v[0] & 0xff;
-                for (i=0 ; i<n ; i++) {
-                    cpuid(2, &v[0], &v[1], &v[2], &v[3]);
+		for (i=0; i<n; i++) {
+			cpuid(2, &v[0], &v[1], &v[2], &v[3]);
 
-                    /* If bit 31 is set, this is an unknown format */
-                    for (j=0 ; j<3 ; j++) {
-                            if (v[j] & (1 << 31)) {
-                                    v[j] = 0;
-			    }
-		    }
+			/* If bit 31 is set, this is an unknown format */
+			for (j=0; j<3; j++) {
+				if (v[j] & (1 << 31)) {
+					v[j] = 0;
+				}
+			}
 
-                    /* Byte 0 is level count, not a descriptor */
-                    for (j = 1 ; j < 16 ; j++) {
-			switch(dp[j]) {
-			case 0x6:
-			case 0xa:
-			case 0x66:
-				l1_cache += 8;
-				break;
-			case 0x8:
-			case 0xc:
-			case 0xd:
-			case 0x60:
-			case 0x67:
-				l1_cache += 16;
-				break;
-			case 0xe:
-				l1_cache += 24;
-				break;
-			case 0x9:
-			case 0x2c:
-			case 0x30:
-			case 0x68:
-				l1_cache += 32;
-				break;
-			case 0x39:
-			case 0x3b:
-			case 0x41:
-			case 0x79:
-				l2_cache += 128;
-				break;
-			case 0x3a:
-				l2_cache += 192;
-				break;
-			case 0x21:
-			case 0x3c:
-			case 0x3f:
-			case 0x42:
-			case 0x7a:
-			case 0x82:
-				l2_cache += 256;
-				break;
-			case 0x3d:
-				l2_cache += 384;
-				break;
-			case 0x3e:
-			case 0x43:
-			case 0x7b:
-			case 0x7f:
-			case 0x80:
-			case 0x83:
-			case 0x86:
-				l2_cache += 512;
-				break;
-			case 0x44:
-			case 0x78:
-			case 0x7c:
-			case 0x84:
-			case 0x87:
-				l2_cache += 1024;
-				break;
-			case 0x45:
-			case 0x7d:
-			case 0x85:
-				l2_cache += 2048;
-				break;
-			case 0x48:
-				l2_cache += 3072;
-				break;
-			case 0x4e:
-				l2_cache += 6144;
-				break;
-			case 0x23:
-			case 0xd0:
-				l3_cache += 512;
-				break;
-			case 0xd1:
-			case 0xd6:
-				l3_cache += 1024;
-				break;
-			case 0x25:
-			case 0xd2:
-			case 0xd7:
-			case 0xdc:
-			case 0xe2:
-				l3_cache += 2048;
-				break;
-			case 0x29:
-			case 0x46:
-			case 0x49:
-			case 0xd8:
-			case 0xdd:
-			case 0xe3:
-				l3_cache += 4096;
-				break;
-			case 0x4a:
-				l3_cache += 6144;
-				break;
-			case 0x47:
-			case 0x4b:
-			case 0xde:
-			case 0xe4:
-				l3_cache += 8192;
-				break;
-			case 0x4c:
-			case 0xea:
-				l3_cache += 12288;
-				break;
-			case 0x4d:
-				l3_cache += 16384;
-				break;
-			case 0xeb:
-				l3_cache += 18432;
-				break;
-			case 0xec:
-				l3_cache += 24576;
-				break;
-			} /* end switch */
-		    } /* end for 1-16 */
+			/* Byte 0 is level count, not a descriptor */
+			for (j = 1; j < 16; j++) {
+				switch (dp[j]) {
+				case 0x6:
+				case 0xa:
+				case 0x66:
+					l1_cache += 8;
+					break;
+				case 0x8:
+				case 0xc:
+				case 0xd:
+				case 0x60:
+				case 0x67:
+					l1_cache += 16;
+					break;
+				case 0xe:
+					l1_cache += 24;
+					break;
+				case 0x9:
+				case 0x2c:
+				case 0x30:
+				case 0x68:
+					l1_cache += 32;
+					break;
+				case 0x39:
+				case 0x3b:
+				case 0x41:
+				case 0x79:
+					l2_cache += 128;
+					break;
+				case 0x3a:
+					l2_cache += 192;
+					break;
+				case 0x21:
+				case 0x3c:
+				case 0x3f:
+				case 0x42:
+				case 0x7a:
+				case 0x82:
+					l2_cache += 256;
+					break;
+				case 0x3d:
+					l2_cache += 384;
+					break;
+				case 0x3e:
+				case 0x43:
+				case 0x7b:
+				case 0x7f:
+				case 0x80:
+				case 0x83:
+				case 0x86:
+					l2_cache += 512;
+					break;
+				case 0x44:
+				case 0x78:
+				case 0x7c:
+				case 0x84:
+				case 0x87:
+					l2_cache += 1024;
+					break;
+				case 0x45:
+				case 0x7d:
+				case 0x85:
+					l2_cache += 2048;
+					break;
+				case 0x48:
+					l2_cache += 3072;
+					break;
+				case 0x4e:
+					l2_cache += 6144;
+					break;
+				case 0x23:
+				case 0xd0:
+					l3_cache += 512;
+					break;
+				case 0xd1:
+				case 0xd6:
+					l3_cache += 1024;
+					break;
+				case 0x25:
+				case 0xd2:
+				case 0xd7:
+				case 0xdc:
+				case 0xe2:
+					l3_cache += 2048;
+					break;
+				case 0x29:
+				case 0x46:
+				case 0x49:
+				case 0xd8:
+				case 0xdd:
+				case 0xe3:
+					l3_cache += 4096;
+					break;
+				case 0x4a:
+					l3_cache += 6144;
+					break;
+				case 0x47:
+				case 0x4b:
+				case 0xde:
+				case 0xe4:
+					l3_cache += 8192;
+					break;
+				case 0x4c:
+				case 0xea:
+					l3_cache += 12288;
+					break;
+				case 0x4d:
+					l3_cache += 16384;
+					break;
+				case 0xeb:
+					l3_cache += 18432;
+					break;
+				case 0xec:
+					l3_cache += 24576;
+					break;
+				} /* end switch */
+			} /* end for 1-16 */
 		} /* end for 0 - n */
 	}
 }
@@ -544,111 +529,104 @@
 void detect_imc(void)
 {
 	// Check AMD IMC
-	if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF)
-		{
-			switch(cpu_id.vers.bits.extendedFamily)
-					{
-						case 0x0:
-							imc_type = 0x0100; // Old K8
-							break;
-						case 0x1:
-						case 0x2:
-							imc_type = 0x0101; // K10 (Family 10h & 11h)
-							break;
-						case 0x3:
-							imc_type = 0x0102; // A-Series APU (Family 12h)
-							break;
-						case 0x5:
-							imc_type = 0x0103; // C- / E- / Z- Series APU (Family 14h)
-							break;
-						case 0x6:
-							imc_type = 0x0104; // FX Series (Family 15h)
-							break;
-						case 0x7:
-							imc_type = 0x0105; // Kabini & related (Family 16h)
-							break;
-					}
-			return;
+	if (cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF) {
+		switch (cpu_id.vers.bits.extendedFamily) {
+		case 0x0:
+			imc_type = 0x0100; // Old K8
+			break;
+		case 0x1:
+		case 0x2:
+			imc_type = 0x0101; // K10 (Family 10h & 11h)
+			break;
+		case 0x3:
+			imc_type = 0x0102; // A-Series APU (Family 12h)
+			break;
+		case 0x5:
+			imc_type = 0x0103; // C- / E- / Z- Series APU (Family 14h)
+			break;
+		case 0x6:
+			imc_type = 0x0104; // FX Series (Family 15h)
+			break;
+		case 0x7:
+			imc_type = 0x0105; // Kabini & related (Family 16h)
+			break;
 		}
+		return;
+	}
 
 	// Check Intel IMC
-	if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.vers.bits.family == 6 && cpu_id.vers.bits.extendedModel)
-		{
-			switch(cpu_id.vers.bits.model)
-			{
-				case 0x5:
-					if(cpu_id.vers.bits.extendedModel == 2) { imc_type = 0x0003; } // Core i3/i5 1st Gen 45 nm (NHM)
-					if(cpu_id.vers.bits.extendedModel == 3) { v->fail_safe |= 4; } // Atom Clover Trail
-					if(cpu_id.vers.bits.extendedModel == 4) { imc_type = 0x0007; } // HSW-ULT
-					break;
-				case 0x6:
-					if(cpu_id.vers.bits.extendedModel == 3) {
-						imc_type = 0x0009;  // Atom Cedar Trail
-						v->fail_safe |= 4; // Disable Core temp
-					}
-					break;
-				case 0x7:
-					if(cpu_id.vers.bits.extendedModel == 3) {
-						imc_type = 0x000A;  // Atom Bay Trail
-					}
-					break;
-				case 0xA:
-					switch(cpu_id.vers.bits.extendedModel)
-					{
-						case 0x1:
-							imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHME)
-							break;
-						case 0x2:
-							imc_type = 0x0004; // Core 2nd Gen (SNB)
-							break;
-						case 0x3:
-							imc_type = 0x0006; // Core 3nd Gen (IVB)
-							break;
-					}
-					break;
-				case 0xC:
-					switch(cpu_id.vers.bits.extendedModel)
-					{
-						case 0x1:
-							if(cpu_id.vers.bits.stepping > 9) { imc_type = 0x0008; } // Atom PineView
-							v->fail_safe |= 4; // Disable Core temp
-							break;
-						case 0x2:
-							imc_type = 0x0002; // Core i7 1st Gen 32 nm (WMR)
-							break;
-						case 0x3:
-							imc_type = 0x0007; // Core 4nd Gen (HSW)
-							break;
-					}
-					break;
-				case 0xD:
-					imc_type = 0x0005; // SNB-E
-					break;
-				case 0xE:
-					imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHM)
-					break;
+	if (cpu_id.vend_id.char_array[0] == 'G' && cpu_id.vers.bits.family == 6 && cpu_id.vers.bits.extendedModel) {
+		switch (cpu_id.vers.bits.model) {
+		case 0x5:
+			if (cpu_id.vers.bits.extendedModel == 2) { imc_type = 0x0003; } // Core i3/i5 1st Gen 45 nm (NHM)
+			if (cpu_id.vers.bits.extendedModel == 3) { v->fail_safe |= 4; } // Atom Clover Trail
+			if (cpu_id.vers.bits.extendedModel == 4) { imc_type = 0x0007; } // HSW-ULT
+			break;
+		case 0x6:
+			if (cpu_id.vers.bits.extendedModel == 3) {
+				imc_type = 0x0009;  // Atom Cedar Trail
+				v->fail_safe |= 4;  // Disable Core temp
 			}
-
-		if(imc_type) { tsc_invariable = 1; }
-		return;
+			break;
+		case 0x7:
+			if (cpu_id.vers.bits.extendedModel == 3) {
+				imc_type = 0x000A;  // Atom Bay Trail
+			}
+			break;
+		case 0xA:
+			switch (cpu_id.vers.bits.extendedModel) {
+			case 0x1:
+				imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHME)
+				break;
+			case 0x2:
+				imc_type = 0x0004; // Core 2nd Gen (SNB)
+				break;
+			case 0x3:
+				imc_type = 0x0006; // Core 3nd Gen (IVB)
+				break;
+			}
+			break;
+		case 0xC:
+			switch (cpu_id.vers.bits.extendedModel) {
+			case 0x1:
+				if (cpu_id.vers.bits.stepping > 9) { imc_type = 0x0008; } // Atom PineView
+				v->fail_safe |= 4; // Disable Core temp
+				break;
+			case 0x2:
+				imc_type = 0x0002; // Core i7 1st Gen 32 nm (WMR)
+				break;
+			case 0x3:
+				imc_type = 0x0007; // Core 4nd Gen (HSW)
+				break;
+			}
+			break;
+		case 0xD:
+			imc_type = 0x0005; // SNB-E
+			break;
+		case 0xE:
+			imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHM)
+			break;
 		}
+
+		if (imc_type) { tsc_invariable = 1; }
+		return;
+	}
 }
 
 void smp_default_mode(void)
 {
 	int i, result;
 	char *cpupsn = cpu_id.brand_id.char_array;
-  char *disabledcpu[] = { "Opteron", "Xeon", "Genuine Intel" };
+	char *disabledcpu[] = { "Opteron", "Xeon", "Genuine Intel" };
 
-  for(i = 0; i < 3; i++)
-  {
-  	result = strstr(cpupsn , disabledcpu[i]);
-  	if(result != -1) { v->fail_safe |= 0b10; }
-  }
+	for (i = 0; i < 3; i++)
+	{
+		result = strstr(cpupsn, disabledcpu[i]);
+		if (result != -1) { v->fail_safe |= 0b10; }
+	}
 
-  // For 5.01 release, SMP disabled by defualt by config.h toggle
-  if(CONSERVATIVE_SMP) { v->fail_safe |= 0b10; }
-
+	// For 5.01 release, SMP disabled by defualt by config.h toggle
+	if (CONSERVATIVE_SMP) { v->fail_safe |= 0b10; }
 }
 
 /*
@@ -667,12 +645,12 @@
 
 	/* The brand string is not available so we need to figure out
 	 * CPU what we have */
-	switch(cpu_id.vend_id.char_array[0]) {
+	switch (cpu_id.vend_id.char_array[0]) {
 	/* AMD Processors */
 	case 'A':
-		switch(cpu_id.vers.bits.family) {
+		switch (cpu_id.vers.bits.family) {
 		case 4:
-			switch(cpu_id.vers.bits.model) {
+			switch (cpu_id.vers.bits.model) {
 			case 3:
 				cprint(0, COL_MID, "AMD 486DX2");
 				break;
@@ -695,7 +673,7 @@
 			/* Since we can't get CPU speed or cache info return */
 			return;
 		case 5:
-			switch(cpu_id.vers.bits.model) {
+			switch (cpu_id.vers.bits.model) {
 			case 0:
 			case 1:
 			case 2:
@@ -720,7 +698,7 @@
 			break;
 		case 6:
 
-			switch(cpu_id.vers.bits.model) {
+			switch (cpu_id.vers.bits.model) {
 			case 1:
 				cprint(0, COL_MID, "AMD Athlon (0.25)");
 				break;
@@ -764,7 +742,7 @@
 
 	/* Intel or Transmeta Processors */
 	case 'G':
-		if ( cpu_id.vend_id.char_array[7] == 'T' ) { /* GenuineTMx86 */
+		if (cpu_id.vend_id.char_array[7] == 'T') { /* GenuineTMx86 */
 			if (cpu_id.vers.bits.family == 5) {
 				cprint(0, COL_MID, "TM 5x00");
 			} else if (cpu_id.vers.bits.family == 15) {
@@ -772,85 +750,85 @@
 			}
 			l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
 			l2_cache = (cpu_id.cache_info.ch[11]*256) + cpu_id.cache_info.ch[10];
-		} else {				/* GenuineIntel */
+		} else { /* GenuineIntel */
 			if (cpu_id.vers.bits.family == 4) {
-			switch(cpu_id.vers.bits.model) {
-			case 0:
-			case 1:
-				cprint(0, COL_MID, "Intel 486DX");
-				break;
-			case 2:
-				cprint(0, COL_MID, "Intel 486SX");
-				break;
-			case 3:
-				cprint(0, COL_MID, "Intel 486DX2");
-				break;
-			case 4:
-				cprint(0, COL_MID, "Intel 486SL");
-				break;
-			case 5:
-				cprint(0, COL_MID, "Intel 486SX2");
-				break;
-			case 7:
-				cprint(0, COL_MID, "Intel 486DX2-WB");
-				break;
-			case 8:
-				cprint(0, COL_MID, "Intel 486DX4");
-				break;
-			case 9:
-				cprint(0, COL_MID, "Intel 486DX4-WB");
-				break;
+				switch (cpu_id.vers.bits.model) {
+				case 0:
+				case 1:
+					cprint(0, COL_MID, "Intel 486DX");
+					break;
+				case 2:
+					cprint(0, COL_MID, "Intel 486SX");
+					break;
+				case 3:
+					cprint(0, COL_MID, "Intel 486DX2");
+					break;
+				case 4:
+					cprint(0, COL_MID, "Intel 486SL");
+					break;
+				case 5:
+					cprint(0, COL_MID, "Intel 486SX2");
+					break;
+				case 7:
+					cprint(0, COL_MID, "Intel 486DX2-WB");
+					break;
+				case 8:
+					cprint(0, COL_MID, "Intel 486DX4");
+					break;
+				case 9:
+					cprint(0, COL_MID, "Intel 486DX4-WB");
+					break;
+				}
+				/* Since we can't get CPU speed or cache info return */
+				return;
 			}
-			/* Since we can't get CPU speed or cache info return */
-			return;
-		}
 
 
-		switch(cpu_id.vers.bits.family) {
-		case 5:
-			switch(cpu_id.vers.bits.model) {
-			case 0:
-			case 1:
-			case 2:
-			case 3:
-			case 7:
-				cprint(0, COL_MID, "Pentium");
-				if (l1_cache == 0) {
-					l1_cache = 8;
-				}
-				break;
-			case 4:
-			case 8:
-				cprint(0, COL_MID, "Pentium-MMX");
-				if (l1_cache == 0) {
-					l1_cache = 16;
-				}
-				break;
-			}
-			break;
-		case 6:
-			switch(cpu_id.vers.bits.model) {
-			case 0:
-			case 1:
-				cprint(0, COL_MID, "Pentium Pro");
-				break;
-			case 3:
-			case 4:
-				cprint(0, COL_MID, "Pentium II");
-				break;
+			switch (cpu_id.vers.bits.family) {
 			case 5:
-				if (l2_cache == 0) {
-					cprint(0, COL_MID, "Celeron");
-				} else {
-					cprint(0, COL_MID, "Pentium II");
+				switch (cpu_id.vers.bits.model) {
+				case 0:
+				case 1:
+				case 2:
+				case 3:
+				case 7:
+					cprint(0, COL_MID, "Pentium");
+					if (l1_cache == 0) {
+						l1_cache = 8;
+					}
+					break;
+				case 4:
+				case 8:
+					cprint(0, COL_MID, "Pentium-MMX");
+					if (l1_cache == 0) {
+						l1_cache = 16;
+					}
+					break;
 				}
 				break;
 			case 6:
-				  if (l2_cache == 128) {
-					cprint(0, COL_MID, "Celeron");
-				  } else {
+				switch (cpu_id.vers.bits.model) {
+				case 0:
+				case 1:
+					cprint(0, COL_MID, "Pentium Pro");
+					break;
+				case 3:
+				case 4:
 					cprint(0, COL_MID, "Pentium II");
-				  }
+					break;
+				case 5:
+					if (l2_cache == 0) {
+						cprint(0, COL_MID, "Celeron");
+					} else {
+						cprint(0, COL_MID, "Pentium II");
+					}
+					break;
+				case 6:
+					if (l2_cache == 128) {
+						cprint(0, COL_MID, "Celeron");
+					} else {
+						cprint(0, COL_MID, "Pentium II");
+					}
 				}
 				break;
 			case 7:
@@ -869,7 +847,7 @@
 					cprint(0, COL_MID, "Pentium M (0.13)");
 				}
 				break;
-     			case 10:
+			case 10:
 				cprint(0, COL_MID, "Pentium III Xeon");
 				break;
 			case 12:
@@ -896,7 +874,7 @@
 			}
 			break;
 		case 15:
-			switch(cpu_id.vers.bits.model) {
+			switch (cpu_id.vers.bits.model) {
 			case 0:
 			case 1:
 			case 2:
@@ -919,30 +897,29 @@
 				break;
 			default:
 				cprint(0, COL_MID, "Unknown Intel");
- 				break;
-		    }
-
+				break;
+			}
 		}
 		break;
 
 	/* VIA/Cyrix/Centaur Processors with CPUID */
 	case 'C':
-		if ( cpu_id.vend_id.char_array[1] == 'e' ) { /* CentaurHauls */
+		if (cpu_id.vend_id.char_array[1] == 'e') {   /* CentaurHauls */
 			l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
 			l2_cache = cpu_id.cache_info.ch[11];
-			switch(cpu_id.vers.bits.family){
+			switch (cpu_id.vers.bits.family) {
 			case 5:
 				cprint(0, COL_MID, "Centaur 5x86");
 				break;
 			case 6: // VIA C3
-				switch(cpu_id.vers.bits.model){
+				switch (cpu_id.vers.bits.model) {
 				default:
-				    if (cpu_id.vers.bits.stepping < 8) {
-					cprint(0, COL_MID, "VIA C3 Samuel2");
-				    } else {
-					cprint(0, COL_MID, "VIA C3 Eden");
-				    }
-				break;
+					if (cpu_id.vers.bits.stepping < 8) {
+						cprint(0, COL_MID, "VIA C3 Samuel2");
+					} else {
+						cprint(0, COL_MID, "VIA C3 Eden");
+					}
+					break;
 				case 10:
 					cprint(0, COL_MID, "VIA C7 (C5J)");
 					l1_cache = 64;
@@ -960,10 +937,10 @@
 					break;
 				}
 			}
-		} else {				/* CyrixInstead */
-			switch(cpu_id.vers.bits.family) {
+		} else {                                /* CyrixInstead */
+			switch (cpu_id.vers.bits.family) {
 			case 5:
-				switch(cpu_id.vers.bits.model) {
+				switch (cpu_id.vers.bits.model) {
 				case 0:
 					cprint(0, COL_MID, "Cyrix 6x86MX/MII");
 					break;
@@ -974,7 +951,7 @@
 				return;
 
 			case 6: // VIA C3
-				switch(cpu_id.vers.bits.model) {
+				switch (cpu_id.vers.bits.model) {
 				case 6:
 					cprint(0, COL_MID, "Cyrix III");
 					break;
@@ -1002,7 +979,7 @@
 	/* Unknown processor */
 	default:
 		/* Make a guess at the family */
-		switch(cpu_id.vers.bits.family) {
+		switch (cpu_id.vers.bits.family) {
 		case 5:
 			cprint(0, COL_MID, "586");
 			break;
@@ -1015,7 +992,7 @@
 	}
 }
 
-#define STEST_ADDR 0x100000	/* Measure memory speed starting at 1MB */
+#define STEST_ADDR 0x100000     /* Measure memory speed starting at 1MB */
 
 /* Measure and display CPU and cache sizes and speeds */
 void cpu_cache_speed(void)
@@ -1073,19 +1050,18 @@
 	/* We measure the L3 cache speed by using a block size that is */
 	/* 2X the size of the L2 cache. */
 
-	if (l3_cache)
-	{
+	if (l3_cache) {
 		cprint(4, 0, "L3 Cache:     K  ");
-   	aprint(4, 10, l3_cache/4);
-    //dprint(4, 10, l3_cache, 4, 0);
+		aprint(4, 10, l3_cache/4);
+		//dprint(4, 10, l3_cache, 4, 0);
 
-    		i = l2_cache*2;
+		i = l2_cache*2;
 
-    		if ((speed=memspeed(STEST_ADDR, i*1024, 150))) {
-    			cprint(4, 16, "       MB/s");
-    			dprint(4, 16, speed, 6, 0);
-    		}
-   }
+		if ((speed=memspeed(STEST_ADDR, i*1024, 150))) {
+			cprint(4, 16, "       MB/s");
+			dprint(4, 16, speed, 6, 0);
+		}
+	}
 }
 
 /* Measure and display memory speed, multitasked using all CPUs */
@@ -1095,10 +1071,10 @@
 	int i;
 	ulong speed=0;
 
-   /* Determine memory speed.  To find the memory speed we use
-   * A block size that is the sum of all the L1, L2 & L3 caches
+	/* Determine memory speed.  To find the memory speed we use
+	 * A block size that is the sum of all the L1, L2 & L3 caches
 	 * in all cpus * 6 */
-   i = (l3_cache + l2_cache + l1_cache) * 4;
+	i = (l3_cache + l2_cache + l1_cache) * 4;
 
 	/* Make sure that we have enough memory to do the test */
 	/* If not use all we have */
@@ -1109,12 +1085,11 @@
 	speed = memspeed(STEST_ADDR, i * 1024, 100);
 	cprint(5, 16, "       MB/s");
 	dprint(5, 16, speed, 6, 0);
-
 }
 
 /* #define TICKS 5 * 11832 (count = 6376)*/
 /* #define TICKS (65536 - 12752) */
-#define TICKS 59659	/* 50 ms */
+#define TICKS 59659     /* 50 ms */
 
 /* Returns CPU clock in khz */
 ulong stlow, sthigh;
@@ -1123,7 +1098,7 @@
 	int loops;
 	ulong end_low, end_high;
 
-	if (cpu_id.fid.bits.rdtsc == 0 ) {
+	if (cpu_id.fid.bits.rdtsc == 0) {
 		return(-1);
 	}
 
@@ -1133,7 +1108,7 @@
 	outb(TICKS & 0xff, 0x42);
 	outb(TICKS >> 8, 0x42);
 
-	asm __volatile__ ("rdtsc":"=a" (stlow),"=d" (sthigh));
+	asm __volatile__ ("rdtsc" : "=a" (stlow), "=d" (sthigh));
 
 	loops = 0;
 	do {
@@ -1144,7 +1119,7 @@
 		"rdtsc\n\t" \
 		"subl stlow,%%eax\n\t" \
 		"sbbl sthigh,%%edx\n\t" \
-		:"=a" (end_low), "=d" (end_high)
+		: "=a" (end_low), "=d" (end_high)
 	);
 
 	/* Make sure we have a credible result */
@@ -1168,7 +1143,7 @@
 	ulong end_low, end_high;
 	ulong cal_low, cal_high;
 
-	if (cpu_id.fid.bits.rdtsc == 0 ) {
+	if (cpu_id.fid.bits.rdtsc == 0) {
 		return(-1);
 	}
 	if (len == 0) return(-2);
@@ -1177,28 +1152,28 @@
 	wlen = len / 4;  /* Length is bytes */
 
 	/* Calibrate the overhead with a zero word copy */
-	asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
+	asm __volatile__ ("rdtsc" : "=a" (st_low), "=d" (st_high));
 	for (i=0; i<iter; i++) {
 		asm __volatile__ (
 			"movl %0,%%esi\n\t" \
- 		 	"movl %1,%%edi\n\t" \
- 		 	"movl %2,%%ecx\n\t" \
- 		 	"cld\n\t" \
- 		 	"rep\n\t" \
- 		 	"movsl\n\t" \
-			:: "g" (src), "g" (dst), "g" (0)
+			"movl %1,%%edi\n\t" \
+			"movl %2,%%ecx\n\t" \
+			"cld\n\t" \
+			"rep\n\t" \
+			"movsl\n\t" \
+			: : "g" (src), "g" (dst), "g" (0)
 			: "esi", "edi", "ecx"
 		);
 	}
-	asm __volatile__ ("rdtsc":"=a" (cal_low),"=d" (cal_high));
+	asm __volatile__ ("rdtsc" : "=a" (cal_low), "=d" (cal_high));
 
 	/* Compute the overhead time */
 	asm __volatile__ (
 		"subl %2,%0\n\t"
 		"sbbl %3,%1"
-		:"=a" (cal_low), "=d" (cal_high)
-		:"g" (st_low), "g" (st_high),
-		"0" (cal_low), "1" (cal_high)
+		: "=a" (cal_low), "=d" (cal_high)
+		: "g" (st_low), "g" (st_high),
+		  "0" (cal_low), "1" (cal_high)
 	);
 
 
@@ -1207,43 +1182,43 @@
 	asm __volatile__ (
 		"movl %0,%%esi\n\t" \
 		"movl %1,%%edi\n\t" \
- 	 	"movl %2,%%ecx\n\t" \
- 	 	"cld\n\t" \
- 	 	"rep\n\t" \
- 	 	"movsl\n\t" \
-		:: "g" (src), "g" (dst), "g" (wlen)
+		"movl %2,%%ecx\n\t" \
+		"cld\n\t" \
+		"rep\n\t" \
+		"movsl\n\t" \
+		: : "g" (src), "g" (dst), "g" (wlen)
 		: "esi", "edi", "ecx"
 	);
-	asm __volatile__ ("rdtsc":"=a" (st_low),"=d" (st_high));
+	asm __volatile__ ("rdtsc" : "=a" (st_low), "=d" (st_high));
 	for (i=0; i<iter; i++) {
-	        asm __volatile__ (
+		asm __volatile__ (
 			"movl %0,%%esi\n\t" \
 			"movl %1,%%edi\n\t" \
- 		 	"movl %2,%%ecx\n\t" \
- 		 	"cld\n\t" \
- 		 	"rep\n\t" \
- 		 	"movsl\n\t" \
-			:: "g" (src), "g" (dst), "g" (wlen)
+			"movl %2,%%ecx\n\t" \
+			"cld\n\t" \
+			"rep\n\t" \
+			"movsl\n\t" \
+			: : "g" (src), "g" (dst), "g" (wlen)
 			: "esi", "edi", "ecx"
 		);
 	}
-	asm __volatile__ ("rdtsc":"=a" (end_low),"=d" (end_high));
+	asm __volatile__ ("rdtsc" : "=a" (end_low), "=d" (end_high));
 
 	/* Compute the elapsed time */
 	asm __volatile__ (
 		"subl %2,%0\n\t"
 		"sbbl %3,%1"
-		:"=a" (end_low), "=d" (end_high)
-		:"g" (st_low), "g" (st_high),
-		"0" (end_low), "1" (end_high)
+		: "=a" (end_low), "=d" (end_high)
+		: "g" (st_low), "g" (st_high),
+		  "0" (end_low), "1" (end_high)
 	);
 	/* Subtract the overhead time */
 	asm __volatile__ (
 		"subl %2,%0\n\t"
 		"sbbl %3,%1"
-		:"=a" (end_low), "=d" (end_high)
-		:"g" (cal_low), "g" (cal_high),
-		"0" (end_low), "1" (end_high)
+		: "=a" (end_low), "=d" (end_high)
+		: "g" (cal_low), "g" (cal_high),
+		  "0" (end_low), "1" (end_high)
 	);
 
 	/* Make sure that the result fits in 32 bits */
@@ -1268,10 +1243,10 @@
 	return((v->clks_msec)/end_low);
 }
 
-#define rdmsr(msr,val1,val2) \
-	__asm__ __volatile__("rdmsr" \
-		  : "=a" (val1), "=d" (val2) \
-		  : "c" (msr))
+#define rdmsr(msr, val1, val2) \
+	__asm__ __volatile__ ("rdmsr" \
+		: "=a" (val1), "=d" (val2) \
+		: "c" (msr))
 
 
 ulong correct_tsc(ulong el_org)
@@ -1282,7 +1257,7 @@
 	rdmsr(0x198, msr_lo, msr_hi);
 	is_xe = (msr_lo >> 31) & 0x1;
 
-	if(is_xe){
+	if (is_xe) {
 		rdmsr(0x198, msr_lo, msr_hi);
 		coef_max = ((msr_hi >> 8) & 0x1F);
 		if ((msr_hi >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
@@ -1292,7 +1267,7 @@
 		if ((msr_lo >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
 	}
 
-	if(cpu_id.fid.bits.eist) {
+	if (cpu_id.fid.bits.eist) {
 		rdmsr(0x198, msr_lo, msr_hi);
 		coef_now = ((msr_lo >> 8) & 0x1F);
 		if ((msr_lo >> 14) & 0x1) { coef_now = coef_now + 0.5f; }
@@ -1300,9 +1275,8 @@
 		rdmsr(0x2A, msr_lo, msr_hi);
 		coef_now = (msr_lo >> 22) & 0x1F;
 	}
-	if(coef_max && coef_now) {
+	if (coef_max && coef_now) {
 		el_org = (ulong)(el_org * coef_now / coef_max);
 	}
 	return el_org;
 }
-
diff --git a/main.c b/main.c
index 606c4f0..4cdb042 100644
--- a/main.c
+++ b/main.c
@@ -23,7 +23,7 @@
 
 /* The main stack is allocated during boot time. The stack size should
  * preferably be a multiple of page size(4Kbytes)
-*/
+ */
 
 extern struct	cpu_ident cpu_id;
 extern char	toupper(char c);
@@ -51,18 +51,18 @@
 static int	compute_segments(struct pmap map, int cpu);
 int		do_test(int ord);
 struct tseq tseq[] = {
-	{1, -1,  0,   6, 0, "[Address test, walking ones, no cache] "},
-	{1, -1,  1,   6, 0, "[Address test, own address Sequential] "},
-	{1, 32,  2,   6, 0, "[Address test, own address Parallel]   "},
-	{1, 32,  3,   6, 0, "[Moving inversions, 1s & 0s Parallel]  "},
-	{1, 32,  5,   3, 0, "[Moving inversions, 8 bit pattern]     "},
-	{1, 32,  6,  30, 0, "[Moving inversions, random pattern]    "},
-	{1, 32,  7,  81, 0, "[Block move]                           "},
-	{1,  1,  8,   3, 0, "[Moving inversions, 32 bit pattern]    "},
-	{1, 32,  9,  48, 0, "[Random number sequence]               "},
-  {1, 32, 10,   6, 0, "[Modulo 20, Random pattern]            "},
-	{1, 1,  11, 240, 0, "[Bit fade test, 2 patterns]            "},
-	{1, 0,   0,   0, 0, NULL}
+	{ 1, -1,  0,   6, 0, "[Address test, walking ones, no cache] " },
+	{ 1, -1,  1,   6, 0, "[Address test, own address Sequential] " },
+	{ 1, 32,  2,   6, 0, "[Address test, own address Parallel]   " },
+	{ 1, 32,  3,   6, 0, "[Moving inversions, 1s & 0s Parallel]  " },
+	{ 1, 32,  5,   3, 0, "[Moving inversions, 8 bit pattern]     " },
+	{ 1, 32,  6,  30, 0, "[Moving inversions, random pattern]    " },
+	{ 1, 32,  7,  81, 0, "[Block move]                           " },
+	{ 1,  1,  8,   3, 0, "[Moving inversions, 32 bit pattern]    " },
+	{ 1, 32,  9,  48, 0, "[Random number sequence]               " },
+	{ 1, 32, 10,   6, 0, "[Modulo 20, Random pattern]            " },
+	{ 1,  1, 11, 240, 0, "[Bit fade test, 2 patterns]            " },
+	{ 1,  0,  0,   0, 0, NULL                                      }
 };
 
 volatile int    mstr_cpu;
@@ -103,17 +103,17 @@
 {
 	test++;
 	while (tseq[test].sel == 0 && tseq[test].cpu_sel != 0) {
-	    test++;
+		test++;
 	}
 
 	if (tseq[test].cpu_sel == 0) {
-	    /* We hit the end of the list so we completed a pass */
-	    pass_flag++;
-	    /* Find the next test to run, start searching from 0 */
-	    test = 0;
-	    while (tseq[test].sel == 0 && tseq[test].cpu_sel != 0) {
-		test++;
-	    }
+		/* We hit the end of the list so we completed a pass */
+		pass_flag++;
+		/* Find the next test to run, start searching from 0 */
+		test = 0;
+		while (tseq[test].sel == 0 && tseq[test].cpu_sel != 0) {
+			test++;
+		}
 	}
 }
 
@@ -217,7 +217,7 @@
 
 	/* We use a lock to insure that only one CPU at a time jumps to
 	 * the new code. Some of the startup stuff is not thread safe! */
-  spin_lock(&barr->mutex);
+	spin_lock(&barr->mutex);
 
 	/* Jump to the start address */
 	goto *ja;
@@ -249,7 +249,7 @@
 
 	offs = (uint8_t *)&boot_stack_top - stackTop;
 	__asm__ __volatile__ (
-	"subl %%eax, %%esp"
+		"subl %%eax, %%esp"
 		: /*no output*/
 		: "a" (offs) : "memory"
 	);
@@ -258,7 +258,7 @@
 void reloc_internal(int cpu)
 {
 	/* clear variables */
-        reloc_pending = FALSE;
+	reloc_pending = FALSE;
 
 	run_at(LOW_TEST_ADR, cpu);
 }
@@ -266,14 +266,14 @@
 void reloc(void)
 {
 	bail++;
-        reloc_pending = TRUE;
+	reloc_pending = TRUE;
 }
 
 /* command line passing using the 'old' boot protocol */
-#define MK_PTR(seg,off) ((void*)(((unsigned long)(seg) << 4) + (off)))
-#define OLD_CL_MAGIC_ADDR ((unsigned short*) MK_PTR(INITSEG,0x20))
+#define MK_PTR(seg, off) ((void*)(((unsigned long)(seg) << 4) + (off)))
+#define OLD_CL_MAGIC_ADDR ((unsigned short*) MK_PTR(INITSEG, 0x20))
 #define OLD_CL_MAGIC 0xA33F
-#define OLD_CL_OFFSET_ADDR ((unsigned short*) MK_PTR(INITSEG,0x22))
+#define OLD_CL_OFFSET_ADDR ((unsigned short*) MK_PTR(INITSEG, 0x22))
 
 static void parse_command_line(void)
 {
@@ -335,36 +335,36 @@
 
 			/* Now enable all of the tests in the list */
 			j = 0;
-			while(*cp && isdigit(*cp)) {
-			    i = *cp-'0';
-			    j = j*10 + i;
-			    cp++;
-			    if (*cp == ',' || !isdigit(*cp)) {
-				if (j < k) {
-				    tseq[j].sel = 1;
+			while (*cp && isdigit(*cp)) {
+				i = *cp-'0';
+				j = j*10 + i;
+				cp++;
+				if (*cp == ',' || !isdigit(*cp)) {
+					if (j < k) {
+						tseq[j].sel = 1;
+					}
+					if (*cp != ',') break;
+					j = 0;
+					cp++;
 				}
-				if (*cp != ',') break;
-				j = 0;
-			    	cp++;
-			    }
 			}
 		}
 		/* Set a CPU mask to select CPU's to use for testing */
 		if (!strncmp(cp, "cpumask=", 8)) {
-		    cp += 8;
-		    if (cp[0] == '0' && toupper(cp[1]) == 'X') cp += 2;
-		    while (*cp && *cp != ' ' && isxdigit(*cp)) {
-			i = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10;
-			bin_mask = bin_mask * 16 + i;
-			cp++;
-		    }
-		    /* Force CPU zero to always be selected */
-		    bin_mask |= 1;
-		    for (i=0; i<32; i++) {
-			if (((bin_mask>>i) & 1) == 0) {
-			     cpu_mask[i] = 0;
+			cp += 8;
+			if (cp[0] == '0' && toupper(cp[1]) == 'X') cp += 2;
+			while (*cp && *cp != ' ' && isxdigit(*cp)) {
+				i = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10;
+				bin_mask = bin_mask * 16 + i;
+				cp++;
 			}
-		    }
+			/* Force CPU zero to always be selected */
+			bin_mask |= 1;
+			for (i=0; i<32; i++) {
+				if (((bin_mask>>i) & 1) == 0) {
+					cpu_mask[i] = 0;
+				}
+			}
 		}
 		/* go to the next parameter */
 		while (*cp && *cp != ' ') cp++;
@@ -380,18 +380,18 @@
 	char *pp;
 
 	/* Clear screen & set background to blue */
-	for(i=0, pp=(char *)(SCREEN_ADR); i<80*25; i++) {
+	for (i=0, pp=(char *)(SCREEN_ADR); i<80*25; i++) {
 		*pp++ = ' ';
 		*pp++ = 0x17;
 	}
 	if (btflag) {
-	    cprint(1, 0, "Boot Trace Enabled");
-	    cprint(1, 0, "Press any key to advance to next trace point");
-	    cprint(9, 1,"CPU Line Message     Param #1 Param #2  CPU Line Message     Param #1 Param #2");
-	    cprint(10,1,"--- ---- ----------- -------- --------  --- ---- ----------- -------- --------");
+		cprint(1, 0, "Boot Trace Enabled");
+		cprint(1, 0, "Press any key to advance to next trace point");
+		cprint(9, 1, "CPU Line Message     Param #1 Param #2  CPU Line Message     Param #1 Param #2");
+		cprint(10, 1, "--- ---- ----------- -------- --------  --- ---- ----------- -------- --------");
 	}
-
 }
+
 /* This is the test entry point. We get here on statup and also whenever
  * we relocate. */
 void test_start(void)
@@ -412,69 +412,67 @@
 
 	/* First time (for this CPU) initialization */
 	if (start_seq < 2) {
+		/* These steps are only done by the boot cpu */
+		if (my_cpu_num == 0) {
+			my_cpu_ord = cpu_ord++;
+			smp_set_ordinal(my_cpu_num, my_cpu_ord);
+			parse_command_line();
+			clear_screen();
+			/* Initialize the barrier so the lock in btrace will work.
+			 * Will get redone later when we know how many CPUs we have */
+			barrier_init(1);
+			btrace(my_cpu_num, __LINE__, "Begin     ", 1, 0, 0);
+			/* Find memory size */
+			mem_size(); /* must be called before initialise_cpus(); */
+			/* Fill in the CPUID table */
+			get_cpuid();
+			/* Startup the other CPUs */
+			start_seq = 1;
+			//initialise_cpus();
+			btrace(my_cpu_num, __LINE__, "BeforeInit", 1, 0, 0);
+			/* Draw the screen and get system information */
+			init();
 
-	    /* These steps are only done by the boot cpu */
-	    if (my_cpu_num == 0) {
-		my_cpu_ord = cpu_ord++;
-		smp_set_ordinal(my_cpu_num, my_cpu_ord);
-		parse_command_line();
-		clear_screen();
-		/* Initialize the barrier so the lock in btrace will work.
-		 * Will get redone later when we know how many CPUs we have */
-		barrier_init(1);
-		btrace(my_cpu_num, __LINE__, "Begin     ", 1, 0, 0);
-		/* Find memory size */
-		 mem_size();	/* must be called before initialise_cpus(); */
-		/* Fill in the CPUID table */
-		get_cpuid();
-		/* Startup the other CPUs */
-		start_seq = 1;
-		//initialise_cpus();
-		btrace(my_cpu_num, __LINE__, "BeforeInit", 1, 0, 0);
-		/* Draw the screen and get system information */
-		init();
+			/* Set defaults and initialize variables */
+			set_defaults();
 
-		/* Set defaults and initialize variables */
-		set_defaults();
+			/* Setup base address for testing, 1 MB */
+			win0_start = 0x100;
 
-		/* Setup base address for testing, 1 MB */
-		win0_start = 0x100;
+			/* Set relocation address to 32Mb if there is enough
+			 * memory. Otherwise set it to 3Mb */
+			/* Large reloc addr allows for more testing overlap */
+			if ((ulong)v->pmap[v->msegs-1].end > 0x2f00) {
+				high_test_adr = 0x2000000;
+			} else {
+				high_test_adr = 0x300000;
+			}
+			win1_end = (high_test_adr >> 12);
 
-		/* Set relocation address to 32Mb if there is enough
-		 * memory. Otherwise set it to 3Mb */
-		/* Large reloc addr allows for more testing overlap */
-	        if ((ulong)v->pmap[v->msegs-1].end > 0x2f00) {
-			high_test_adr = 0x2000000;
-	        } else {
-			high_test_adr = 0x300000;
+			/* Adjust the map to not test the page at 939k,
+			 *  reserved for locks */
+			v->pmap[0].end--;
+
+			find_ticks_for_pass();
+		} else {
+			/* APs only, Register the APs */
+			btrace(my_cpu_num, __LINE__, "AP_Start  ", 0, my_cpu_num,
+			       cpu_ord);
+			smp_ap_booted(my_cpu_num);
+			/* Asign a sequential CPU ordinal to each active cpu */
+			spin_lock(&barr->mutex);
+			my_cpu_ord = cpu_ord++;
+			smp_set_ordinal(my_cpu_num, my_cpu_ord);
+			spin_unlock(&barr->mutex);
+			btrace(my_cpu_num, __LINE__, "AP_Done   ", 0, my_cpu_num,
+			       my_cpu_ord);
 		}
-		win1_end = (high_test_adr >> 12);
-
-		/* Adjust the map to not test the page at 939k,
-		 *  reserved for locks */
-		v->pmap[0].end--;
-
-		find_ticks_for_pass();
-       	    } else {
-		/* APs only, Register the APs */
-		btrace(my_cpu_num, __LINE__, "AP_Start  ", 0, my_cpu_num,
-			cpu_ord);
-		smp_ap_booted(my_cpu_num);
-		/* Asign a sequential CPU ordinal to each active cpu */
-		spin_lock(&barr->mutex);
-		my_cpu_ord = cpu_ord++;
-		smp_set_ordinal(my_cpu_num, my_cpu_ord);
-		spin_unlock(&barr->mutex);
-		btrace(my_cpu_num, __LINE__, "AP_Done   ", 0, my_cpu_num,
-			my_cpu_ord);
-	    }
-
 	} else {
-	    /* Unlock after a relocation */
-	    spin_unlock(&barr->mutex);
-	    /* Get the CPU ordinal since it is lost during relocation */
-	    my_cpu_ord = smp_my_ord_num(my_cpu_num);
-	    btrace(my_cpu_num, __LINE__, "Reloc_Done",0,my_cpu_num,my_cpu_ord);
+		/* Unlock after a relocation */
+		spin_unlock(&barr->mutex);
+		/* Get the CPU ordinal since it is lost during relocation */
+		my_cpu_ord = smp_my_ord_num(my_cpu_num);
+		btrace(my_cpu_num, __LINE__, "Reloc_Done", 0, my_cpu_num, my_cpu_ord);
 	}
 
 	/* A barrier to insure that all of the CPUs are done with startup */
@@ -485,52 +483,51 @@
 	/* Setup Memory Management and measure memory speed, we do it here
 	 * because we need all of the available CPUs */
 	if (start_seq < 2) {
+		/* Enable floating point processing */
+		if (cpu_id.fid.bits.fpu)
+			__asm__ __volatile__ (
+				"movl %%cr0, %%eax\n\t"
+				"andl $0x7, %%eax\n\t"
+				"movl %%eax, %%cr0\n\t"
+				: :
+				: "ax"
+			);
+		if (cpu_id.fid.bits.sse)
+			__asm__ __volatile__ (
+				"movl %%cr4, %%eax\n\t"
+				"orl $0x00000200, %%eax\n\t"
+				"movl %%eax, %%cr4\n\t"
+				: :
+				: "ax"
+			);
 
-	   /* Enable floating point processing */
-	   if (cpu_id.fid.bits.fpu)
-        	__asm__ __volatile__ (
-		    "movl %%cr0, %%eax\n\t"
-		    "andl $0x7, %%eax\n\t"
-		    "movl %%eax, %%cr0\n\t"
-                    : :
-                    : "ax"
-                );
-	   if (cpu_id.fid.bits.sse)
-        	__asm__ __volatile__ (
-                    "movl %%cr4, %%eax\n\t"
-                    "orl $0x00000200, %%eax\n\t"
-                    "movl %%eax, %%cr4\n\t"
-                    : :
-                    : "ax"
-                );
-
-	    btrace(my_cpu_num, __LINE__, "Mem Mgmnt ", 1, cpu_id.fid.bits.pae, cpu_id.fid.bits.lm);
-	    /* Setup memory management modes */
-	    /* If we have PAE, turn it on */
-	    if (cpu_id.fid.bits.pae == 1) {
-		__asm__ __volatile__(
-                    "movl %%cr4, %%eax\n\t"
-                    "orl $0x00000020, %%eax\n\t"
-                    "movl %%eax, %%cr4\n\t"
-                    : :
-                    : "ax"
-                );
-        cprint(LINE_TITLE+1, COL_MODE, "(PAE Mode)");
-       	    }
-	    /* If this is a 64 CPU enable long mode */
-	    if (cpu_id.fid.bits.lm == 1) {
-		__asm__ __volatile__(
-		    "movl $0xc0000080, %%ecx\n\t"
-		    "rdmsr\n\t"
-		    "orl $0x00000100, %%eax\n\t"
-		    "wrmsr\n\t"
-		    : :
-		    : "ax", "cx"
-		);
-		cprint(LINE_TITLE+1, COL_MODE, "(X64 Mode)");
-            }
-	    /* Get the memory Speed with all CPUs */
-	    get_mem_speed(my_cpu_num, num_cpus);
+		btrace(my_cpu_num, __LINE__, "Mem Mgmnt ", 1, cpu_id.fid.bits.pae, cpu_id.fid.bits.lm);
+		/* Setup memory management modes */
+		/* If we have PAE, turn it on */
+		if (cpu_id.fid.bits.pae == 1) {
+			__asm__ __volatile__ (
+				"movl %%cr4, %%eax\n\t"
+				"orl $0x00000020, %%eax\n\t"
+				"movl %%eax, %%cr4\n\t"
+				: :
+				: "ax"
+			);
+			cprint(LINE_TITLE+1, COL_MODE, "(PAE Mode)");
+		}
+		/* If this is a 64 CPU enable long mode */
+		if (cpu_id.fid.bits.lm == 1) {
+			__asm__ __volatile__ (
+				"movl $0xc0000080, %%ecx\n\t"
+				"rdmsr\n\t"
+				"orl $0x00000100, %%eax\n\t"
+				"wrmsr\n\t"
+				: :
+				: "ax", "cx"
+			);
+			cprint(LINE_TITLE+1, COL_MODE, "(X64 Mode)");
+		}
+		/* Get the memory Speed with all CPUs */
+		get_mem_speed(my_cpu_num, num_cpus);
 	}
 
 	/* Set the initialized flag only after all of the CPU's have
@@ -541,226 +538,221 @@
 
 	/* Loop through all tests */
 	while (1) {
-	    /* If the restart flag is set all initial params */
-	    if (restart_flag) {
-		set_defaults();
-		continue;
-	    }
-            /* Skip single CPU tests if we are using only one CPU */
-            if (tseq[test].cpu_sel == -1 &&
-                    (num_cpus == 1 || cpu_mode != CPM_ALL)) {
-                test++;
-                continue;
-            }
-
-	    test_setup();
-
-	    /* Loop through all possible windows */
-	    while (win_next <= ((ulong)v->pmap[v->msegs-1].end + WIN_SZ)) {
-
-		/* Main scheduling barrier */
-		cprint(8, my_cpu_num+7, "W");
-		btrace(my_cpu_num, __LINE__, "Sched_Barr", 1,window,win_next);
-		barrier();
-
-		/* Don't go over the 8TB PAE limit */
-		if (win_next > MAX_MEM) {
-			break;
+		/* If the restart flag is set all initial params */
+		if (restart_flag) {
+			set_defaults();
+			continue;
+		}
+		/* Skip single CPU tests if we are using only one CPU */
+		if (tseq[test].cpu_sel == -1 &&
+		    (num_cpus == 1 || cpu_mode != CPM_ALL)) {
+			test++;
+			continue;
 		}
 
-		/* For the bit fade test, #11, we cannot relocate so bump the
-		 * window to 1 */
-		if (tseq[test].pat == 11 && window == 0) {
-			window = 1;
+		test_setup();
+
+		/* Loop through all possible windows */
+		while (win_next <= ((ulong)v->pmap[v->msegs-1].end + WIN_SZ)) {
+			/* Main scheduling barrier */
+			cprint(8, my_cpu_num+7, "W");
+			btrace(my_cpu_num, __LINE__, "Sched_Barr", 1, window, win_next);
+			barrier();
+
+			/* Don't go over the 8TB PAE limit */
+			if (win_next > MAX_MEM) {
+				break;
+			}
+
+			/* For the bit fade test, #11, we cannot relocate so bump the
+			 * window to 1 */
+			if (tseq[test].pat == 11 && window == 0) {
+				window = 1;
+			}
+
+			/* Relocate if required */
+			if (window != 0 && (ulong)&_start != LOW_TEST_ADR) {
+				btrace(my_cpu_num, __LINE__, "Sched_RelL", 1, 0, 0);
+				run_at(LOW_TEST_ADR, my_cpu_num);
+			}
+			if (window == 0 && v->plim_lower >= win0_start) {
+				window++;
+			}
+			if (window == 0 && (ulong)&_start == LOW_TEST_ADR) {
+				btrace(my_cpu_num, __LINE__, "Sched_RelH", 1, 0, 0);
+				run_at(high_test_adr, my_cpu_num);
+			}
+
+			/* Decide which CPU(s) to use */
+			btrace(my_cpu_num, __LINE__, "Sched_CPU0", 1, cpu_sel,
+			       tseq[test].cpu_sel);
+			run = 1;
+			switch (cpu_mode) {
+			case CPM_RROBIN:
+			case CPM_SEQ:
+				/* Select a single CPU */
+				if (my_cpu_ord == cpu_sel) {
+					mstr_cpu = cpu_sel;
+					run_cpus = 1;
+				} else {
+					run = 0;
+				}
+				break;
+			case CPM_ALL:
+				/* Use all CPUs */
+				if (tseq[test].cpu_sel == -1) {
+					/* Round robin through all of the CPUs */
+					if (my_cpu_ord == cpu_sel) {
+						mstr_cpu = cpu_sel;
+						run_cpus = 1;
+					} else {
+						run = 0;
+					}
+				} else {
+					/* Use the number of CPUs specified by the test,
+					 * Starting with zero */
+					if (my_cpu_ord >= tseq[test].cpu_sel) {
+						run = 0;
+					}
+					/* Set the master CPU to the highest CPU number
+					 * that has been selected */
+					if (act_cpus < tseq[test].cpu_sel) {
+						mstr_cpu = act_cpus-1;
+						run_cpus = act_cpus;
+					} else {
+						mstr_cpu = tseq[test].cpu_sel-1;
+						run_cpus = tseq[test].cpu_sel;
+					}
+				}
+			}
+			btrace(my_cpu_num, __LINE__, "Sched_CPU1", 1, run_cpus, run);
+			barrier();
+			dprint(9, 7, run_cpus, 2, 0);
+
+			/* Setup a sub barrier for only the selected CPUs */
+			if (my_cpu_ord == mstr_cpu) {
+				s_barrier_init(run_cpus);
+			}
+
+			/* Make sure the the sub barrier is ready before proceeding */
+			barrier();
+
+			/* Not selected CPUs go back to the scheduling barrier */
+			if (run == 0) {
+				continue;
+			}
+			cprint(8, my_cpu_num+7, "-");
+			btrace(my_cpu_num, __LINE__, "Sched_Win0", 1, window, win_next);
+
+			/* Do we need to exit */
+			if (reloc_pending) {
+				reloc_internal(my_cpu_num);
+			}
+
+			if (my_cpu_ord == mstr_cpu) {
+				switch (window) {
+				/* Special case for relocation */
+				case 0:
+					winx.start = 0;
+					winx.end = win1_end;
+					window++;
+					break;
+				/* Special case for first segment */
+				case 1:
+					winx.start = win0_start;
+					winx.end = WIN_SZ;
+					win_next += WIN_SZ;
+					window++;
+					break;
+				/* For all other windows */
+				default:
+					winx.start = win_next;
+					win_next += WIN_SZ;
+					winx.end = win_next;
+				}
+				btrace(my_cpu_num, __LINE__, "Sched_Win1", 1, winx.start,
+				       winx.end);
+
+				/* Find the memory areas to test */
+				segs = compute_segments(winx, my_cpu_num);
+			}
+			s_barrier();
+			btrace(my_cpu_num, __LINE__, "Sched_Win2", 1, segs,
+			       v->map[0].pbase_addr);
+
+			if (segs == 0) {
+				/* No memory in this window so skip it */
+				continue;
+			}
+
+			/* map in the window... */
+			if (map_page(v->map[0].pbase_addr) < 0) {
+				/* Either there is no PAE or we are at the PAE limit */
+				break;
+			}
+
+			btrace(my_cpu_num, __LINE__, "Strt_Test ", 1, my_cpu_num,
+			       my_cpu_ord);
+			do_test(my_cpu_ord);
+			btrace(my_cpu_num, __LINE__, "End_Test  ", 1, my_cpu_num,
+			       my_cpu_ord);
+
+			paging_off();
+		} /* End of window loop */
+
+		s_barrier();
+		btrace(my_cpu_num, __LINE__, "End_Win   ", 1, test, window);
+
+		/* Setup for the next set of windows */
+		win_next = 0;
+		window = 0;
+		bail = 0;
+
+		/* Only the master CPU does the end of test housekeeping */
+		if (my_cpu_ord != mstr_cpu) {
+			continue;
 		}
 
-		/* Relocate if required */
-		if (window != 0 && (ulong)&_start != LOW_TEST_ADR) {
-			btrace(my_cpu_num, __LINE__, "Sched_RelL", 1,0,0);
-			run_at(LOW_TEST_ADR, my_cpu_num);
-	        }
-		if (window == 0 && v->plim_lower >= win0_start) {
-			window++;
-		}
-		if (window == 0 && (ulong)&_start == LOW_TEST_ADR) {
-			btrace(my_cpu_num, __LINE__, "Sched_RelH", 1,0,0);
-			run_at(high_test_adr, my_cpu_num);
+		/* Special handling for the bit fade test #11 */
+		if (tseq[test].pat == 11 && bitf_seq != 6) {
+			/* Keep going until the sequence is complete. */
+			bitf_seq++;
+			continue;
+		} else {
+			bitf_seq = 0;
 		}
 
-		/* Decide which CPU(s) to use */
-		btrace(my_cpu_num, __LINE__, "Sched_CPU0",1,cpu_sel,
-			tseq[test].cpu_sel);
-		run = 1;
-		switch(cpu_mode) {
+		/* Select advancement of CPUs and next test */
+		switch (cpu_mode) {
 		case CPM_RROBIN:
+			if (++cpu_sel >= act_cpus) {
+				cpu_sel = 0;
+			}
+			next_test();
+			break;
 		case CPM_SEQ:
-			/* Select a single CPU */
-			if (my_cpu_ord == cpu_sel) {
-				mstr_cpu = cpu_sel;
-				run_cpus = 1;
-	    		} else {
-				run = 0;
+			if (++cpu_sel >= act_cpus) {
+				cpu_sel = 0;
+				next_test();
 			}
 			break;
 		case CPM_ALL:
-		    /* Use all CPUs */
-		    if (tseq[test].cpu_sel == -1) {
-			/* Round robin through all of the CPUs */
-			if (my_cpu_ord == cpu_sel) {
-				mstr_cpu = cpu_sel;
-				run_cpus = 1;
-	    		} else {
-				run = 0;
-			}
-		    } else {
-			/* Use the number of CPUs specified by the test,
-			 * Starting with zero */
-			if (my_cpu_ord >= tseq[test].cpu_sel) {
-				run = 0;
-			}
-			/* Set the master CPU to the highest CPU number
-			 * that has been selected */
-			if (act_cpus < tseq[test].cpu_sel) {
-				mstr_cpu = act_cpus-1;
-				run_cpus = act_cpus;
+			if (tseq[test].cpu_sel == -1) {
+				/* Do the same test for each CPU */
+				if (++cpu_sel >= act_cpus) {
+					cpu_sel = 0;
+					next_test();
+				} else {
+					continue;
+				}
 			} else {
-				mstr_cpu = tseq[test].cpu_sel-1;
-				run_cpus = tseq[test].cpu_sel;
+				next_test();
 			}
-		    }
-		}
-		btrace(my_cpu_num, __LINE__, "Sched_CPU1",1,run_cpus,run);
-		barrier();
-		dprint(9, 7, run_cpus, 2, 0);
+		} //????
+		btrace(my_cpu_num, __LINE__, "Next_CPU  ", 1, cpu_sel, test);
 
-		/* Setup a sub barrier for only the selected CPUs */
-		if (my_cpu_ord == mstr_cpu) {
-			s_barrier_init(run_cpus);
-		}
-
-		/* Make sure the the sub barrier is ready before proceeding */
-		barrier();
-
-		/* Not selected CPUs go back to the scheduling barrier */
-		if (run == 0 ) {
-			continue;
-		}
-		cprint(8, my_cpu_num+7, "-");
-		btrace(my_cpu_num, __LINE__, "Sched_Win0",1,window,win_next);
-
-		/* Do we need to exit */
-		if(reloc_pending) {
-		    reloc_internal(my_cpu_num);
-	 	}
-
-		if (my_cpu_ord == mstr_cpu) {
-		    switch (window) {
-		    /* Special case for relocation */
-		    case 0:
-			winx.start = 0;
-			winx.end = win1_end;
-			window++;
-			break;
-		    /* Special case for first segment */
-		    case 1:
-			winx.start = win0_start;
-			winx.end = WIN_SZ;
-			win_next += WIN_SZ;
-			window++;
-			break;
-		    /* For all other windows */
-		    default:
-			winx.start = win_next;
-			win_next += WIN_SZ;
-			winx.end = win_next;
-		    }
-		    btrace(my_cpu_num,__LINE__,"Sched_Win1",1,winx.start,
-				winx.end);
-
-	            /* Find the memory areas to test */
-	            segs = compute_segments(winx, my_cpu_num);
-		}
-		s_barrier();
-		btrace(my_cpu_num,__LINE__,"Sched_Win2",1,segs,
-			v->map[0].pbase_addr);
-
-	        if (segs == 0) {
-		/* No memory in this window so skip it */
-		    continue;
-	        }
-
-		/* map in the window... */
-		if (map_page(v->map[0].pbase_addr) < 0) {
-		    /* Either there is no PAE or we are at the PAE limit */
-		    break;
-		}
-
-		btrace(my_cpu_num, __LINE__, "Strt_Test ",1,my_cpu_num,
-			my_cpu_ord);
-		do_test(my_cpu_ord);
-		btrace(my_cpu_num, __LINE__, "End_Test  ",1,my_cpu_num,
-			my_cpu_ord);
-
-            	paging_off();
-
-	    } /* End of window loop */
-
-	    s_barrier();
-	    btrace(my_cpu_num, __LINE__, "End_Win   ",1,test, window);
-
-	    /* Setup for the next set of windows */
-	    win_next = 0;
-	    window = 0;
-	    bail = 0;
-
-	    /* Only the master CPU does the end of test housekeeping */
-	    if (my_cpu_ord != mstr_cpu) {
-		continue;
-	    }
-
-	    /* Special handling for the bit fade test #11 */
-	    if (tseq[test].pat == 11 && bitf_seq != 6) {
-		/* Keep going until the sequence is complete. */
-		bitf_seq++;
-		continue;
-	    } else {
-		bitf_seq = 0;
-	    }
-
-	    /* Select advancement of CPUs and next test */
-	    switch(cpu_mode) {
-	    case CPM_RROBIN:
-		if (++cpu_sel >= act_cpus) {
-		    cpu_sel = 0;
-		}
-		next_test();
-		break;
-	    case CPM_SEQ:
-		if (++cpu_sel >= act_cpus) {
-		    cpu_sel = 0;
-		    next_test();
-		}
-		break;
-	    case CPM_ALL:
-	      if (tseq[test].cpu_sel == -1)
-	      	{
-			    /* Do the same test for each CPU */
-			    if (++cpu_sel >= act_cpus)
-			    	{
-				cpu_sel = 0;
-			        next_test();
-			    	} else {
-			        continue;
-			    	}
-	        } else {
-		    		next_test();
-					}
-	    } //????
-	    btrace(my_cpu_num, __LINE__, "Next_CPU  ",1,cpu_sel,test);
-
-	    /* If this was the last test then we finished a pass */
-	  if (pass_flag)
-	  	{
+		/* If this was the last test then we finished a pass */
+		if (pass_flag) {
 			pass_flag = 0;
 
 			v->pass++;
@@ -769,23 +761,21 @@
 			find_ticks_for_pass();
 			ltest = -1;
 
-			if (v->ecount == 0)
-				{
-			    /* If onepass is enabled and we did not get any errors
-			     * reboot to exit the test */
-			    if (onepass) {	reboot();   }
-			    if (!btflag) cprint(LINE_MSG, COL_MSG-8, "** Pass complete, no errors, press Esc to exit **");
-					if(BEEP_END_NO_ERROR)
-						{
-							beep(1000);
-							beep(2000);
-							beep(1000);
-							beep(2000);
-						}
+			if (v->ecount == 0) {
+				/* If onepass is enabled and we did not get any errors
+				 * reboot to exit the test */
+				if (onepass) {      reboot();   }
+				if (!btflag) cprint(LINE_MSG, COL_MSG-8, "** Pass complete, no errors, press Esc to exit **");
+				if (BEEP_END_NO_ERROR) {
+					beep(1000);
+					beep(2000);
+					beep(1000);
+					beep(2000);
 				}
-	    }
+			}
+		}
 
-	    bail=0;
+		bail=0;
 	} /* End test loop */
 }
 
@@ -796,8 +786,8 @@
 
 	/* See if a specific test has been selected */
 	if (v->testsel >= 0) {
-                test = v->testsel;
-        }
+		test = v->testsel;
+	}
 
 	/* Only do the setup if this is a new test */
 	if (test == ltest) {
@@ -814,7 +804,7 @@
 	}
 
 	/* Set the number of iterations. We only do half of the iterations */
-        /* on the first pass */
+	/* on the first pass */
 	//dprint(LINE_INFO, 28, c_iter, 3, 0);
 	test_ticks = find_ticks_for_test(test);
 	nticks = 0;
@@ -837,34 +827,32 @@
 	unsigned long p0=0, p1=0, p2=0;
 
 	if (my_ord == mstr_cpu) {
-	  if ((ulong)&_start > LOW_TEST_ADR) {
-		/* Relocated so we need to test all selected lower memory */
-		v->map[0].start = mapping(v->plim_lower);
+		if ((ulong)&_start > LOW_TEST_ADR) {
+			/* Relocated so we need to test all selected lower memory */
+			v->map[0].start = mapping(v->plim_lower);
 
-		/* Good 'ol Legacy USB_WAR */
-		if (v->map[0].start < (ulong*)0x500)
-		{
-    	v->map[0].start = (ulong*)0x500;
+			/* Good 'ol Legacy USB_WAR */
+			if (v->map[0].start < (ulong*)0x500) {
+				v->map[0].start = (ulong*)0x500;
+			}
+
+			cprint(LINE_PAT, COL_MID+25, " R");
+		} else {
+			cprint(LINE_PAT, COL_MID+25, "  ");
 		}
 
-		cprint(LINE_PAT, COL_MID+25, " R");
-	    } else {
-		cprint(LINE_PAT, COL_MID+25, "  ");
-	    }
-
-	    /* Update display of memory segments being tested */
-	    p0 = page_of(v->map[0].start);
-	    p1 = page_of(v->map[segs-1].end);
-	    aprint(LINE_RANGE, COL_MID+9, p0);
-	    cprint(LINE_RANGE, COL_MID+14, " - ");
-	    aprint(LINE_RANGE, COL_MID+17, p1);
-	    aprint(LINE_RANGE, COL_MID+25, p1-p0);
-	    cprint(LINE_RANGE, COL_MID+30, " of ");
-	    aprint(LINE_RANGE, COL_MID+34, v->selected_pages);
+		/* Update display of memory segments being tested */
+		p0 = page_of(v->map[0].start);
+		p1 = page_of(v->map[segs-1].end);
+		aprint(LINE_RANGE, COL_MID+9, p0);
+		cprint(LINE_RANGE, COL_MID+14, " - ");
+		aprint(LINE_RANGE, COL_MID+17, p1);
+		aprint(LINE_RANGE, COL_MID+25, p1-p0);
+		cprint(LINE_RANGE, COL_MID+30, " of ");
+		aprint(LINE_RANGE, COL_MID+34, v->selected_pages);
 	}
 
-	switch(tseq[test].pat) {
-
+	switch (tseq[test].pat) {
 	/* Do the testing according to the selected pattern */
 
 	case 0: /* Address test, walking ones (test #0) */
@@ -882,16 +870,16 @@
 		break;
 
 	case 3:
-	case 4:	/* Moving inversions, all ones and zeros (tests #3, 4) */
+	case 4: /* Moving inversions, all ones and zeros (tests #3, 4) */
 		p1 = 0;
 		p2 = ~p1;
 		s_barrier();
-		movinv1(c_iter,p1,p2,my_ord);
+		movinv1(c_iter, p1, p2, my_ord);
 		BAILOUT;
 
 		/* Switch patterns */
 		s_barrier();
-		movinv1(c_iter,p2,p1,my_ord);
+		movinv1(c_iter, p2, p1, my_ord);
 		BAILOUT;
 		break;
 
@@ -901,12 +889,12 @@
 			p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24);
 			p2 = ~p1;
 			s_barrier();
-			movinv1(c_iter,p1,p2, my_ord);
+			movinv1(c_iter, p1, p2, my_ord);
 			BAILOUT;
 
 			/* Switch patterns */
 			s_barrier();
-			movinv1(c_iter,p2,p1, my_ord);
+			movinv1(c_iter, p2, p1, my_ord);
 			BAILOUT;
 		}
 		break;
@@ -914,13 +902,13 @@
 	case 6: /* Random Data (test #6) */
 		/* Seed the random number generator */
 		if (my_ord == mstr_cpu) {
-		    if (cpu_id.fid.bits.rdtsc) {
-                	asm __volatile__ ("rdtsc":"=a" (sp1),"=d" (sp2));
-        	    } else {
-                	sp1 = 521288629 + v->pass;
-                	sp2 = 362436069 - v->pass;
-        	    }
-		    rand_seed(sp1, sp2, 0);
+			if (cpu_id.fid.bits.rdtsc) {
+				asm __volatile__ ("rdtsc" : "=a" (sp1), "=d" (sp2));
+			} else {
+				sp1 = 521288629 + v->pass;
+				sp2 = 362436069 - v->pass;
+			}
+			rand_seed(sp1, sp2, 0);
 		}
 
 		s_barrier();
@@ -930,7 +918,7 @@
 				sp2 = ~p1;
 			}
 			s_barrier();
-			movinv1(2,sp1,sp2, my_ord);
+			movinv1(2, sp1, sp2, my_ord);
 			BAILOUT;
 		}
 		break;
@@ -944,11 +932,11 @@
 	case 8: /* Moving inversions, 32 bit shifting pattern (test #8) */
 		for (i=0, p1=1; p1; p1=p1<<1, i++) {
 			s_barrier();
-			movinv32(c_iter,p1, 1, 0x80000000, 0, i, my_ord);
+			movinv32(c_iter, p1, 1, 0x80000000, 0, i, my_ord);
 			BAILOUT;
 			s_barrier();
-			movinv32(c_iter,~p1, 0xfffffffe,
-				0x7fffffff, 1, i, my_ord);
+			movinv32(c_iter, ~p1, 0xfffffffe,
+			         0x7fffffff, 1, i, my_ord);
 			BAILOUT;
 		}
 		break;
@@ -979,9 +967,9 @@
 		break;
 
 	case 11: /* Bit fade test, fill (test #11) */
-		/* Use a sequence to process all windows for each stage */
-		switch(bitf_seq) {
-		case 0:	/* Fill all of memory 0's */
+		 /* Use a sequence to process all windows for each stage */
+		switch (bitf_seq) {
+		case 0: /* Fill all of memory 0's */
 			bit_fade_fill(0, my_ord);
 			bitf_sleep = 1;
 			break;
@@ -995,7 +983,7 @@
 		case 2: /* Now check all of memory for changes */
 			bit_fade_chk(0, my_ord);
 			break;
-		case 3:	/* Fill all of memory 1's */
+		case 3: /* Fill all of memory 1's */
 			bit_fade_fill(-1, my_ord);
 			bitf_sleep = 1;
 			break;
@@ -1023,7 +1011,7 @@
 			/* Switch patterns */
 			p2 = p1;
 			p1 = ~p2;
-			modtst(i, c_iter, p1,p2, my_ord);
+			modtst(i, c_iter, p1, p2, my_ord);
 			BAILOUT;
 		}
 		break;
@@ -1053,14 +1041,14 @@
 int find_chunks(int tst)
 {
 	int i, j, sg, wmax, ch;
-	struct pmap twin={0,0};
+	struct pmap twin={0, 0};
 	unsigned long wnxt = WIN_SZ;
 	unsigned long len;
 
 	wmax = MAX_MEM/WIN_SZ+2;  /* The number of 2 GB segments +2 */
 	/* Compute the number of SPINSZ memory segments */
 	ch = 0;
-	for(j = 0; j < wmax; j++) {
+	for (j = 0; j < wmax; j++) {
 		/* special case for relocation */
 		if (j == 0) {
 			twin.start = 0;
@@ -1080,25 +1068,25 @@
 			twin.end = wnxt;
 		}
 
-	        /* Find the memory areas I am going to test */
+		/* Find the memory areas I am going to test */
 		sg = compute_segments(twin, -1);
-		for(i = 0; i < sg; i++) {
+		for (i = 0; i < sg; i++) {
 			len = v->map[i].end - v->map[i].start;
 
 			if (cpu_mode == CPM_ALL && num_cpus > 1) {
-				switch(tseq[tst].pat) {
+				switch (tseq[tst].pat) {
 				case 2:
 				case 4:
 				case 5:
 				case 6:
 				case 9:
 				case 10:
-				    len /= act_cpus;
-				    break;
+					len /= act_cpus;
+					break;
 				case 7:
 				case 8:
-				    len /= act_cpus;
-				    break;
+					len /= act_cpus;
+					break;
 				}
 			}
 			ch += (len + SPINSZ -1)/SPINSZ;
@@ -1120,8 +1108,8 @@
 	while (tseq[i].cpu_sel != 0) {
 		/* Skip tests 2 and 4 if we are using 1 cpu */
 		if (act_cpus == 1 && (i == 2 || i == 4)) {
-		    i++;
-		    continue;
+			i++;
+			continue;
 		}
 		v->pass_ticks += find_ticks_for_test(i);
 		i++;
@@ -1140,14 +1128,14 @@
 	ch = find_chunks(tst);
 
 	/* Set the number of iterations. We only do 1/2 of the iterations */
-        /* on the first pass */
+	/* on the first pass */
 	if (v->pass == 0) {
 		c = tseq[tst].iter/FIRST_DIVISER;
 	} else {
 		c = tseq[tst].iter;
 	}
 
-	switch(tseq[tst].pat) {
+	switch (tseq[tst].pat) {
 	case 0: /* Address test, walking ones */
 		ticks = 2;
 		break;
@@ -1262,34 +1250,33 @@
 		hprint(LINE_SCROLL+(2*i+1), 46, i);
 
 		cprint(LINE_SCROLL+(2*i+2), 0,
-			"                                        "
-			"                                        ");
+		       "                                        "
+		       "                                        ");
 		cprint(LINE_SCROLL+(2*i+3), 0,
-			"                                        "
-			"                                        ");
+		       "                                        "
+		       "                                        ");
 #endif
 		if ((start < end) && (start < wend) && (end > wstart)) {
 			v->map[sg].pbase_addr = start;
 			v->map[sg].start = mapping(start);
 			v->map[sg].end = emapping(end);
 #if 0
-		hprint(LINE_SCROLL+(sg+1), 0, sg);
-		hprint(LINE_SCROLL+(sg+1), 12, v->map[sg].pbase_addr);
-		hprint(LINE_SCROLL+(sg+1), 22, start);
-		hprint(LINE_SCROLL+(sg+1), 32, end);
-		hprint(LINE_SCROLL+(sg+1), 42, mapping(start));
-		hprint(LINE_SCROLL+(sg+1), 52, emapping(end));
-		cprint(LINE_SCROLL+(sg+2), 0,
-			"                                        "
-			"                                        ");
+			hprint(LINE_SCROLL+(sg+1), 0, sg);
+			hprint(LINE_SCROLL+(sg+1), 12, v->map[sg].pbase_addr);
+			hprint(LINE_SCROLL+(sg+1), 22, start);
+			hprint(LINE_SCROLL+(sg+1), 32, end);
+			hprint(LINE_SCROLL+(sg+1), 42, mapping(start));
+			hprint(LINE_SCROLL+(sg+1), 52, emapping(end));
+			cprint(LINE_SCROLL+(sg+2), 0,
+			       "                                        "
+			       "                                        ");
 #endif
 #if 0
-		cprint(LINE_SCROLL+(2*i+1), 54, ", sg=");
-		hprint(LINE_SCROLL+(2*i+1), 59, sg);
+			cprint(LINE_SCROLL+(2*i+1), 54, ", sg=");
+			hprint(LINE_SCROLL+(2*i+1), 59, sg);
 #endif
 			sg++;
 		}
 	}
 	return (sg);
 }
-
diff --git a/memsize.c b/memsize.c
index 53c2bc6..9b01c4f 100644
--- a/memsize.c
+++ b/memsize.c
@@ -23,7 +23,7 @@
 static void memsize_820(void);
 static void memsize_801(void);
 static int sanitize_e820_map(struct e820entry *orig_map,
-struct e820entry *new_bios, short old_nr);
+                             struct e820entry *new_bios, short old_nr);
 static void memsize_coreboot();
 
 /*
@@ -35,10 +35,10 @@
 	v->test_pages = 0;
 
 	/* Get the memory size from the BIOS */
-        /* Determine the memory map */
+	/* Determine the memory map */
 	if (query_multiboot()) {
-                flag = 2;
-        } else if (query_coreboot()) {
+		flag = 2;
+	} else if (query_coreboot()) {
 		flag = 1;
 	} else if (query_pcbios()) {
 		flag = 2;
@@ -77,9 +77,9 @@
 	/* Do an insertion sort on the pmap, on an already sorted
 	 * list this should be a O(1) algorithm.
 	 */
-	for(i = 0; i < v->msegs; i++) {
+	for (i = 0; i < v->msegs; i++) {
 		/* Find where to insert the current element */
-		for(j = i -1; j >= 0; j--) {
+		for (j = i -1; j >= 0; j--) {
 			if (v->pmap[i].start > v->pmap[j].start) {
 				j++;
 				break;
@@ -90,7 +90,7 @@
 			struct pmap temp;
 			temp = v->pmap[i];
 			memmove(&v->pmap[j], &v->pmap[j+1],
-				(i -j)* sizeof(temp));
+			        (i -j)* sizeof(temp));
 			v->pmap[j] = temp;
 		}
 	}
@@ -153,13 +153,13 @@
 			v->test_pages += v->pmap[n].end - v->pmap[n].start;
 			n++;
 #if 0
-	 		int epmap = 0;
-	 		int lpmap = 0;
-	 		if(n > 12) { epmap = 34; lpmap = -12; }
-			hprint (11+n+lpmap,0+epmap,v->pmap[n-1].start);
-			hprint (11+n+lpmap,10+epmap,v->pmap[n-1].end);
-			hprint (11+n+lpmap,20+epmap,v->pmap[n-1].end - v->pmap[n-1].start);
-			dprint (11+n+lpmap,30+epmap,nm[i].type,0,0);
+			int epmap = 0;
+			int lpmap = 0;
+			if (n > 12) { epmap = 34; lpmap = -12; }
+			hprint (11+n+lpmap, 0+epmap, v->pmap[n-1].start);
+			hprint (11+n+lpmap, 10+epmap, v->pmap[n-1].end);
+			hprint (11+n+lpmap, 20+epmap, v->pmap[n-1].end - v->pmap[n-1].start);
+			dprint (11+n+lpmap, 30+epmap, nm[i].type, 0, 0);
 #endif
 		}
 	}
@@ -198,10 +198,10 @@
  *
  */
 static int sanitize_e820_map(struct e820entry *orig_map, struct e820entry *new_bios,
-	short old_nr)
+                             short old_nr)
 {
 	struct change_member {
-		struct e820entry *pbios; /* pointer to original bios entry */
+		struct e820entry  *pbios; /* pointer to original bios entry */
 		unsigned long long addr; /* address for this change point */
 	};
 	struct change_member change_point_list[2*E820MAX];
@@ -269,7 +269,7 @@
 
 	/* record all known change-points (starting and ending addresses) */
 	chgidx = 0;
-	for (i=0; i < old_nr; i++)	{
+	for (i=0; i < old_nr; i++) {
 		change_point[chgidx]->addr = biosmap[i].addr;
 		change_point[chgidx++]->pbios = &biosmap[i];
 		change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size;
@@ -278,17 +278,16 @@
 
 	/* sort change-point list by memory addresses (low -> high) */
 	still_changing = 1;
-	while (still_changing)	{
+	while (still_changing) {
 		still_changing = 0;
-		for (i=1; i < 2*old_nr; i++)  {
+		for (i=1; i < 2*old_nr; i++) {
 			/* if <current_addr> > <last_addr>, swap */
 			/* or, if current=<start_addr> & last=<end_addr>, swap */
 			if ((change_point[i]->addr < change_point[i-1]->addr) ||
-				((change_point[i]->addr == change_point[i-1]->addr) &&
-				 (change_point[i]->addr == change_point[i]->pbios->addr) &&
-				 (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
-			   )
-			{
+			    ((change_point[i]->addr == change_point[i-1]->addr) &&
+			     (change_point[i]->addr == change_point[i]->pbios->addr) &&
+			     (change_point[i-1]->addr != change_point[i-1]->pbios->addr))
+			) {
 				change_tmp = change_point[i];
 				change_point[i] = change_point[i-1];
 				change_point[i-1] = change_tmp;
@@ -298,21 +297,18 @@
 	}
 
 	/* create a new bios memory map, removing overlaps */
-	overlap_entries=0;	 /* number of entries in the overlap table */
-	new_bios_entry=0;	 /* index for creating new bios map entries */
-	last_type = 0;		 /* start with undefined memory type */
-	last_addr = 0;		 /* start with 0 as last starting address */
+	overlap_entries=0;       /* number of entries in the overlap table */
+	new_bios_entry=0;        /* index for creating new bios map entries */
+	last_type = 0;           /* start with undefined memory type */
+	last_addr = 0;           /* start with 0 as last starting address */
 	/* loop through change-points, determining affect on the new bios map */
 	for (chgidx=0; chgidx < 2*old_nr; chgidx++)
 	{
 		/* keep track of all overlapping bios entries */
-		if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr)
-		{
+		if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr) {
 			/* add map entry to overlap list (> 1 entry implies an overlap) */
 			overlap_list[overlap_entries++]=change_point[chgidx]->pbios;
-		}
-		else
-		{
+		} else {
 			/* remove entry from list (order independent, so swap with last) */
 			for (i=0; i<overlap_entries; i++)
 			{
@@ -328,16 +324,16 @@
 			if (overlap_list[i]->type > current_type)
 				current_type = overlap_list[i]->type;
 		/* continue building up new bios map based on this information */
-		if (current_type != last_type)	{
-			if (last_type != 0)	 {
+		if (current_type != last_type) {
+			if (last_type != 0) {
 				new_bios[new_bios_entry].size =
 					change_point[chgidx]->addr - last_addr;
 				/* move forward only if the new size was non-zero */
 				if (new_bios[new_bios_entry].size != 0)
 					if (++new_bios_entry >= E820MAX)
-						break; 	/* no more space left for new bios entries */
+						break;  /* no more space left for new bios entries */
 			}
-			if (current_type != 0)	{
+			if (current_type != 0) {
 				new_bios[new_bios_entry].addr = change_point[chgidx]->addr;
 				new_bios[new_bios_entry].type = current_type;
 				last_addr=change_point[chgidx]->addr;
diff --git a/patn.c b/patn.c
index 57262e9..2e35a38 100644
--- a/patn.c
+++ b/patn.c
@@ -32,26 +32,27 @@
  *  - Print a new pattern only when the pattern array is changed.
  */
 
-#define COMBINE_MASK(a,b,c,d) ((a & b & c & d) | (~a & b & ~c & d))
+#define COMBINE_MASK(a, b, c, d) ((a & b & c & d) | (~a & b & ~c & d))
 
 /* Combine two adr/mask pairs to one adr/mask pair.
  */
 void combine (ulong adr1, ulong mask1, ulong adr2, ulong mask2,
-		ulong *adr, ulong *mask) {
-
+              ulong *adr, ulong *mask)
+{
 	*mask = COMBINE_MASK (adr1, mask1, adr2, mask2);
 
 	*adr  = adr1 | adr2;
-	*adr &= *mask;	// Normalise, no fundamental need for this
+	*adr &= *mask;  // Normalise, no fundamental need for this
 }
 
 /* Count the number of addresses covered with a mask.
  */
-ulong addresses (ulong mask) {
+ulong addresses (ulong mask)
+{
 	ulong ctr=1;
 	int i=32;
 	while (i-- > 0) {
-		if (! (mask & 1)) {
+		if (!(mask & 1)) {
 			ctr += ctr;
 		}
 		mask >>= 1;
@@ -62,7 +63,8 @@
 /* Count how much more addresses would be covered by adr1/mask1 when combined
  * with adr2/mask2.
  */
-ulong combicost (ulong adr1, ulong mask1, ulong adr2, ulong mask2) {
+ulong combicost (ulong adr1, ulong mask1, ulong adr2, ulong mask2)
+{
 	ulong cost1=addresses (mask1);
 	ulong tmp, mask;
 	combine (adr1, mask1, adr2, mask2, &tmp, &mask);
@@ -72,7 +74,8 @@
 /* Find the cheapest array index to extend with the given adr/mask pair.
  * Return -1 if nothing below the given minimum cost can be found.
  */
-int cheapindex (ulong adr1, ulong mask1, ulong mincost) {
+int cheapindex (ulong adr1, ulong mask1, ulong mincost)
+{
 	int i=v->numpatn;
 	int idx=-1;
 	while (i-- > 0) {
@@ -88,11 +91,12 @@
 /* Try to find a relocation index for idx if it costs nothing.
  * Return -1 if no such index exists.
  */
-int relocateidx (int idx) {
+int relocateidx (int idx)
+{
 	ulong adr =v->patn[idx].adr;
 	ulong mask=v->patn[idx].mask;
 	int new;
-	v->patn[idx].adr ^= ~0L;	// Never select idx
+	v->patn[idx].adr ^= ~0L;        // Never select idx
 	new=cheapindex (adr, mask, 1+addresses (mask));
 	v->patn[idx].adr = adr;
 	return new;
@@ -102,13 +106,14 @@
  * This is useful to combine to `neighbouring' sections to integrate.
  * Inspired on the Buddy memalloc principle in the Linux kernel.
  */
-void relocateiffree (int idx) {
+void relocateiffree (int idx)
+{
 	int newidx=relocateidx (idx);
 	if (newidx>=0) {
 		ulong cadr, cmask;
 		combine (v->patn [newidx].adr, v->patn[newidx].mask,
 		         v->patn [   idx].adr, v->patn[   idx].mask,
-			 &cadr, &cmask);
+		         &cadr, &cmask);
 		v->patn[newidx].adr =cadr;
 		v->patn[newidx].mask=cmask;
 		if (idx < --v->numpatn) {
@@ -122,7 +127,8 @@
 /* Insert a single faulty address in the pattern array.
  * Return 1 only if the array was changed.
  */
-int insertaddress (ulong adr) {
+int insertaddress (ulong adr)
+{
 	if (cheapindex (adr, DEFAULT_MASK, 1L) != -1)
 		return 0;
 
diff --git a/pci.c b/pci.c
index 2d24453..f193a94 100644
--- a/pci.c
+++ b/pci.c
@@ -25,7 +25,7 @@
 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
 	(0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
 
-#define PCI_CONF2_ADDRESS(dev, reg)	(unsigned short)(0xC000 | (dev << 8) | reg)
+#define PCI_CONF2_ADDRESS(dev, reg)     (unsigned short)(0xC000 | (dev << 8) | reg)
 
 #define PCI_CONF3_ADDRESS(bus, dev, fn, reg) \
 	(0x80000000 | (((reg >> 8) & 0xF) << 24) | (bus << 16) | ((dev & 0x1F) << 11) | (fn << 8) | (reg & 0xFF))
@@ -38,14 +38,14 @@
 		return -1;
 
 	result = -1;
-	switch(pci_conf_type) {
+	switch (pci_conf_type) {
 	case PCI_CONF_TYPE_1:
-		if(reg < 256){
+		if (reg < 256) {
 			outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
-		}else{
+		} else {
 			outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
 		}
-		switch(len) {
+		switch (len) {
 		case 1:  *value = inb(0xCFC + (reg & 3)); result = 0; break;
 		case 2:  *value = inw(0xCFC + (reg & 2)); result = 0; break;
 		case 4:  *value = inl(0xCFC); result = 0; break;
@@ -55,7 +55,7 @@
 		outb(0xF0 | (fn << 1), 0xCF8);
 		outb(bus, 0xCFA);
 
-		switch(len) {
+		switch (len) {
 		case 1:  *value = inb(PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
 		case 2:  *value = inw(PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
 		case 4:  *value = inl(PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
@@ -75,31 +75,30 @@
 
 	result = -1;
 
-	switch(pci_conf_type)
-	{
-		case PCI_CONF_TYPE_1:
-			if(reg < 256){
-				outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
-			}else{
-				outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
-			}
-			switch(len) {
-			case 1:  outb(value, 0xCFC + (reg & 3)); result = 0; break;
-			case 2:  outw(value, 0xCFC + (reg & 2)); result = 0; break;
-			case 4:  outl(value, 0xCFC); result = 0; break;
-			}
-			break;
-		case PCI_CONF_TYPE_2:
-			outb(0xF0 | (fn << 1), 0xCF8);
-			outb(bus, 0xCFA);
+	switch (pci_conf_type) {
+	case PCI_CONF_TYPE_1:
+		if (reg < 256) {
+			outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
+		} else {
+			outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
+		}
+		switch (len) {
+		case 1:  outb(value, 0xCFC + (reg & 3)); result = 0; break;
+		case 2:  outw(value, 0xCFC + (reg & 2)); result = 0; break;
+		case 4:  outl(value, 0xCFC); result = 0; break;
+		}
+		break;
+	case PCI_CONF_TYPE_2:
+		outb(0xF0 | (fn << 1), 0xCF8);
+		outb(bus, 0xCFA);
 
-			switch(len) {
-			case 1: outb(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
-			case 2: outw(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
-			case 4: outl(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
-			}
-			outb(0, 0xCF8);
-			break;
+		switch (len) {
+		case 1: outb(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
+		case 2: outw(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
+		case 4: outl(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
+		}
+		outb(0, 0xCF8);
+		break;
 	}
 	return result;
 }
@@ -126,43 +125,41 @@
 static int pci_check_direct(void)
 {
 	unsigned char tmpCFB;
-	unsigned int  tmpCF8;
+	unsigned int tmpCF8;
 
 	if (cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF) {
-			pci_conf_type = PCI_CONF_TYPE_1;
-			return 0;
+		pci_conf_type = PCI_CONF_TYPE_1;
+		return 0;
 	} else {
-			/* Check if configuration type 1 works. */
-			pci_conf_type = PCI_CONF_TYPE_1;
-			tmpCFB = inb(0xCFB);
-			outb(0x01, 0xCFB);
-			tmpCF8 = inl(0xCF8);
-			outl(0x80000000, 0xCF8);
-			if ((inl(0xCF8) == 0x80000000) && (pci_sanity_check() == 0)) {
-				outl(tmpCF8, 0xCF8);
-				outb(tmpCFB, 0xCFB);
-				return 0;
-			}
+		/* Check if configuration type 1 works. */
+		pci_conf_type = PCI_CONF_TYPE_1;
+		tmpCFB = inb(0xCFB);
+		outb(0x01, 0xCFB);
+		tmpCF8 = inl(0xCF8);
+		outl(0x80000000, 0xCF8);
+		if ((inl(0xCF8) == 0x80000000) && (pci_sanity_check() == 0)) {
 			outl(tmpCF8, 0xCF8);
+			outb(tmpCFB, 0xCFB);
+			return 0;
+		}
+		outl(tmpCF8, 0xCF8);
 
-			/* Check if configuration type 2 works. */
+		/* Check if configuration type 2 works. */
 
-			pci_conf_type = PCI_CONF_TYPE_2;
-			outb(0x00, 0xCFB);
-			outb(0x00, 0xCF8);
-			outb(0x00, 0xCFA);
-			if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && (pci_sanity_check() == 0)) {
-				outb(tmpCFB, 0xCFB);
-				return 0;
+		pci_conf_type = PCI_CONF_TYPE_2;
+		outb(0x00, 0xCFB);
+		outb(0x00, 0xCF8);
+		outb(0x00, 0xCFA);
+		if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && (pci_sanity_check() == 0)) {
+			outb(tmpCFB, 0xCFB);
+			return 0;
+		}
 
-	}
+		outb(tmpCFB, 0xCFB);
 
-	outb(tmpCFB, 0xCFB);
-
-	/* Nothing worked return an error */
-	pci_conf_type = PCI_CONF_TYPE_NONE;
-	return -1;
-
+		/* Nothing worked return an error */
+		pci_conf_type = PCI_CONF_TYPE_NONE;
+		return -1;
 	}
 }
 
diff --git a/random.c b/random.c
index 2fb1bc3..8a965e7 100644
--- a/random.c
+++ b/random.c
@@ -15,24 +15,23 @@
 
 unsigned long rand (int cpu)
 {
-   static unsigned int a = 18000, b = 30903;
-   int me;
+	static unsigned int a = 18000, b = 30903;
+	int me;
 
-   me = cpu*16;
+	me = cpu*16;
 
-   SEED_X[me] = a*(SEED_X[me]&65535) + (SEED_X[me]>>16);
-   SEED_Y[me] = b*(SEED_Y[me]&65535) + (SEED_Y[me]>>16);
+	SEED_X[me] = a*(SEED_X[me]&65535) + (SEED_X[me]>>16);
+	SEED_Y[me] = b*(SEED_Y[me]&65535) + (SEED_Y[me]>>16);
 
-   return ((SEED_X[me]<<16) + (SEED_Y[me]&65535));
+	return ((SEED_X[me]<<16) + (SEED_Y[me]&65535));
 }
 
 
 void rand_seed( unsigned int seed1, unsigned int seed2, int cpu)
 {
-   int me;
+	int me;
 
-   me = cpu*16;
-   SEED_X[me] = seed1;
-   SEED_Y[me] = seed2;
+	me = cpu*16;
+	SEED_X[me] = seed1;
+	SEED_Y[me] = seed2;
 }
-
diff --git a/vmem.c b/vmem.c
index 5adbe14..6f857df 100644
--- a/vmem.c
+++ b/vmem.c
@@ -23,14 +23,14 @@
 		"movl %%eax, %%cr0\n\t"
 		: :
 		: "ax"
-		);
+	);
 }
 
 static void paging_on(void *pdp)
 {
 	if (!cpu_id.fid.bits.pae)
 		return;
-	__asm__ __volatile__(
+	__asm__ __volatile__ (
 		/* Load the page table address */
 		"movl %0, %%cr3\n\t"
 		/* Enable paging */
@@ -40,14 +40,14 @@
 		:
 		: "r" (pdp)
 		: "ax"
-		);
+	);
 }
 
 static void paging_on_lm(void *pml)
 {
 	if (!cpu_id.fid.bits.pae)
 		return;
-	__asm__ __volatile__(
+	__asm__ __volatile__ (
 		/* Load the page table address */
 		"movl %0, %%cr3\n\t"
 		/* Enable paging */
@@ -57,7 +57,7 @@
 		:
 		: "r" (pml)
 		: "ax"
-		);
+	);
 }
 
 int map_page(unsigned long page)
@@ -81,13 +81,13 @@
 		return -1;
 	}
 	if (cpu_id.fid.bits.lm == 0 && (page > 0x1000000)) {
-		 /* Fail, we want an address that is out of bounds (> 64GB)
+		/* Fail, we want an address that is out of bounds (> 64GB)
 		 *  for PAE and no long mode (ie. 32 bit CPU).
 		 */
 		return -1;
 	}
 	/* Compute the page table entries... */
-	for(i = 0; i < 1024; i++) {
+	for (i = 0; i < 1024; i++) {
 		/*-----------------10/30/2004 12:37PM---------------
 		 * 0xE3 --
 		 * Bit 0 = Present bit.      1 = PDE is present
@@ -118,8 +118,7 @@
 	if (page_addr < 0x80000) {
 		/* If the address is less than 1GB directly use the address */
 		result = (void *)(page_addr << 12);
-	}
-	else {
+	} else {
 		unsigned long alias;
 		alias = page_addr & 0x7FFFF;
 		alias += 0x80000;