spd: refactor code for AMD SBx00 and FCH

This patch splits code for FCH from previous one that was used both for SB800
and FCH. Initial support for FCH in AMD Mullins was included in this commit:
https://review.coreboot.org/c/memtest86plus/+/22289

Because of mentioned commit even platforms using SBx00 (device ID = 0x4385)
with revision 40 or higher were checking for base address in PMx00+1. This
broke support for e.g. apu1.

Change-Id: I9e2c6dc27e699b47a25eea760f846fb35945057b
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/memtest86plus/+/29372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/spd.c b/spd.c
index d91a242..d30e3e2 100644
--- a/spd.c
+++ b/spd.c
@@ -54,31 +54,17 @@
 
 static void sb800_get_smb(void)
 {
-	int lbyte, hbyte, result;
-	unsigned long x;
+	int lbyte, hbyte;
 
-	result = pci_conf_read(0, smbdev, smbfun, 0x08, 1, &x);
+	__outb(AMD_SMBUS_BASE_REG + 1, AMD_INDEX_IO_PORT);
+	hbyte = __inb(AMD_DATA_IO_PORT);
+	__outb(AMD_SMBUS_BASE_REG, AMD_INDEX_IO_PORT);
+	lbyte = __inb(AMD_DATA_IO_PORT);
 
-	/* if processor revision is ML_A0 or ML_A1 use different way for SMBus
-	 * IO base calculation */
-	if (x == 0x42 || x == 0x41) {
-		/* read PMx00+1 to get SmbusAsfIoBase */
-		__outb(AMD_PM_DECODE_EN_REG + 1, AMD_INDEX_IO_PORT);
-		lbyte = __inb(AMD_DATA_IO_PORT);
-
-		/* SMBus IO base is defined as {Smbus0AsfIoBase[7:0], 0x00} */
-		smbusbase = (lbyte & 0xF) << 8;
-	} else {
-		__outb(AMD_SMBUS_BASE_REG + 1, AMD_INDEX_IO_PORT);
-		lbyte = __inb(AMD_DATA_IO_PORT);
-		__outb(AMD_SMBUS_BASE_REG, AMD_INDEX_IO_PORT);
-		hbyte = __inb(AMD_DATA_IO_PORT);
-
-		smbusbase = lbyte;
-		smbusbase <<= 8;
-		smbusbase += hbyte;
-		smbusbase &= 0xFFE0;
-	}
+	smbusbase = hbyte;
+	smbusbase <<= 8;
+	smbusbase += lbyte;
+	smbusbase &= 0xFFE0;
 
 	if (smbusbase == 0xFFE0) {
 		smbusbase = 0;
@@ -103,6 +89,27 @@
 	}
 }
 
+static void fch_get_smb(void)
+{
+	int lbyte;
+	unsigned long x;
+
+	pci_conf_read(0, smbdev, smbfun, 0x08, 1, &x);
+
+	/* if processor revision is ML_A0 or ML_A1 use different way for SMBus
+	 * IO base calculation */
+	if (x == 0x42 || x == 0x41) {
+		/* read PMx00+1 to get SmbusAsfIoBase */
+		__outb(AMD_PM_DECODE_EN_REG + 1, AMD_INDEX_IO_PORT);
+		lbyte = __inb(AMD_DATA_IO_PORT);
+
+		/* SMBus IO base is defined as {Smbus0AsfIoBase[7:0], 0x00} */
+		smbusbase = (lbyte & 0xFF) << 8;
+	} else {
+		sb800_get_smb();
+	}
+}
+
 static unsigned char ich5_smb_read_byte(unsigned char adr, unsigned char cmd)
 {
 	int l1, h1, l2, h2;
@@ -223,8 +230,8 @@
 	{0x8086, 0x0f12, "Intel E3800", ich5_get_smb, ich5_read_spd},
 
 	// AMD SMBUS
-	{0x1002, 0x4385, "AMD SB600/700", sb600_get_smb, ich5_read_spd},
-	{0x1022, 0x780B, "AMD SB800/900", sb800_get_smb, ich5_read_spd},
+	{0x1002, 0x4385, "AMD SBx00", sb600_get_smb, ich5_read_spd},
+	{0x1022, 0x780B, "AMD FCH", fch_get_smb, ich5_read_spd},
 	{0, 0, "", NULL, NULL}
 };