spd: refactor code for AMD SBx00 and FCH

This patch splits code for FCH from previous one that was used both for SB800
and FCH. Initial support for FCH in AMD Mullins was included in this commit:
https://review.coreboot.org/c/memtest86plus/+/22289

Because of mentioned commit even platforms using SBx00 (device ID = 0x4385)
with revision 40 or higher were checking for base address in PMx00+1. This
broke support for e.g. apu1.

Change-Id: I9e2c6dc27e699b47a25eea760f846fb35945057b
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/memtest86plus/+/29372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
1 file changed