Fix typos

Change-Id: If39c42c06c634d76ca2a9b059fb06d406192c31b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/controller.c b/controller.c
index b3a57fa..151457f 100644
--- a/controller.c
+++ b/controller.c
@@ -43,7 +43,7 @@
 #define __ECC_CHIPKILL  16      /* Can corrected multi-errors */
 
 #define ECC_UNKNOWN      (~0UL)    /* Unknown error correcting ability/status */
-#define ECC_NONE         0       /* Doesnt support ECC (or is BIOS disabled) */
+#define ECC_NONE         0       /* Doesn't support ECC (or is BIOS disabled) */
 #define ECC_RESERVED     __ECC_UNEXPECTED  /* Reserved ECC type */
 #define ECC_DETECT       __ECC_DETECT
 #define ECC_CORRECT      (__ECC_DETECT | __ECC_CORRECT)
@@ -358,7 +358,7 @@
 		/* NEW K8 0Fh Family 90 nm */
 
 		if ((dramcl >> 19)&1) {
-			/* Fill in the correct memory capabilites */
+			/* Fill in the correct memory capabilities */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
 			ctrl.mode = ddim[(nbxcfg >> 22)&3];
 		} else {
@@ -375,7 +375,7 @@
 		/* OLD K8 130 nm */
 
 		if ((dramcl >> 17)&1) {
-			/* Fill in the correct memory capabilites */
+			/* Fill in the correct memory capabilities */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
 			ctrl.mode = ddim[(nbxcfg >> 22)&3];
 		} else {
@@ -408,7 +408,7 @@
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
 
 	if ((dramcl >> 19)&1) {
-		// Fill in the correct memory capabilites */
+		// Fill in the correct memory capabilities */
 		pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
 		ctrl.mode = ddim[(nbxcfg >> 22)&3];
 	} else {
@@ -492,7 +492,7 @@
 {
 	unsigned long dram_status;
 
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5a, 2, &dram_status);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = (dram_status & (1 << 2)) ? ECC_CORRECT : ECC_NONE;
@@ -515,7 +515,7 @@
 			if (!(ecc_status & (1 << i))) {
 				continue;
 			}
-			// Find the bank the error occured on
+			// Find the bank the error occurred on
 			bank_addr = 0x40 + (i << 1);
 
 			// Now get the information on the erroring bank
@@ -552,7 +552,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_DETECT, ECC_CORRECT, ECC_CORRECT };
 	unsigned long ecc_mode_status;
 
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(ecc_mode_status >> 10)&3];
@@ -570,7 +570,7 @@
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status);
 	// Multibit error
 	if (ecc_mode_status & (1 << 9)) {
-		// Find the bank the error occured on
+		// Find the bank the error occurred on
 		bank_addr = 0xC0 + (((ecc_mode_status >> 4) & 0xf) << 2);
 
 		// Now get the information on the erroring bank
@@ -585,7 +585,7 @@
 	}
 	// Singlebit error
 	if (ecc_mode_status & (1 << 8)) {
-		// Find the bank the error occured on
+		// Find the bank the error occurred on
 		bank_addr = 0xC0 + (((ecc_mode_status >> 0) & 0xf) << 2);
 
 		// Now get the information on the erroring bank
@@ -607,7 +607,7 @@
 
 static void setup_cnb20(void)
 {
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 	ctrl.cap = ECC_CORRECT;
 
 	/* FIXME add ECC error polling.  I don't have the documentation
@@ -782,7 +782,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_DETECT, ECC_CORRECT, ECC_CORRECT };
 	unsigned long nbxcfg;
 
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 4, &nbxcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(nbxcfg >> 7)&3];
@@ -827,7 +827,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT };
 	unsigned long mchcfg;
 
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
@@ -872,7 +872,7 @@
 	long *ptr;
 	ulong dev0, dev6;
 
-	/* Fill in the correct memory capabilites */
+	/* Fill in the correct memory capabilities */
 
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ECC_NONE;
@@ -892,7 +892,7 @@
 
 	if (((*ptr >> 18)&1) == 1) { ctrl.mode = ECC_CORRECT; }
 
-	/* Reseting state */
+	/* Resetting state */
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2,  0x81);
 }
 
@@ -1009,7 +1009,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED };
 	unsigned long drc;
 
-	// Fill in the correct memory capabilites
+	// Fill in the correct memory capabilities
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x7C, 4, &drc);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(drc >> 20)&3];
@@ -1052,7 +1052,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT };
 	unsigned long mchcfg;
 
-	// Fill in the correct memory capabilites
+	// Fill in the correct memory capabilities
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xbe, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
@@ -1091,7 +1091,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED };
 	unsigned long mchcfg;
 
-	// Fill in the correct memory capabilites
+	// Fill in the correct memory capabilities
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
@@ -1135,7 +1135,7 @@
 	unsigned long mchcfg;
 	unsigned long errsts;
 
-	// Fill in the correct memory capabilites
+	// Fill in the correct memory capabilities
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
diff --git a/defs.h b/defs.h
index b69c167..dc95556 100644
--- a/defs.h
+++ b/defs.h
@@ -15,7 +15,7 @@
  */
 #define LOW_TEST_ADR	0x00010000		/* Final adrs for test code */
 
-#define BOOTSEG		0x07c0			/* Segment adrs for inital boot */
+#define BOOTSEG		0x07c0			/* Segment adrs for initial boot */
 #define INITSEG		0x9000			/* Segment adrs for relocated boot */
 #define SETUPSEG	(INITSEG+0x20)		/* Segment adrs for relocated setup */
 #define TSTLOAD		0x1000			/* Segment adrs for load of test */
diff --git a/error.c b/error.c
index a063579..3e22186 100644
--- a/error.c
+++ b/error.c
@@ -51,7 +51,7 @@
 	/* A sporadic bug exists in test #6, with SMP enabled, that
 	 * reports false positives on < 65K-0.5MB range. I was
 	 * not able to solve this. After investigations, it seems
-	 * related to a BIOS issue similiar to the one solved by
+	 * related to a BIOS issue similar to the one solved by
 	 * USB_WAR, but for MP Table.
 	 */
 	/* Solved
@@ -121,7 +121,7 @@
 */
 
 	/* Paint the error messages on the screen red to provide a vivid */
-	/* indicator that an error has occured */
+	/* indicator that an error has occurred */
 	if ((v->printmode == PRINTMODE_ADDRESSES ||
 	     v->printmode == PRINTMODE_PATTERNS) &&
 	    v->msg_line < 24) {
diff --git a/init.c b/init.c
index 18f5299..55b1b01 100644
--- a/init.c
+++ b/init.c
@@ -278,7 +278,7 @@
 	/* Check fail safe */
 	failsafe(5000, 0x3B);
 
-	/* Initalize SMP */
+	/* Initialize SMP */
 	initialise_cpus();
 
 	for (i = 0; i <num_cpus; i++) {
@@ -625,7 +625,7 @@
 		if (result != -1) { v->fail_safe |= 0b10; }
 	}
 
-	// For 5.01 release, SMP disabled by defualt by config.h toggle
+	// For 5.01 release, SMP disabled by default by config.h toggle
 	if (CONSERVATIVE_SMP) { v->fail_safe |= 0b10; }
 }
 
diff --git a/lib.c b/lib.c
index 478a991..c36e124 100644
--- a/lib.c
+++ b/lib.c
@@ -1150,7 +1150,7 @@
 	serial_cons = 1;
 }
 
-/* Get a comma seperated list of numbers */
+/* Get a comma separated list of numbers */
 void get_list(int x, int y, int len, char *buf)
 {
 	int c, n = 0;
diff --git a/main.c b/main.c
index 010f3f6..525a87e 100644
--- a/main.c
+++ b/main.c
@@ -462,7 +462,7 @@
 			btrace(my_cpu_num, __LINE__, "AP_Start  ", 0, my_cpu_num,
 			       cpu_ord);
 			smp_ap_booted(my_cpu_num);
-			/* Asign a sequential CPU ordinal to each active cpu */
+			/* Assign a sequential CPU ordinal to each active cpu */
 			spin_lock(&barr->mutex);
 			my_cpu_ord = cpu_ord++;
 			smp_set_ordinal(my_cpu_num, my_cpu_ord);
diff --git a/smp.c b/smp.c
index ab9b8ae..ef2675a 100644
--- a/smp.c
+++ b/smp.c
@@ -33,7 +33,7 @@
 
 void barrier_init(int max)
 {
-	/* Set the adddress of the barrier structure */
+	/* Set the address of the barrier structure */
 	barr = (struct barrier_s *)0x9ff00;
         barr->lck.slock = 1;
         barr->mutex.slock = 1;
@@ -689,4 +689,4 @@
 		if (num_to_ord[i] == me) return i;
 	}
 	return -1;
-}
\ No newline at end of file
+}
diff --git a/test.c b/test.c
index d20f13d..a91b3fe 100644
--- a/test.c
+++ b/test.c
@@ -1301,12 +1301,12 @@
 
 					//
 					// At the end of all this
-					// - the second half equals the inital value of the first half
+					// - the second half equals the initial value of the first half
 					// - the first half is right shifted 32-bytes (with wrapping)
 					//
 
 					// Move first half to second half
-					"movl %1,%%edi\n\t" // Destionation, pp (mid point)
+					"movl %1,%%edi\n\t" // Destination, pp (mid point)
 					"movl %0,%%esi\n\t" // Source, p (start point)
 					"movl %2,%%ecx\n\t" // Length, len (size of a half in DWORDS)
 					"rep\n\t"
diff --git a/test.h b/test.h
index f772a44..f7b9ec0 100644
--- a/test.h
+++ b/test.h
@@ -271,7 +271,7 @@
 
 #define MAX_MEM_SEGMENTS E820MAX
 
-/* Define common variables accross relocations of memtest86 */
+/* Define common variables across relocations of memtest86 */
 struct vars {
 	int pass;
 	int msg_line;