memtest86+: remove trailing whitespace

This makes comparison with other codebases more difficult, but helps
preserve our sanity.

Change-Id: I45f467f8e7949e8e4f7de623264bfe21b58c5536
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13826
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
diff --git a/FAQ b/FAQ
index 3c2a01c..3859386 100644
--- a/FAQ
+++ b/FAQ
@@ -133,7 +133,7 @@
   after the first pass. To be sure though simply have the test run overnight
   or even for a couple of days depending on the level of importance of the
   system.
-  
+
 - How many errors are acceptable?
 
   No errors are acceptable. Even if there is just one error, something is
@@ -155,7 +155,7 @@
   correctly configured. Look up the memory timing settings applicable to the
   brand and type of memory modules you have and check they match your BIOS
   settings, correct them if they don't and run memtest again
-  
+
   Ok, you have all the settings correctly set and you're still getting errors.
   Well of course a very likely cause are the memory modules and the logical
   course of action is to look into them further.
@@ -170,7 +170,7 @@
   errors it's a pretty good bet that the module giving the errors is simply
   defective. To exclude the possibility that a defective slot is throwing your
   results, use the same slot to test each different module.
-  
+
   If each module by itself shows no errors, but when you place two or more
   modules into the machine at the same time you do get errors, you are most
   likely stuck with a compatibility issue and unfortunately there isn't a
@@ -196,7 +196,7 @@
   persist, first check if you can rule out any compatibility issues or timing
   issues. If you are sure the memory should work in the system the cause of
   the errors must obviously lie someplace else in the system.
-  
+
   The only way to find out where, is by trial and error really. Simply start
   replacing and/or removing parts of your computer one by one, running memtest
   each time you changed anything, until the errors are resolved.
@@ -265,7 +265,7 @@
   for the FAQ.
 
   -isolinux
-    
+
     For general instructions on how to make a bootable CD with isolinux see
     the syslinux website and the manual. What you need to do to get memtest
     working is as follows.
diff --git a/Makefile b/Makefile
index a7e1f76..da6dc00 100644
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
       config.o cpuid.o linuxbios.o pci.o memsize.o spd.o error.o dmi.o controller.o \
       smp.o vmem.o random.o multiboot.o
 
-all: clean memtest.bin memtest 
+all: clean memtest.bin memtest
 
 # Link it statically once so I know I don't have undefined
 # symbols and then link it dynamically so I have full
@@ -61,10 +61,10 @@
 
 random.o: random.c
 	$(CC) -c -Wall -march=i486 -m32 -O3 -fomit-frame-pointer -fno-builtin -ffreestanding random.c
-	
-# rule for build number generation  
+
+# rule for build number generation
 build_number:
-	sh make_buildnum.sh  
+	sh make_buildnum.sh
 
 clean:
 	rm -f *.o *.s *.iso memtest.bin memtest memtest_shared \
@@ -79,6 +79,6 @@
 
 install-precomp:
 	dd <precomp.bin >$(FDISK) bs=8192
-	
+
 dos: all
 	cat mt86+_loader memtest.bin > memtest.exe
diff --git a/README b/README
index f9df887..0832e87 100644
--- a/README
+++ b/README
@@ -62,7 +62,7 @@
   To boot from a disk partition via Grub
    1) Copy the image file to a permanent location (ie. /boot/memtest.bin).
    2) Add an entry in the Grub config file (/boot/grub/menu.lst) to boot
-      memtest86.  Only the title and kernel fields need to be specified. 
+      memtest86.  Only the title and kernel fields need to be specified.
       The following is a sample Grub entry for booting memtest86:
 
 	title Memtest86
@@ -102,7 +102,7 @@
 Memtest86 has a limited number of online commands.  Online commands
 provide control over caching, test selection, address range and error
 scrolling.  A help bar is displayed at the bottom of the screen listing
-the available on-line commands. 
+the available on-line commands.
 
   Command  Description
 
@@ -114,7 +114,7 @@
 	       2) Address Range
 	       3) Error Report Mode
 	       4) CPU Selection Mode
-	       5) Refresh Screen 
+	       5) Refresh Screen
 
   SP    Set scroll lock (Stops scrolling of error messages)
 	Note: Testing is stalled when the scroll lock is
@@ -172,9 +172,9 @@
 hexadecimal.
 
   Tst:			Test number
-  Failing Address:	Failing memory address 
-  Good:			Expected data pattern 
-  Bad:			Failing data pattern 
+  Failing Address:	Failing memory address
+  Good:			Expected data pattern
+  Bad:			Failing data pattern
   Err-Bits:		Exclusive or of good and bad data (this shows the
 			position of the failing bit(s))
   Count:		Number of consecutive errors with the same address
@@ -203,7 +203,7 @@
 the motherboard.  It is impossible for the test to determine what causes
 the failure to occur.  Most failures will be due to a problem with memory.
 When it is not, the only option is to replace parts until the failure is
-corrected.  
+corrected.
 
 Once a memory error has been detected, determining the failing
 module is not a clear cut procedure.  With the large number of motherboard
@@ -232,7 +232,7 @@
 
 3) Replacing modules
 If you are unable to use either of the previous techniques then you are
-left to selective replacement of modules to find the failure.  
+left to selective replacement of modules to find the failure.
 
 4) Avoiding allocation
 The printing mode for BadRAM patterns is intended to construct boot time
@@ -271,10 +271,10 @@
 8) Execution Time
 ==================
 The time required for a complete pass of Memtest86 will vary greatly
-depending on CPU speed, memory speed and memory size. Memtest86 executes 
-indefinitely.  The pass counter increments each time that all of the 
-selected tests have been run.  Generally a single pass is sufficient to 
-catch all but the most obscure errors. However, for complete confidence 
+depending on CPU speed, memory speed and memory size. Memtest86 executes
+indefinitely.  The pass counter increments each time that all of the
+selected tests have been run.  Generally a single pass is sufficient to
+catch all but the most obscure errors. However, for complete confidence
 when intermittent errors are suspected testing for a longer period is advised.
 
 9) Memory Testing Philosophy
@@ -302,7 +302,7 @@
 of how the memory cells are laid out on the chip.  In addition there is a
 never ending number of possible chip layouts for different chip types
 and manufacturers making this strategy impractical.  However, there
-are testing algorithms that can approximate this ideal strategy. 
+are testing algorithms that can approximate this ideal strategy.
 
 
 11) Memtest86 Test Algorithms
@@ -376,7 +376,7 @@
 
 Test 2 [Address test, own address Parallel]
   Same as test 1 but the testing is done in parallel using all CPUs using
-  overlapping addresses. 
+  overlapping addresses.
 
 Test 3 [Moving inversions, ones&zeros Sequential]
   This test uses the moving inversions algorithm with patterns of all
@@ -387,7 +387,7 @@
 
 Test 4 [Moving inversions, ones&zeros Parallel]
   Same as test 3 but the testing is done in parallel using all CPUs.
- 
+
 Test 5 [Moving inversions, 8 bit pat]
   This is the same as test 4 but uses a 8 bit wide pattern of
   "walking" ones and zeros.  This test will better detect subtle errors
@@ -396,10 +396,10 @@
 Test 6 [Moving inversions, random pattern]
   Test 6 uses the same algorithm as test 4 but the data pattern is a
   random number and it's complement. This test is particularly effective
-  in finding difficult to detect data sensitive errors. 
-  The random number sequence is different with each pass 
-  so multiple passes increase effectiveness. 
-  
+  in finding difficult to detect data sensitive errors.
+  The random number sequence is different with each pass
+  so multiple passes increase effectiveness.
+
 Test 7 [Block move, 64 moves]
   This test stresses memory by using block move (movsl) instructions
   and is based on Robert Redelmeier's burnBX test.  Memory is initialized
@@ -419,7 +419,7 @@
   is shifted left for each pass. To use all possible data patterns 32 passes
   are required.  This test is quite effective at detecting data sensitive
   errors but the execution time is long.
- 
+
 Test 9 [Random number sequence]
  This test writes a series of random numbers into memory. By resetting the
  seed for the random number the same sequence of number can be created for
@@ -535,21 +535,21 @@
   CPU detection has been completely re-written to use the brand ID string
   rather than the cumbersome, difficult to maintain and often out of date
   CPUID family information. All new processors will now be correctly
-  identified without requiring code support. 
+  identified without requiring code support.
 
   All code related to controller identification, PCI and DMI has been removed.
   This may be a controversial decision and was not made lightly. The following
   are justifications for the decision:
 
     1. Controller identification has nothing to do with actual testing of
-       memory, the core purpose of Memtest86. 
+       memory, the core purpose of Memtest86.
     2. This code needed to be updated with every new chipset. With the ever
        growing number of chipsets it is not possible to keep up with the
        changes. The result is that new chipsets were more often than not
        reported in-correctly. In the authors opinion incorrect information is
        worse than no information.
     3. Probing for chipset information carries the risk of making the program
-       crash. 
+       crash.
     4. The amount of code involved with controller identification was quite
        large, making support more difficult.
 
@@ -557,7 +557,7 @@
   correctable ECC errors. The code to support ECC was hopelessly intertwined
   the controller identification code. A fresh, streamlined implementation of
   ECC reporting is planned for a future release.
-    
+
   A surprising number of conditions existed that potentially cause problems
   when testing more than 4 GB of memory. Most if not all of these conditions
   have been identified and corrected.
@@ -574,7 +574,7 @@
   multi channel memory controllers.
 
   This is a major re-write of the Memtest86 with a large number of minor
-  bug-fixes and substantial cleanup and re-organization of the code. 
+  bug-fixes and substantial cleanup and re-organization of the code.
 
 
 Enhancements in v3.5 (3/Jan/2008)
@@ -637,14 +637,14 @@
   Updated CPU detection for newer AMD, Intel and Cyrix CPUs.
 
   Reworked test sequence:
-	- Dropped ineffective non cached tests (Numbers 7-11) 
-	- Changed cache mode to "cached" for test 2 
+	- Dropped ineffective non cached tests (Numbers 7-11)
+	- Changed cache mode to "cached" for test 2
 	- Fixed bug that did not allow some tests to be skipped
 	- Added bailout for Bit fade test
 
-  Error reports are highlighted in red to provide a more vivid error 
+  Error reports are highlighted in red to provide a more vivid error
   indication.
-	    
+
   Added support for a large number of additional chipsets. (from Memtest86+
   v1.30)
 
@@ -692,7 +692,7 @@
 Enhancements in v2.9 (29/Feb/2002)
 
    The memory sizing code has been completely rewritten.  By default
-   Memtest86 gets a memory map from the BIOS that is now used to find 
+   Memtest86 gets a memory map from the BIOS that is now used to find
    available memory. A new online configuration option provides three
    choices for how memory will be sized, including the old "probe" method.
    The default mode generally will not test all of memory, but should be more
@@ -723,7 +723,7 @@
 
    Added CPU detection for Pentium 4.
 
-   
+
 Enhancements in v2.7 (12/Jul/2001)
    Expanded workaround for errors caused by BIOS USB keyboard support to
    include test #5.
@@ -788,7 +788,7 @@
 Enhancements in v2.3
    A progress meter was added to replace the spinner and dots.
 
-   Measurement and reporting of memory and cache performance  
+   Measurement and reporting of memory and cache performance
    was added.
 
    Support for creating BadRAM patterns was added.
@@ -848,7 +848,7 @@
    Re-arranged the screen layout and colors.
 
    Created local include files for I/O and serial interface definitions
-   rather than using the sometimes incompatible system include files. 
+   rather than using the sometimes incompatible system include files.
 
    Broke up the "C" source code into four separate source modules.
 
@@ -860,7 +860,7 @@
    wide memory chips are becoming more common.
 
    A new test algorithm was added to improve detection of data
-   pattern sensitive errors. 
+   pattern sensitive errors.
 
 
 Enhancements in v1.4
@@ -872,7 +872,7 @@
 
    On-line commands are now available for configuring Memtest86 on
    the fly (see On-line Commands).
-	
+
 
 Enhancements in v1.3
    Scrolling of memory errors is now provided.  Previously, only one screen
diff --git a/README.background b/README.background
index 9c35250..06f368b 100644
--- a/README.background
+++ b/README.background
@@ -2,7 +2,7 @@
                        -----------------------------------------
 
 1. Binary layout
-                                            
+
        ---------------------------------------------------------------
        | bootsect.o      | setup.o          | head.o memtest_shared  |
        ---------------------------------------------------------------
@@ -12,78 +12,78 @@
        -----------------------------------------------------------
 
 2. The following steps occur after we power on.
-   a. The bootsect.o code gets loaded at 0x7c00 
-      and copies 
+   a. The bootsect.o code gets loaded at 0x7c00
+      and copies
       i.   itself to 0x90000
       ii.  setup.o to 0x90200
-      iii. everything between _start and _end i.e memtest 
+      iii. everything between _start and _end i.e memtest
            to 0x10000
    b. jumps somewhere into the copied bootsect.o code at 0x90000
       ,does some trivial stuff and jumps to setup.o
    c. setup.o puts the processor in protected mode, with a basic
-      gdt and idt and does a long jump to the start of the 
-      memtest code (startup_32, see 4 below). The code and data 
-      segment base address are all set to 0x0. So a linear 
+      gdt and idt and does a long jump to the start of the
+      memtest code (startup_32, see 4 below). The code and data
+      segment base address are all set to 0x0. So a linear
       address range and no paging is enabled.
-   d. From now on we no longer required the bootsect.o and setup.o 
+   d. From now on we no longer required the bootsect.o and setup.o
       code.
 3. The code in memtest is compiled as position independent
-   code. Which implies that the code can be moved dynamically in 
+   code. Which implies that the code can be moved dynamically in
    the address space and can still work. Since we are now in head.o,
-   which is compiled with PIC , we no longer should use absolute 
-   addresses references while accessing functions or globals.  
+   which is compiled with PIC , we no longer should use absolute
+   addresses references while accessing functions or globals.
    All symbols are stored in a table called Global Offset Table(GOT)
-   and %ebx is set to point to the base of that table. So to get/set 
-   the value of a symbol we need to read (%ebx + symbolOffsetIntoGOT) to 
+   and %ebx is set to point to the base of that table. So to get/set
+   the value of a symbol we need to read (%ebx + symbolOffsetIntoGOT) to
    get the symbol value. For eg. if foo is global varible the assembly
    code to store %eax value into foo will be changed from
                     mov %eax, foo
-                        to 
+                        to
                     mov %eax, foo@GOTOFF(%ebx)
-4. (startup_32) The first step done in head.o is to change   
-   the gdtr and idtr register values to point to the final(!) 
-   gdt and ldt tables in head.o, since we can no longer use the 
-   gdt and ldt tables in setup.o, and call the dynamic linker 
-   stub in memtest_shared (see call _dl_start in head.S). This 
-   dynamic linker stub relocates all the code in memtest w.r.t 
-   the new base location i.e 0x1000. Finally we call the test_start() 
+4. (startup_32) The first step done in head.o is to change
+   the gdtr and idtr register values to point to the final(!)
+   gdt and ldt tables in head.o, since we can no longer use the
+   gdt and ldt tables in setup.o, and call the dynamic linker
+   stub in memtest_shared (see call _dl_start in head.S). This
+   dynamic linker stub relocates all the code in memtest w.r.t
+   the new base location i.e 0x1000. Finally we call the test_start()
    'C' routine.
-5. The test_start() C routine is the main routine which lets the BSP 
-   bring up the APs from their halt state, relocate the code 
-   (if necessary) to new address, move the APs to the newly 
+5. The test_start() C routine is the main routine which lets the BSP
+   bring up the APs from their halt state, relocate the code
+   (if necessary) to new address, move the APs to the newly
    relocated address and execute the tests. The BSP is the
    master which controls the execution of the APs, and mostly
-   it is the one which manupulates the global variables. 
+   it is the one which manupulates the global variables.
    i.  we change the stack to a private per cpu stack.
        (this step happens every time we move to a new location)
    ii. We kick start the APs in the system by
-      a. Putting a temporary real mode code 
-         (_ap_trampoline_start - _ap_trampoline_protmode) 
-         at 0x9000, which puts the AP in protected mode and jumps 
-         to _ap_trampoline_protmode in head.o. The code in 
-         _ap_trampoline_protmode calls start_32 in head.o which 
+      a. Putting a temporary real mode code
+         (_ap_trampoline_start - _ap_trampoline_protmode)
+         at 0x9000, which puts the AP in protected mode and jumps
+         to _ap_trampoline_protmode in head.o. The code in
+         _ap_trampoline_protmode calls start_32 in head.o which
          reinitialises the AP's gdt and idt to point to the
          final(!) gdt and idt. (see step 4 above)
       b. Since the APs also traverse through the same initialisation
          code(startup_32 in head.o), the APs also call test_start().
-         The APs just spin wait (see AP_SpinWaitStart) till the 
-         are instructed by the BSP to jump to a new location, 
-         which can either be a test execution or spin wait at a 
+         The APs just spin wait (see AP_SpinWaitStart) till the
+         are instructed by the BSP to jump to a new location,
+         which can either be a test execution or spin wait at a
          new location.
   iii. The base address at which memtest tries to execute as far
        as possible is 0x2000. This is the lowest possible address
-       memtest can put itself at. So the next step is to 
+       memtest can put itself at. So the next step is to
        move to 0x2000, which it cannot directly, since copying
        code to 0x2000 will override the existing code at 0x1000.
        0x2000 +sizeof(memtest) will usually be greater than 0x1000.
        so we temporarily relocated to 0x200000 and then relocate
        back to 0x2000. Every time the BSP relocates the code to the
-       new location, it pulls up the APs spin waiting at the old 
-       location to spin wait at the corresponding relocated 
+       new location, it pulls up the APs spin waiting at the old
+       location to spin wait at the corresponding relocated
        spin wait location, by making them jump to the new
        statup_32 relocated location(see 4 above).
-       Hence forth during the tests 0x200000 is the only place 
-       we relocate to if we need to test a memory window 
+       Hence forth during the tests 0x200000 is the only place
+       we relocate to if we need to test a memory window
        (see v. below to get a description of what a window is)
        which includes address range 0x2000.
 
@@ -105,45 +105,45 @@
 addr   memory that is being tested... |0x200000                 |         |RAM_END
        --------------------------------------------------------------------
 
-   iv. Once we are at 0x2000 we initialise the system, and 
-       determine the memory map ,usually via the bios e820 map. 
-       The sorted, and non-overlapping RAM page ranges are 
-       placed in v->pmap[] array. This array is the reference 
-       of the RAM memory map on the system. 
-    v. The memory range(in page numbers) which the 
+   iv. Once we are at 0x2000 we initialise the system, and
+       determine the memory map ,usually via the bios e820 map.
+       The sorted, and non-overlapping RAM page ranges are
+       placed in v->pmap[] array. This array is the reference
+       of the RAM memory map on the system.
+    v. The memory range(in page numbers) which the
        memtest86 can test is partitioned into windows.
        the current version of memtest86-smp has the capability
        to test the memory from 0x0 - 0xFFFFFFFFF (max address
-       when pae mode is enabled). 
+       when pae mode is enabled).
        We then compute the linear memory address ranges(called
-       segments) for the window we are currently about to 
+       segments) for the window we are currently about to
        test. The windows are
-          a. 0  - 640K 
+          a. 0  - 640K
           b. (0x2000 + (_end - _start))  - 4G (since the code is at 0x2000).
-          c. >4G to test pae address range, each window with size 
+          c. >4G to test pae address range, each window with size
              of 0x80000(2G), large enough to be mapped in one page directory
-             entry. So a window size of 0x80000 means we can map 1024 page 
+             entry. So a window size of 0x80000 means we can map 1024 page
              table entries, with page size of 2M(pae mode), with one
              page directory entry. Something similar to kseg entry
              in linux. The upper bound page number is 0x1000000 which
              corresponds to linear address 0xFFFFFFFFF + 1 which uses
-             all the 36 address bits. 
-       Each window is compared against the sorted & non-overlapping 
-       e820 map which we have stored in v->pmap[] array, since all 
+             all the 36 address bits.
+       Each window is compared against the sorted & non-overlapping
+       e820 map which we have stored in v->pmap[] array, since all
        memory in the selected window address range may correspond to
        RAM or can be usable. A list of segments within the window is
-       created , which contain the usable portions of the window. 
+       created , which contain the usable portions of the window.
        This is stored in v->mmap[] array.
-   vi. Once the v->mmap[] array populated, we have the list of 
+   vi. Once the v->mmap[] array populated, we have the list of
        non-overlapping segments in the current window which are the
        final address ranges that can be tested. The BSP executes the
        test first and lets each AP execute the test one by one. Once
        all the APs finish execting the same test, the BSP moves to the
-       next window follows the same procedure till all the windows 
+       next window follows the same procedure till all the windows
        are done. Once all the windows are done, the BSP moves to the
        next test. Before executing in any window the BSP checks if
        the window overlaps with the code/data of memtest86, if so
-       tries to relocate to 0x200000. If the window includes both 
+       tries to relocate to 0x200000. If the window includes both
        0x2000 as well as 0x200000  the BSP skips that window.
        Looking at the window values the only time the memtest
        relocates is when testing the 0 - 640K window.
diff --git a/README.build-process b/README.build-process
index 19edfcf..2ef9d1a 100644
--- a/README.build-process
+++ b/README.build-process
@@ -7,7 +7,7 @@
 In restructuring the build process I had several goals.  Maintainability and
 comprehsibility of the build process.  Simplicity of the toolset. And the
 ability to build images bootable by both the legacy x86 bootloader,
-and images bootable by bootloaders that directly load static ELF images. 
+and images bootable by bootloaders that directly load static ELF images.
 
 With the ability to proecess relocation records, memtest.bin has been
 reduced in size from 84480 bytes to 49308 bytes.  And now only requires one copy
@@ -28,7 +28,7 @@
 memtest is the ELF bootable target.
 
 Another major change is now data in the bss segment is also preserved
-when memtest86 is relocated, and memtest86 can be relocated to any address. 
+when memtest86 is relocated, and memtest86 can be relocated to any address.
 
 The one thing to watch out for is pointers to data inside of memtest86.  Except
 for constant pointers to static data there is not enough information to generate
diff --git a/bootsect.S b/bootsect.S
index 96aa22b..b03a6ab 100644
--- a/bootsect.S
+++ b/bootsect.S
@@ -1,383 +1,383 @@
-/*

- *	 bootsect.s		Copyright (C) 1991, 1992 Linus Torvalds

- *

- * bootsect.s is loaded at 0x7c00 by the bios-startup routines, and moves

- * itself out of the way to address 0x90000, and jumps there.

- *

- * It then loads 'setup' directly after itself (0x90200), and the system

- * at 0x10000, using BIOS interrupts.

- *

- * The loader has been made as simple as possible, and continuos

- * read errors will result in a unbreakable loop. Reboot by hand. It

- * loads pretty fast by getting whole tracks at a time whenever possible.

- *

- * 1-Jan-96 Modified by Chris Brady for use as a boot loader for MemTest-86.

- */

-

-#include "defs.h"

-

-ROOT_DEV = 0

-

-.code16

-.section ".bootsect", "ax", @progbits

-_boot:

-

-

-# ld86 requires an entry symbol. This may as well be the usual one.

-.globl	_main

-_main:

-	movw	$BOOTSEG, %ax

-	movw	%ax, %ds

-	movw	$INITSEG, %ax

-	movw	%ax, %es

-	movw	$256, %cx

-	subw	%si, %si

-	subw	%di, %di

-	cld

-	rep

-	movsw

-	ljmp	$INITSEG, $go - _boot

-

-go:

-	movw	%cs, %ax

-	movw	$(0x4000-12), %dx	# 0x4000 is arbitrary value >= length of

-					# bootsect + length of setup + room for stack

-					# 12 is disk parm size

-

-# bde - changed 0xff00 to 0x4000 to use debugger at 0x6400 up (bde).  We

-# wouldn't have to worry about this if we checked the top of memory.  Also

-# my BIOS can be configured to put the wini drive tables in high memory

-# instead of in the vector table.  The old stack might have clobbered the

-# drive table.

-

-	movw	%ax, %ds

-	movw	%ax, %es

-	movw	%ax, %ss		# put stack at INITSEG:0x4000-12.

-	movw	%dx, %sp

-

-/*

- *	Many BIOS's default disk parameter tables will not

- *	recognize multi-sector reads beyond the maximum sector number

- *	specified in the default diskette parameter tables - this may

- *	mean 7 sectors in some cases.

- *

- *	Since single sector reads are slow and out of the question,

- *	we must take care of this by creating new parameter tables

- *	(for the first disk) in RAM.  We will set the maximum sector

- *	count to 18 - the most we will encounter on an HD 1.44.

- *

- *	High doesn't hurt.  Low does.

- *

- *	Segments are as follows: ds=es=ss=cs - INITSEG,

- *		fs = 0, gs = parameter table segment

- */

-	pushw	$0

-	popw	%fs

-	movw	$0x78, %bx		# fs:bx is parameter table address

-	lgs	%fs:(%bx),%si		# gs:si is source

-

-	movw	%dx, %di		# es:di is destination

-	movw	$6, %cx			# copy 12 bytes

-	cld

-

-	rep	movsw %gs:(%si), (%di)

-

-	movw	%dx, %di

-	movb	$18, 4(%di)		# patch sector count

-

-	movw	%di, %fs:(%bx)

-	movw	%es, %fs:2(%bx)

-

-	movw	%cs, %ax

-	movw	%ax, %fs

-	movw	%ax, %gs

-

-	xorb	%ah, %ah		# reset FDC

-	xorb	%dl, %dl

-	int	$0x13

-

-# load the setup-sectors directly after the bootblock.

-# Note that 'es' is already set up.

-

-load_setup:

-	xorw	%dx, %dx			# drive 0, head 0

-	movw	$0x0002, %cx			# sector 2, track 0

-	movw	$0x0200, %bx			# address = 512, in INITSEG

-	movw	$(0x0200 + SETUPSECS), %ax	# service 2, nr of sectors

-						# (assume all on head 0, track 0)

-	int	$0x13				# read it

-	jnc	ok_load_setup			# ok - continue

-

-	pushw	%ax			# dump error code

-	call	print_nl

-	movw	%sp, %bp

-	call	print_hex

-	popw	%ax

-

-	xorb	%dl, %dl		# reset FDC

-	xorb	%ah, %ah

-	int	$0x13

-	jmp	load_setup

-

-ok_load_setup:

-

-# Get disk drive parameters, specifically nr of sectors/track

-

-

-/* It seems that there is no BIOS call to get the number of sectors.  Guess

- * 18 sectors if sector 18 can be read, 15 if sector 15 can be read.

- * Otherwise guess 9

- */

-

-	xorw	%dx, %dx			# drive 0, head 0

-	movw	$0x0012, %cx			# sector 18, track 0

-	movw	$(0x200+(SETUPSECS*0x200)), %bx	# address after setup (es = cs)

-	movw	$0x0201, %ax			# service 2, 1 sector

-	int	$0x13

-	jnc	got_sectors

-	movb	$0x0f, %cl			# sector 15

-	movw	$0x0201, %ax			# service 2, 1 sector

-	int	$0x13

-	jnc	got_sectors

-	movb	$0x09, %cl

-

-got_sectors:

-	movw	%cx, %cs:sectors - _boot

-	movw	$INITSEG, %ax

-	movw	%ax, %es

-

-# Print some inane message

-

-	movb	$0x03, %ah		# read cursor pos

-	xorb	%bh, %bh

-	int	$0x10

-

-	movw	$9, %cx

-	movw	$0x0007, %bx		# page 0, attribute 7 (normal)

-	movw	$msg1 - _boot, %bp

-	movw	$0x1301, %ax		# write string, move cursor

-	int	$0x10

-

-# ok, we've written the message, now

-# we want to load the system (at 0x10000)

-

-	movw	$TSTLOAD, %ax

-	movw	%ax, %es		# segment of 0x010000

-	call	read_it

-	call	kill_motor

-	call  turnoffcursor

-	call	print_nl

-

-# after that (everyting loaded), we jump to

-# the setup-routine loaded directly after

-# the bootblock:

-

-	ljmp	$SETUPSEG,$0

-

-# This routine loads the system at address 0x10000, making sure

-# no 64kB boundaries are crossed. We try to load it as fast as

-# possible, loading whole tracks whenever we can.

-#

-# in:	es - starting address segment (normally 0x1000)

-#

-sread:	.word 1+SETUPSECS	# sectors read of current track

-head:	.word 0			# current head

-track:	.word 0			# current track

-

-read_it:

-	movw	%es, %ax

-	testw	$0x0fff, %ax

-die:

-	jne	die		# es must be at 64kB boundary

-	xorw	%bx,%bx		# bx is starting address within segment

-rp_read:

-	movw	%es, %ax

-	subw	$TSTLOAD, %ax	# have we loaded all yet?

-	cmpw	syssize - _boot, %ax

-	jbe	ok1_read

-	ret

-ok1_read:

-	movw	%cs:sectors - _boot, %ax

-	subw	sread - _boot, %ax

-	movw	%ax, %cx

-	shlw	$9, %cx

-	addw	%bx, %cx

-	jnc	ok2_read

-	je	ok2_read

-	xorw	%ax, %ax

-	subw	%bx, %ax

-	shrw	$9, %ax

-ok2_read:

-	call	read_track

-	movw	%ax, %cx

-	add	sread - _boot, %ax

-	cmpw	%cs:sectors - _boot, %ax

-	jne	ok3_read

-	movw	$1, %ax

-	subw	head - _boot, %ax

-	jne	ok4_read

-	incw	track - _boot

-ok4_read:

-	movw	%ax, head - _boot

-	xorw	%ax, %ax

-ok3_read:

-	movw	%ax, sread - _boot

-	shlw	$9, %cx

-	addw	%cx, %bx

-	jnc	rp_read

-	movw	%es, %ax

-	addb	$0x10, %ah

-	movw	%ax, %es

-	xorw	%bx, %bx

-	jmp	rp_read

-

-read_track:

-	pusha

-	pusha

-	movw	$0xe2e, %ax 	# loading... message 2e = .

-	movw	$7, %bx

-	int	$0x10

-	popa

-

-	movw	track - _boot, %dx

-	movw	sread - _boot, %cx

-	incw	%cx

-	movb	%dl, %ch

-	movw	head - _boot, %dx

-	movb	%dl, %dh

-	andw	$0x0100, %dx

-	movb	$2, %ah

-

-	pushw	%dx				# save for error dump

-	pushw	%cx

-	pushw	%bx

-	pushw	%ax

-

-	int	$0x13

-	jc	bad_rt

-	addw	$8, %sp

-	popa

-	ret

-

-bad_rt:

-	pushw	%ax				# save error code

-	call	print_all			# ah = error, al = read

-

-	xorb	%ah, %ah

-	xorb	%dl, %dl

-	int	$0x13

-

-	addw	$10, %sp

-	popa

-	jmp read_track

-

-/*

- *	print_all is for debugging purposes.

- *	It will print out all of the registers.  The assumption is that this is

- *	called from a routine, with a stack frame like

- *	dx

- *	cx

- *	bx

- *	ax

- *	error

- *	ret <- sp

- *

-*/

-

-print_all:

-	movw	$5, %cx		# error code + 4 registers

-	movw	%sp, %bp

-

-print_loop:

-	pushw	%cx		# save count left

-	call	print_nl	# nl for readability

-

-	cmpb	5, %cl		# see if register name is needed

-	jae	no_reg

-

-	movw	$(0xe05	+ 'A' - 1), %ax

-	subb	%cl, %al

-	int	$0x10

-	movb	$'X', %al

-	int	$0x10

-	movb	$':', %al

-	int	$0x10

-

-no_reg:

-	addw	$2, %bp		# next register

-	call	print_hex	# print it

-	popw	%cx

-	loop	print_loop

-	ret

-

-print_nl:

-	movw	$0xe0d, %ax	# CR

-	int	$0x10

-	movb	$0x0a, %al	# LF

-	int	$0x10

-	ret

-

-/*

- *	print_hex is for debugging purposes, and prints the word

- *	pointed to by ss:bp in hexadecmial.

- */

-

-print_hex:

-	movw	$4, %cx		# 4 hex digits

-	movw	(%bp), %dx	# load word into dx

-

-print_digit:

-	rolw	$4, %dx		# rotate so that lowest 4 bits are used

-	movb	$0xe, %ah

-	movb	%dl, %al	# mask off so we have only next nibble

-	andb	$0xf, %al

-	addb	$'0', %al	# convert to 0-based digit

-	cmpb	$'9', %al	# check for overflow

-	jbe	good_digit

-	addb	$('A' - '0' - 10), %al

-

-good_digit:

-	int	$0x10

-	loop	print_digit

-	ret

-

-

-/*

- * This procedure turns off the floppy drive motor, so

- * that we enter the kernel in a known state, and

- * don't have to worry about it later.

- */

-kill_motor:

-	pushw	%dx

-	movw	$0x3f2, %dx

-	xorb	%al, %al

-	outb	%al, %dx

-	popw	%dx

-	ret

-

-turnoffcursor:

-  movb  $0x01, %ah      # turn off the cursor

-  movb  $0x00, %bh

-  movw  $0x2000, %cx

-  int   $0x10 

-	ret

-	

-sectors:

-	.word 0

-

-msg1:

-	.byte 13,10

-	.ascii "Loading"

-

-.org 497

-setup_sects:

-	.byte SETUPSECS

-.org 500

-syssize:

-	.word _syssize

-.org 508

-root_dev:

-	.word ROOT_DEV

-boot_flag:

-	.word 0xAA55

-_eboot:

+/*
+ *	 bootsect.s		Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * bootsect.s is loaded at 0x7c00 by the bios-startup routines, and moves
+ * itself out of the way to address 0x90000, and jumps there.
+ *
+ * It then loads 'setup' directly after itself (0x90200), and the system
+ * at 0x10000, using BIOS interrupts.
+ *
+ * The loader has been made as simple as possible, and continuos
+ * read errors will result in a unbreakable loop. Reboot by hand. It
+ * loads pretty fast by getting whole tracks at a time whenever possible.
+ *
+ * 1-Jan-96 Modified by Chris Brady for use as a boot loader for MemTest-86.
+ */
+
+#include "defs.h"
+
+ROOT_DEV = 0
+
+.code16
+.section ".bootsect", "ax", @progbits
+_boot:
+
+
+# ld86 requires an entry symbol. This may as well be the usual one.
+.globl	_main
+_main:
+	movw	$BOOTSEG, %ax
+	movw	%ax, %ds
+	movw	$INITSEG, %ax
+	movw	%ax, %es
+	movw	$256, %cx
+	subw	%si, %si
+	subw	%di, %di
+	cld
+	rep
+	movsw
+	ljmp	$INITSEG, $go - _boot
+
+go:
+	movw	%cs, %ax
+	movw	$(0x4000-12), %dx	# 0x4000 is arbitrary value >= length of
+					# bootsect + length of setup + room for stack
+					# 12 is disk parm size
+
+# bde - changed 0xff00 to 0x4000 to use debugger at 0x6400 up (bde).  We
+# wouldn't have to worry about this if we checked the top of memory.  Also
+# my BIOS can be configured to put the wini drive tables in high memory
+# instead of in the vector table.  The old stack might have clobbered the
+# drive table.
+
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss		# put stack at INITSEG:0x4000-12.
+	movw	%dx, %sp
+
+/*
+ *	Many BIOS's default disk parameter tables will not
+ *	recognize multi-sector reads beyond the maximum sector number
+ *	specified in the default diskette parameter tables - this may
+ *	mean 7 sectors in some cases.
+ *
+ *	Since single sector reads are slow and out of the question,
+ *	we must take care of this by creating new parameter tables
+ *	(for the first disk) in RAM.  We will set the maximum sector
+ *	count to 18 - the most we will encounter on an HD 1.44.
+ *
+ *	High doesn't hurt.  Low does.
+ *
+ *	Segments are as follows: ds=es=ss=cs - INITSEG,
+ *		fs = 0, gs = parameter table segment
+ */
+	pushw	$0
+	popw	%fs
+	movw	$0x78, %bx		# fs:bx is parameter table address
+	lgs	%fs:(%bx),%si		# gs:si is source
+
+	movw	%dx, %di		# es:di is destination
+	movw	$6, %cx			# copy 12 bytes
+	cld
+
+	rep	movsw %gs:(%si), (%di)
+
+	movw	%dx, %di
+	movb	$18, 4(%di)		# patch sector count
+
+	movw	%di, %fs:(%bx)
+	movw	%es, %fs:2(%bx)
+
+	movw	%cs, %ax
+	movw	%ax, %fs
+	movw	%ax, %gs
+
+	xorb	%ah, %ah		# reset FDC
+	xorb	%dl, %dl
+	int	$0x13
+
+# load the setup-sectors directly after the bootblock.
+# Note that 'es' is already set up.
+
+load_setup:
+	xorw	%dx, %dx			# drive 0, head 0
+	movw	$0x0002, %cx			# sector 2, track 0
+	movw	$0x0200, %bx			# address = 512, in INITSEG
+	movw	$(0x0200 + SETUPSECS), %ax	# service 2, nr of sectors
+						# (assume all on head 0, track 0)
+	int	$0x13				# read it
+	jnc	ok_load_setup			# ok - continue
+
+	pushw	%ax			# dump error code
+	call	print_nl
+	movw	%sp, %bp
+	call	print_hex
+	popw	%ax
+
+	xorb	%dl, %dl		# reset FDC
+	xorb	%ah, %ah
+	int	$0x13
+	jmp	load_setup
+
+ok_load_setup:
+
+# Get disk drive parameters, specifically nr of sectors/track
+
+
+/* It seems that there is no BIOS call to get the number of sectors.  Guess
+ * 18 sectors if sector 18 can be read, 15 if sector 15 can be read.
+ * Otherwise guess 9
+ */
+
+	xorw	%dx, %dx			# drive 0, head 0
+	movw	$0x0012, %cx			# sector 18, track 0
+	movw	$(0x200+(SETUPSECS*0x200)), %bx	# address after setup (es = cs)
+	movw	$0x0201, %ax			# service 2, 1 sector
+	int	$0x13
+	jnc	got_sectors
+	movb	$0x0f, %cl			# sector 15
+	movw	$0x0201, %ax			# service 2, 1 sector
+	int	$0x13
+	jnc	got_sectors
+	movb	$0x09, %cl
+
+got_sectors:
+	movw	%cx, %cs:sectors - _boot
+	movw	$INITSEG, %ax
+	movw	%ax, %es
+
+# Print some inane message
+
+	movb	$0x03, %ah		# read cursor pos
+	xorb	%bh, %bh
+	int	$0x10
+
+	movw	$9, %cx
+	movw	$0x0007, %bx		# page 0, attribute 7 (normal)
+	movw	$msg1 - _boot, %bp
+	movw	$0x1301, %ax		# write string, move cursor
+	int	$0x10
+
+# ok, we've written the message, now
+# we want to load the system (at 0x10000)
+
+	movw	$TSTLOAD, %ax
+	movw	%ax, %es		# segment of 0x010000
+	call	read_it
+	call	kill_motor
+	call  turnoffcursor
+	call	print_nl
+
+# after that (everyting loaded), we jump to
+# the setup-routine loaded directly after
+# the bootblock:
+
+	ljmp	$SETUPSEG,$0
+
+# This routine loads the system at address 0x10000, making sure
+# no 64kB boundaries are crossed. We try to load it as fast as
+# possible, loading whole tracks whenever we can.
+#
+# in:	es - starting address segment (normally 0x1000)
+#
+sread:	.word 1+SETUPSECS	# sectors read of current track
+head:	.word 0			# current head
+track:	.word 0			# current track
+
+read_it:
+	movw	%es, %ax
+	testw	$0x0fff, %ax
+die:
+	jne	die		# es must be at 64kB boundary
+	xorw	%bx,%bx		# bx is starting address within segment
+rp_read:
+	movw	%es, %ax
+	subw	$TSTLOAD, %ax	# have we loaded all yet?
+	cmpw	syssize - _boot, %ax
+	jbe	ok1_read
+	ret
+ok1_read:
+	movw	%cs:sectors - _boot, %ax
+	subw	sread - _boot, %ax
+	movw	%ax, %cx
+	shlw	$9, %cx
+	addw	%bx, %cx
+	jnc	ok2_read
+	je	ok2_read
+	xorw	%ax, %ax
+	subw	%bx, %ax
+	shrw	$9, %ax
+ok2_read:
+	call	read_track
+	movw	%ax, %cx
+	add	sread - _boot, %ax
+	cmpw	%cs:sectors - _boot, %ax
+	jne	ok3_read
+	movw	$1, %ax
+	subw	head - _boot, %ax
+	jne	ok4_read
+	incw	track - _boot
+ok4_read:
+	movw	%ax, head - _boot
+	xorw	%ax, %ax
+ok3_read:
+	movw	%ax, sread - _boot
+	shlw	$9, %cx
+	addw	%cx, %bx
+	jnc	rp_read
+	movw	%es, %ax
+	addb	$0x10, %ah
+	movw	%ax, %es
+	xorw	%bx, %bx
+	jmp	rp_read
+
+read_track:
+	pusha
+	pusha
+	movw	$0xe2e, %ax 	# loading... message 2e = .
+	movw	$7, %bx
+	int	$0x10
+	popa
+
+	movw	track - _boot, %dx
+	movw	sread - _boot, %cx
+	incw	%cx
+	movb	%dl, %ch
+	movw	head - _boot, %dx
+	movb	%dl, %dh
+	andw	$0x0100, %dx
+	movb	$2, %ah
+
+	pushw	%dx				# save for error dump
+	pushw	%cx
+	pushw	%bx
+	pushw	%ax
+
+	int	$0x13
+	jc	bad_rt
+	addw	$8, %sp
+	popa
+	ret
+
+bad_rt:
+	pushw	%ax				# save error code
+	call	print_all			# ah = error, al = read
+
+	xorb	%ah, %ah
+	xorb	%dl, %dl
+	int	$0x13
+
+	addw	$10, %sp
+	popa
+	jmp read_track
+
+/*
+ *	print_all is for debugging purposes.
+ *	It will print out all of the registers.  The assumption is that this is
+ *	called from a routine, with a stack frame like
+ *	dx
+ *	cx
+ *	bx
+ *	ax
+ *	error
+ *	ret <- sp
+ *
+*/
+
+print_all:
+	movw	$5, %cx		# error code + 4 registers
+	movw	%sp, %bp
+
+print_loop:
+	pushw	%cx		# save count left
+	call	print_nl	# nl for readability
+
+	cmpb	5, %cl		# see if register name is needed
+	jae	no_reg
+
+	movw	$(0xe05	+ 'A' - 1), %ax
+	subb	%cl, %al
+	int	$0x10
+	movb	$'X', %al
+	int	$0x10
+	movb	$':', %al
+	int	$0x10
+
+no_reg:
+	addw	$2, %bp		# next register
+	call	print_hex	# print it
+	popw	%cx
+	loop	print_loop
+	ret
+
+print_nl:
+	movw	$0xe0d, %ax	# CR
+	int	$0x10
+	movb	$0x0a, %al	# LF
+	int	$0x10
+	ret
+
+/*
+ *	print_hex is for debugging purposes, and prints the word
+ *	pointed to by ss:bp in hexadecmial.
+ */
+
+print_hex:
+	movw	$4, %cx		# 4 hex digits
+	movw	(%bp), %dx	# load word into dx
+
+print_digit:
+	rolw	$4, %dx		# rotate so that lowest 4 bits are used
+	movb	$0xe, %ah
+	movb	%dl, %al	# mask off so we have only next nibble
+	andb	$0xf, %al
+	addb	$'0', %al	# convert to 0-based digit
+	cmpb	$'9', %al	# check for overflow
+	jbe	good_digit
+	addb	$('A' - '0' - 10), %al
+
+good_digit:
+	int	$0x10
+	loop	print_digit
+	ret
+
+
+/*
+ * This procedure turns off the floppy drive motor, so
+ * that we enter the kernel in a known state, and
+ * don't have to worry about it later.
+ */
+kill_motor:
+	pushw	%dx
+	movw	$0x3f2, %dx
+	xorb	%al, %al
+	outb	%al, %dx
+	popw	%dx
+	ret
+
+turnoffcursor:
+  movb  $0x01, %ah      # turn off the cursor
+  movb  $0x00, %bh
+  movw  $0x2000, %cx
+  int   $0x10
+	ret
+
+sectors:
+	.word 0
+
+msg1:
+	.byte 13,10
+	.ascii "Loading"
+
+.org 497
+setup_sects:
+	.byte SETUPSECS
+.org 500
+syssize:
+	.word _syssize
+.org 508
+root_dev:
+	.word ROOT_DEV
+boot_flag:
+	.word 0xAA55
+_eboot:
diff --git a/changelog b/changelog
index 9379a5b..b99e5a3 100644
--- a/changelog
+++ b/changelog
@@ -1,25 +1,25 @@
-Memtest86+ V5.01 changelog

-----------------------------

-

-	- Added support for up to 2 TB of RAM on X64 CPUs

-	- Added experimental SMT support up to 32 cores

-	- Added complete detection for memory controllers.

-	- Added Motherboard Manufacturer & Model reporting

-	- Added CPU temperature reporting

-	- Added enhanced Fail Safe Mode (Press F1 at startup)

-	- Added support for Intel "Sandy Bridge-E" CPUs

-	- Added support for Intel "Ivy Bridge" CPUs

-	- Added preliminary support for Intel "Haswell" CPUs

-	- Added preliminary support for Intel "Haswell-ULT" CPUs

-	- Added support for AMD "Kabini" (K16) CPUs

-	- Added support for AMD "Bulldozer" CPUs

-	- Added support for AMD "Trinity" CPUs

-	- Added support for AMD E-/C-/G-/Z- "Bobcat" CPUs

-	- Added support for Intel Atom "Pineview" CPUs

-	- Added support for Intel Atom "Cedar Trail" CPUs

-	- Added SPD detection on most AMD Chipsets

-	- Enforced Coreboot support

-	- Optimized run time for faster memory error detection

-	- Rewriten lots of memory timings detection code

-	- Corrected bugs, bugs and more bugs

-	

+Memtest86+ V5.01 changelog
+----------------------------
+
+	- Added support for up to 2 TB of RAM on X64 CPUs
+	- Added experimental SMT support up to 32 cores
+	- Added complete detection for memory controllers.
+	- Added Motherboard Manufacturer & Model reporting
+	- Added CPU temperature reporting
+	- Added enhanced Fail Safe Mode (Press F1 at startup)
+	- Added support for Intel "Sandy Bridge-E" CPUs
+	- Added support for Intel "Ivy Bridge" CPUs
+	- Added preliminary support for Intel "Haswell" CPUs
+	- Added preliminary support for Intel "Haswell-ULT" CPUs
+	- Added support for AMD "Kabini" (K16) CPUs
+	- Added support for AMD "Bulldozer" CPUs
+	- Added support for AMD "Trinity" CPUs
+	- Added support for AMD E-/C-/G-/Z- "Bobcat" CPUs
+	- Added support for Intel Atom "Pineview" CPUs
+	- Added support for Intel Atom "Cedar Trail" CPUs
+	- Added SPD detection on most AMD Chipsets
+	- Enforced Coreboot support
+	- Optimized run time for faster memory error detection
+	- Rewriten lots of memory timings detection code
+	- Corrected bugs, bugs and more bugs
+
diff --git a/config.c b/config.c
index 18d8887..9c05324 100644
--- a/config.c
+++ b/config.c
@@ -92,7 +92,7 @@
 					cprint(POP_Y+4, POP_X+5,
 						"Test Number [1-11]: ");
 					n = getval(POP_Y+4, POP_X+24, 0) - 1;
-					if (n <= 11) 
+					if (n <= 11)
 						{
 					    /* Deselect all tests */
 					    i = 0;
@@ -292,7 +292,7 @@
 					/* Set Beep On Error mode */
 					beepmode = !beepmode;
 					sflag++;
-					break;						
+					break;
 				case 11:
 				case 57:
 					/* 0/CR - Continue */
@@ -356,10 +356,10 @@
 			/* Display DMI Memory Info */
 			pop2up();
       print_dmi_info();
-			pop2down();			
+			pop2down();
 			break;
 		case 8:
-			/* Display SPD Data */			
+			/* Display SPD Data */
 			popdown();
 			show_spd();
 			popup();
@@ -386,13 +386,13 @@
 {
 	int i, j;
 	char *pp;
-	
-	for (i=POP_Y; i<POP_Y + POP_H; i++) { 
-		for (j=POP_X; j<POP_X + POP_W; j++) { 
+
+	for (i=POP_Y; i<POP_Y + POP_H; i++) {
+		for (j=POP_X; j<POP_X + POP_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
                         save[0][i-POP_Y][j-POP_X] = *pp;  /* Save screen */
                         set_scrn_buf(i, j, ' ');
-			*pp = ' ';		/* Clear */                        
+			*pp = ' ';		/* Clear */
 			pp++;
                         save[1][i-POP_Y][j-POP_X] = *pp;
 			*pp = 0x07;		/* Change Background to black */
@@ -405,9 +405,9 @@
 {
 	int i, j;
 	char *pp;
-	
-	for (i=POP_Y; i<POP_Y + POP_H; i++) { 
-		for (j=POP_X; j<POP_X + POP_W; j++) { 
+
+	for (i=POP_Y; i<POP_Y + POP_H; i++) {
+		for (j=POP_X; j<POP_X + POP_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
 			*pp = save[0][i-POP_Y][j-POP_X]; /* Restore screen */
                         set_scrn_buf(i, j, save[0][i-POP_Y][j-POP_X]);
@@ -422,9 +422,9 @@
 {
 	int i, j;
 	char *pp;
-	
-	for (i=POP_Y; i<POP_Y + POP_H; i++) { 
-		for (j=POP_X; j<POP_X + POP_W; j++) { 
+
+	for (i=POP_Y; i<POP_Y + POP_H; i++) {
+		for (j=POP_X; j<POP_X + POP_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
 			*pp = ' ';		/* Clear popup */
                         set_scrn_buf(i, j, ' ');
@@ -439,8 +439,8 @@
 	int i, j;
 	char *pp;
 
-	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) { 
-		for (j=POP2_X; j<POP2_X + POP2_W; j++) { 
+	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) {
+		for (j=POP2_X; j<POP2_X + POP2_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
 			save2[0][i-POP2_Y][j-POP2_X] = *pp;  /* Save screen */
 			set_scrn_buf(i, j, ' ');
@@ -458,8 +458,8 @@
 	int i, j;
 	char *pp;
 
-	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) { 
-		for (j=POP2_X; j<POP2_X + POP2_W; j++) { 
+	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) {
+		for (j=POP2_X; j<POP2_X + POP2_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
 			*pp = save2[0][i-POP2_Y][j-POP2_X]; /* Restore screen */
 			set_scrn_buf(i, j, save2[0][i-POP2_Y][j-POP2_X]);
@@ -475,8 +475,8 @@
 	int i, j;
 	char *pp;
 
-	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) { 
-		for (j=POP2_X; j<POP2_X + POP2_W; j++) { 
+	for (i=POP2_Y; i<POP2_Y + POP2_H; i++) {
+		for (j=POP2_X; j<POP2_X + POP2_W; j++) {
 			pp = (char *)(SCREEN_ADR + (i * 160) + (j * 2));
 			*pp = ' ';		/* Clear popup */
 			set_scrn_buf(i, j, ' ');
@@ -505,14 +505,14 @@
 			if (v->pmap[i].end < v->plim_lower) {
 				continue;
 			}
-			
+
 			/* Ends past upper limit? */
 			if (v->pmap[i].end > v->plim_upper) {
-				v->selected_pages += 
+				v->selected_pages +=
 					v->plim_upper - v->plim_lower;
 			} else {
 				/* Straddles lower limit */
-				v->selected_pages += 
+				v->selected_pages +=
 					(v->pmap[i].end - v->plim_lower);
 			}
 			continue;
@@ -524,7 +524,7 @@
 				continue;
 			}
 			/* Straddles upper limit */
-			v->selected_pages += 
+			v->selected_pages +=
 				(v->plim_upper - v->pmap[i].start);
 		}
 	}
diff --git a/config.h b/config.h
index aa4c9fb..f11b634 100644
--- a/config.h
+++ b/config.h
@@ -31,14 +31,14 @@
 /*	to enable. */
 #define SERIAL_CONSOLE_DEFAULT 0
 
-/* SERIAL_TTY - The default serial port to use. 0=ttyS0, 1=ttyS1 */ 
+/* SERIAL_TTY - The default serial port to use. 0=ttyS0, 1=ttyS1 */
 #define SERIAL_TTY 0
 
 /* SERIAL_BAUD_RATE - Baud rate for the serial console */
 #define SERIAL_BAUD_RATE 9600
 
 /* SCRN_DEBUG - extra check for SCREEN_BUFFER
- */ 
+ */
 /* #define SCRN_DEBUG */
 
 /* APM - Turns off APM at boot time to avoid blanking the screen */
diff --git a/controller.c b/controller.c
index 183e9c3..a1398f7 100644
--- a/controller.c
+++ b/controller.c
@@ -1,4 +1,4 @@
-/* 
+/*
  * MemTest86+ V5 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
  * http://www.canardpc.com - http://www.memtest.org
@@ -20,7 +20,7 @@
 
 int col, col2;
 int nhm_bus = 0x3F;
-	
+
 extern ulong extclock;
 extern unsigned long imc_type;
 extern struct cpu_ident cpu_id;
@@ -75,18 +75,18 @@
 };
 
 
-void coretemp(void) 
+void coretemp(void)
 {
 	unsigned int msrl, msrh;
 	unsigned int tjunc, tabs, tnow;
 	unsigned long rtcr;
 	double amd_raw_temp;
-	
+
 	// Only enable coretemp if IMC is known
 	if(imc_type == 0) { return; }
-	
+
 	tnow = 0;
-	
+
 	// Intel  CPU
 	if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.max_cpuid >= 6)
 	{
@@ -96,52 +96,52 @@
 			rdmsr(MSR_IA32_TEMPERATURE_TARGET, msrl, msrh);
 			tjunc = ((msrl >> 16) & 0x7F);
 			if(tjunc < 50 || tjunc > 125) { tjunc = 90; } // assume Tjunc = 90°C if boggus value received.
-			tnow = tjunc - tabs;		
-			dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);	
+			tnow = tjunc - tabs;
+			dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
 			v->check_temp = tnow;
 		}
 		return;
 	}
-	
+
 	// AMD CPU
 	if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.extendedFamily > 0)
 	{
 		pci_conf_read(0, 24, 3, 0xA4, 4, &rtcr);
 		amd_raw_temp = ((rtcr >> 21) & 0x7FF);
 		v->check_temp = (int)(amd_raw_temp / 8);
-		dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);	
-	}	
-	
-				
+		dprint(LINE_CPU+1, 30, v->check_temp, 3, 0);
+	}
+
+
 }
 
 void print_cpu_line(float dram_freq, float fsb_freq, int ram_type)
 {
 	int cur_col = COL_SPEC;
-	
+
 	cprint(LINE_CPU, cur_col, "RAM:                                ");
 	cur_col += 5;
 	dprint(LINE_CPU, cur_col, dram_freq, 4, 1);
 	cur_col += 4;
 	cprint(LINE_CPU, cur_col, "MHz (");
 	cur_col += 5;
-	
+
 	switch(ram_type)
 	{
 		default:
 		case 1:
 			cprint(LINE_CPU, cur_col, "DDR-");
 			cur_col += 4;
-			break;		
+			break;
 		case 2:
 			cprint(LINE_CPU, cur_col, "DDR2-");
 			cur_col += 5;
-			break;	
+			break;
 		case 3:
 			cprint(LINE_CPU, cur_col, "DDR3-");
 			cur_col += 5;
-			break;	
-	}		
+			break;
+	}
 
 	if(dram_freq < 500)
 	{
@@ -149,19 +149,19 @@
 		cur_col += 3;
 	} else {
 		dprint(LINE_CPU, cur_col, dram_freq*2, 4, 0);
-		cur_col += 4;		
+		cur_col += 4;
 	}
 	cprint(LINE_CPU, cur_col, ")");
-	cur_col++;	
-	
+	cur_col++;
+
 	if(fsb_freq > 10)
 	{
 		cprint(LINE_CPU, cur_col, " - BCLK: ");
 		cur_col += 9;
-	
-		dprint(LINE_CPU, cur_col, fsb_freq, 3, 0);	
+
+		dprint(LINE_CPU, cur_col, fsb_freq, 3, 0);
 	}
-	
+
 }
 
 void print_ram_line(float cas, int rcd, int rp, int ras, int chan)
@@ -169,7 +169,7 @@
 	int cur_col = COL_SPEC;
 
 	cprint(LINE_RAM, cur_col, "Timings: CAS                        ");
-	cur_col += 13;	
+	cur_col += 13;
 
 	// CAS Latency (tCAS)
 	if (cas == 1.5) {
@@ -179,7 +179,7 @@
 	} else if (cas < 10) {
 		dprint(LINE_RAM, cur_col, cas, 1, 0); cur_col += 1;
 	} else {
-		dprint(LINE_RAM, cur_col, cas, 2, 0); cur_col += 2;		
+		dprint(LINE_RAM, cur_col, cas, 2, 0); cur_col += 2;
 	}
 	cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
 
@@ -189,7 +189,7 @@
 		cur_col += 1;
 	} else {
 		dprint(LINE_RAM, cur_col, rcd, 2, 0);
-		cur_col += 2;		
+		cur_col += 2;
 	}
 	cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
 
@@ -199,7 +199,7 @@
 		cur_col += 1;
 	} else {
 		dprint(LINE_RAM, cur_col, rp, 2, 0);
-		cur_col += 2;		
+		cur_col += 2;
 	}
 	cprint(LINE_RAM, cur_col, "-"); cur_col += 1;
 
@@ -211,24 +211,24 @@
 		dprint(LINE_RAM, cur_col, ras, 2, 0);
 		cur_col += 2;
 	}
-	
-		
+
+
 	switch(chan)
 	{
 		case 0:
 			break;
 		case 1:
 			cprint(LINE_RAM, cur_col, " @ 64-bit Mode");
-			break;			
-		case 2: 
+			break;
+		case 2:
 			cprint(LINE_RAM, cur_col, " @ 128-bit Mode");
-			break;			
+			break;
 		case 3:
 			cprint(LINE_RAM, cur_col, " @ 192-bit Mode");
-			break;	
+			break;
 		case 4:
 			cprint(LINE_RAM, cur_col, " @ 256-bit Mode");
-			break;	
+			break;
 	}
 }
 
@@ -236,10 +236,10 @@
 {
 
 	char *name;
-	
+
 	/* Print the controller name */
 	name = controllers[ctrl.index].name;
-	cprint(LINE_CPU, COL_SPEC, "Chipset:               ");	
+	cprint(LINE_CPU, COL_SPEC, "Chipset:               ");
 	cprint(LINE_CPU, COL_SPEC+9, name);
 	return;
 }
@@ -247,7 +247,7 @@
 static void poll_timings_nothing(void)
 {
 	char *ram_type;
-	
+
 	/* Print the controller name */
 	ram_type = controllers[ctrl.index].ram_type;
 	cprint(LINE_RAM, COL_SPEC, "RAM Type:              ");
@@ -272,7 +272,7 @@
 static void setup_wmr(void)
 {
 	ulong dev0;
-		
+
 	// Activate MMR I/O
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	if (!(dev0 & 0x1)) {
@@ -287,7 +287,7 @@
 	static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
 	unsigned long did, vid, mc_control, mc_ssrcontrol;
 	int i;
-	
+
 	//Nehalem supports Scrubbing */
 	ctrl.cap = ECC_SCRUB;
 	ctrl.mode = ECC_NONE;
@@ -299,23 +299,23 @@
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
 		vid &= 0xFFFF;
 		did &= 0xFF00;
-		if(vid == 0x8086 && did >= 0x2C00) { 
-			nhm_bus = possible_nhm_bus[i]; 
+		if(vid == 0x8086 && did >= 0x2C00) {
+			nhm_bus = possible_nhm_bus[i];
 			}
 }
 
 	/* Now, we have the last IMC bus number in nhm_bus */
 	/* Check for ECC & Scrub */
-	
-	pci_conf_read(nhm_bus, 3, 0, 0x4C, 2, &mc_control);	
-	if((mc_control >> 4) & 1) { 
-		ctrl.mode = ECC_CORRECT; 
-		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);	
-		if(mc_ssrcontrol & 3) { 
-			ctrl.mode = ECC_SCRUB; 
-		}		
+
+	pci_conf_read(nhm_bus, 3, 0, 0x4C, 2, &mc_control);
+	if((mc_control >> 4) & 1) {
+		ctrl.mode = ECC_CORRECT;
+		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
+		if(mc_ssrcontrol & 3) {
+			ctrl.mode = ECC_SCRUB;
+		}
 	}
-	
+
 }
 
 static void setup_nhm32(void)
@@ -323,7 +323,7 @@
 	static float possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
 	unsigned long did, vid, mc_control, mc_ssrcontrol;
 	int i;
-	
+
 	//Nehalem supports Scrubbing */
 	ctrl.cap = ECC_SCRUB;
 	ctrl.mode = ECC_NONE;
@@ -334,22 +334,22 @@
 		pci_conf_read( possible_nhm_bus[i], 3, 4, 0x02, 2, &did);
 		vid &= 0xFFFF;
 		did &= 0xFF00;
-		if(vid == 0x8086 && did >= 0x2C00) { 
-			nhm_bus = possible_nhm_bus[i]; 
+		if(vid == 0x8086 && did >= 0x2C00) {
+			nhm_bus = possible_nhm_bus[i];
 			}
 	}
 
 	/* Now, we have the last IMC bus number in nhm_bus */
 	/* Check for ECC & Scrub */
-	pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);	
-	if((mc_control >> 1) & 1) { 
-		ctrl.mode = ECC_CORRECT; 
-		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);	
-		if(mc_ssrcontrol & 1) { 
-			ctrl.mode = ECC_SCRUB; 
-		}		
+	pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
+	if((mc_control >> 1) & 1) {
+		ctrl.mode = ECC_CORRECT;
+		pci_conf_read(nhm_bus, 3, 2, 0x48, 2, &mc_ssrcontrol);
+		if(mc_ssrcontrol & 1) {
+			ctrl.mode = ECC_SCRUB;
+		}
 	}
-	
+
 }
 
 static void setup_amd64(void)
@@ -366,10 +366,10 @@
 
 	/* Check First if ECC DRAM Modules are used */
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
-	
+
 	if (cpu_id.vers.bits.extendedModel >= 4) {
 		/* NEW K8 0Fh Family 90 nm */
-		
+
 		if ((dramcl >> 19)&1){
 			/* Fill in the correct memory capabilites */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
@@ -380,14 +380,14 @@
 		/* Enable NB ECC Logging by MSR Write */
 		rdmsr(0x017B, mcgsrl, mcgsth);
 		wrmsr(0x017B, 0x10, mcgsth);
-	
+
 		/* Clear any previous error */
 		pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
-		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );		
+		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
 
-	} else { 
+	} else {
 		/* OLD K8 130 nm */
-		
+
 		if ((dramcl >> 17)&1){
 			/* Fill in the correct memory capabilites */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
@@ -398,7 +398,7 @@
 		/* Enable NB ECC Logging by MSR Write */
 		rdmsr(0x017B, mcgsrl, mcgsth);
 		wrmsr(0x017B, 0x10, mcgsth);
-	
+
 		/* Clear any previous error */
 		pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
 		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7F801EFC );
@@ -420,7 +420,7 @@
 
 	// Check First if ECC DRAM Modules are used */
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramcl);
-	
+
 		if ((dramcl >> 19)&1){
 			// Fill in the correct memory capabilites */
 			pci_conf_read(0, 24, 3, 0x44, 4, &nbxcfg);
@@ -431,11 +431,11 @@
 		// Enable NB ECC Logging by MSR Write */
 		rdmsr(0x017B, mcgsrl, mcgsth);
 		wrmsr(0x017B, 0x10, mcgsth);
-	
+
 		// Clear any previous error */
 		pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
-		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );	
-		
+		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
+
 		/* Enable ECS */
 		rdmsr(0xC001001F, msr_low,  msr_high);
 		wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
@@ -447,7 +447,7 @@
 {
 
 	ulong msr_low, msr_high;
-	
+
 	/* Enable ECS */
 	rdmsr(0xC001001F, msr_low,  msr_high);
 	wrmsr(0xC001001F, msr_low, (msr_high | 0x4000));
@@ -467,37 +467,37 @@
 	pci_conf_read(0, 24, 3, 0x4C, 4, &mcanb);
 
 	if (((mcanb >> 31)&1) && ((mcanb >> 14)&1)) {
-		// Find out about the first correctable error 
-		// Syndrome code -> bits use a complex matrix. Will add this later 
-		// Read the error location 
+		// Find out about the first correctable error
+		// Syndrome code -> bits use a complex matrix. Will add this later
+		// Read the error location
 		pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add);
 
-		// Read the syndrome 
+		// Read the syndrome
 		celog_syndrome = (mcanb >> 15)&0xFF;
 
-		// Parse the error location 
+		// Parse the error location
 		page = (mcanb_add >> 12);
 		offset = (mcanb_add >> 3) & 0xFFF;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, offset, 1, celog_syndrome, 0);
 
-		// Clear the error registers 
+		// Clear the error registers
 		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFFF );
 	}
 	if (((mcanb >> 31)&1) && ((mcanb >> 13)&1)) {
-		// Found out about the first uncorrectable error 
-		// Read the error location 
+		// Found out about the first uncorrectable error
+		// Read the error location
 		pci_conf_read(0, 24, 3, 0x50, 4, &mcanb_add);
 
-		// Parse the error location 
+		// Parse the error location
 		page = (mcanb_add >> 12);
 		offset = (mcanb_add >> 3) & 0xFFF;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, offset, 0, 0, 0);
 
-		// Clear the error registers 
+		// Clear the error registers
 		pci_conf_write(0, 24, 3, 0x4C, 4, mcanb & 0x7FFFFFF );
 
 	}
@@ -525,29 +525,29 @@
 	int bits;
 	int i;
 
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, &ecc_status);
 	if (ecc_status & (3 << 8)) {
 		for(i = 0; i < 6; i++) {
 			if (!(ecc_status & (1 << i))) {
 				continue;
 			}
-			// Find the bank the error occured on 
+			// Find the bank the error occured on
 			bank_addr = 0x40 + (i << 1);
 
-			// Now get the information on the erroring bank 
+			// Now get the information on the erroring bank
 			pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 2, &bank_info);
 
-			// Parse the error location and error type 
+			// Parse the error location and error type
 			page = (bank_info & 0xFF80) << 4;
 			bits = (((ecc_status >> 8) &3) == 2)?1:2;
 
-			// Report the error 
+			// Report the error
 			print_ecc_err(page, 0, bits==1?1:0, 0, 0);
 
 		}
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 2, 0);
 	}
 }
@@ -587,35 +587,35 @@
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, &ecc_mode_status);
 	// Multibit error
 	if (ecc_mode_status & (1 << 9)) {
-		// Find the bank the error occured on 
+		// Find the bank the error occured on
 		bank_addr = 0xC0 + (((ecc_mode_status >> 4) & 0xf) << 2);
 
-		// Now get the information on the erroring bank 
+		// Now get the information on the erroring bank
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (bank_info & 0xFF800000) >> 12;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, 1, 0, 0);
 
 	}
-	// Singlebit error 
+	// Singlebit error
 	if (ecc_mode_status & (1 << 8)) {
-		// Find the bank the error occured on 
+		// Find the bank the error occured on
 		bank_addr = 0xC0 + (((ecc_mode_status >> 0) & 0xf) << 2);
 
-		// Now get the information on the erroring bank 
+		// Now get the information on the erroring bank
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, bank_addr, 4, &bank_info);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (bank_info & 0xFF800000) >> 12;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, 0, 0, 0);
 
 	}
-	// Clear the error status 
+	// Clear the error status
 	if (ecc_mode_status & (3 << 8)) {
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x48, 4, ecc_mode_status);
 	}
@@ -697,7 +697,7 @@
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x88, 1, 0x0);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8A, 1, 0x0);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x8C, 1, 0x0);
-	
+
 
 	}
 
@@ -753,45 +753,45 @@
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, &nerr);
 
 	if (ferr & 1) {
-		// Find out about the first correctable error 
+		// Find out about the first correctable error
 		unsigned long celog_add;
 		unsigned long celog_syndrome;
 		unsigned long page;
 
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA0, 4, &celog_add);
-		// Read the syndrome 
+		// Read the syndrome
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xD0, 2, &celog_syndrome);
 
-		// Parse the error location 
+		// Parse the error location
 		page = (celog_add & 0x0FFFFFC0) >> 6;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, 1, celog_syndrome, 0);
 
-		// Clear Bit 
+		// Clear Bit
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3);
 	}
 
 	if (ferr & 2) {
-		// Found out about the first uncorrectable error 
+		// Found out about the first uncorrectable error
 		unsigned long uccelog_add;
 		unsigned long page;
 
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xB0, 4, &uccelog_add);
 
-		// Parse the error location 
+		// Parse the error location
 		page = (uccelog_add & 0x0FFFFFC0) >> 6;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, 0, 0, 0);
 
-		// Clear Bit 
+		// Clear Bit
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 1, ferr & 3);
 	}
 
-	// Check if DRAM_NERR contains data 
+	// Check if DRAM_NERR contains data
 	if (nerr & 3) {
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 1, nerr & 3);
 	}
@@ -816,14 +816,14 @@
 	unsigned long errsts;
 	unsigned long page;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, &errsts);
 	if (errsts & 0x11) {
 		unsigned long eap;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, &eap);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFF000) >> 12;
 		bits = 0;
 		if (eap &3) {
@@ -831,11 +831,11 @@
 		}
 
 		if (bits) {
-			// Report the error 
+			// Report the error
 			print_ecc_err(page, 0, bits==1?1:0, 0, 0);
 		}
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x91, 2, 0x11);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0x80, 4, 3);
 	}
@@ -863,25 +863,25 @@
 	unsigned long syndrome;
 	int channel;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 3) {
 		unsigned long eap;
 		unsigned long derrctl_sts;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFF800) >> 11;
 		channel = eap & 1;
 		syndrome = derrctl_sts & 0xFF;
 		bits = ((errsts & 3) == 1)?1:2;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, bits==1?1:0, syndrome, channel);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, 3 << 10);
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
 	}
@@ -926,11 +926,11 @@
 	ulong dev0, drc;
 	unsigned long tolm;
 	long *ptr;
-	
+
 	pci_conf_read( 0, 0, 0, 0x54, 4, &dev0);
 	dev0 = dev0 | 0x10000000;
 	pci_conf_write( 0, 0, 0, 0x54, 4, dev0);
-	
+
 	// CDH start
 	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
 	if (!(dev0 & 0xFFFFC000)) {
@@ -945,12 +945,12 @@
 	dev0 &= 0xFFFFC000;
 	ptr=(long*)(dev0+0x120);
 	drc = *ptr & 0xFFFFFFFF;
-	
-	if (((drc >> 20) & 3) == 2) { 
+
+	if (((drc >> 20) & 3) == 2) {
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
-		ctrl.mode = ECC_CORRECT; 
-	} else { 
-		ctrl.mode = ECC_NONE; 
+		ctrl.mode = ECC_CORRECT;
+	} else {
+		ctrl.mode = ECC_NONE;
 	}
 
 }
@@ -960,7 +960,7 @@
 
 	// Activate MMR I/O
 	ulong dev0, capid0;
-	
+
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	if (!(dev0 & 0x1)) {
 		pci_conf_write( 0, 0, 0, 0x48, 1, dev0 | 1);
@@ -971,11 +971,11 @@
 	if ((capid0 >> 8) & 1) {
 		ctrl.cap = ECC_NONE;
 	} else {
-		ctrl.cap = ECC_CORRECT;	
+		ctrl.cap = ECC_CORRECT;
 	}
 
-	ctrl.mode = ECC_NONE; 
-	
+	ctrl.mode = ECC_NONE;
+
 	/*
 	ulong toto;
 	pci_conf_write(0, 31, 3, 0x40, 1,  0x1);
@@ -992,7 +992,7 @@
 	pci_conf_read(0, 31, 1, 0x0, 4, &toto);
 	hprint(11,50,toto)	;
 	pci_conf_read(0, 31, 2, 0x0, 4, &toto);
-	hprint(11,60,toto)	;	
+	hprint(11,60,toto)	;
 	*/
 }
 
@@ -1005,26 +1005,26 @@
 	unsigned long syndrome;
 	int channel;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 0x81)  {
 		unsigned long eap;
 		unsigned long derrsyn;
-		// Read the error location, syndrome and channel 
+		// Read the error location, syndrome and channel
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 4, &eap);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5C, 1, &derrsyn);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5D, 1, &des);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFF000) >> 12;
 		syndrome = derrsyn;
 		channel = des & 1;
 		bits = (errsts & 0x80)?0:1;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, bits, syndrome, channel);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2,  0x81);
 	}
 }
@@ -1035,7 +1035,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED };
 	unsigned long drc;
 
-	// Fill in the correct memory capabilites 
+	// Fill in the correct memory capabilites
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x7C, 4, &drc);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(drc >> 20)&3];
@@ -1048,25 +1048,25 @@
 	unsigned long page, offset;
 	unsigned long syndrome;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 3) {
 		unsigned long eap;
 		unsigned long derrsyn;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x8C, 4, &eap);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x86, 1, &derrsyn);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		offset = (eap & 0xFE) << 4;
 		page = (eap & 0x3FFFFFFE) >> 8;
 		syndrome = derrsyn;
 		bits = ((errsts & 3) == 1)?1:2;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, offset, bits==1?1:0, syndrome, 0);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
 	}
 }
@@ -1078,7 +1078,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_CORRECT };
 	unsigned long mchcfg;
 
-	// Fill in the correct memory capabilites 
+	// Fill in the correct memory capabilites
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xbe, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
@@ -1091,22 +1091,22 @@
 	unsigned long page;
 	unsigned long syndrome;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 3) {
 		unsigned long eap;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xc4, 4, &eap);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFF000) >> 4;
 		syndrome = eap & 0xFF;
 		bits = ((errsts & 3) == 1)?1:2;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, bits==1?1:0, syndrome, 0);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, 3);
 	}
 }
@@ -1117,7 +1117,7 @@
 	static const int ddim[] = { ECC_NONE, ECC_RESERVED, ECC_CORRECT, ECC_RESERVED };
 	unsigned long mchcfg;
 
-	// Fill in the correct memory capabilites 
+	// Fill in the correct memory capabilites
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
@@ -1131,25 +1131,25 @@
 	unsigned long syndrome;
 	int channel;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 3) {
 		unsigned long eap;
 		unsigned long derrctl_sts;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFF800) >> 11;
 		channel = eap & 1;
 		syndrome = derrctl_sts & 0xFF;
 		bits = ((errsts & 3) == 1)?1:2;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, bits==1?1:0, syndrome, channel);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);
 	}
 }
@@ -1161,12 +1161,12 @@
 	unsigned long mchcfg;
 	unsigned long errsts;
 
-	// Fill in the correct memory capabilites 
+	// Fill in the correct memory capabilites
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x50, 2, &mchcfg);
 	ctrl.cap = ECC_CORRECT;
 	ctrl.mode = ddim[(mchcfg >> 7)&3];
 
-	// Clear any prexisting error reports 
+	// Clear any prexisting error reports
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);
 }
@@ -1179,25 +1179,25 @@
 	unsigned char syndrome;
 	int channel;
 	int bits;
-	// Read the error status 
+	// Read the error status
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
 	if (errsts & 3) {
 		unsigned long eap;
 		unsigned long derrctl_sts;
-		// Read the error location 
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE4, 4, &eap);
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xE2, 2, &derrctl_sts);
 
-		// Parse the error location and error type 
+		// Parse the error location and error type
 		page = (eap & 0xFFFFFE00) >> 9;
 		channel = eap & 1;
 		syndrome = derrctl_sts & 0xFF;
 		bits = ((errsts & 3) == 1)?1:2;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, 0, bits==1?1:0, syndrome, channel);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);
 	}
 }
@@ -1211,38 +1211,38 @@
 	int channel;
 	int bits;
 	int errocc;
-	
+
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, &errsts);
-	
+
 	errocc = errsts & 3;
-	
+
 	if ((errocc == 1) || (errocc == 2)) {
 		unsigned long eap, offset;
-		unsigned long derrctl_sts;		
-		
-		// Read the error location 
+		unsigned long derrctl_sts;
+
+		// Read the error location
 		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x58, 4, &eap);
-		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5C, 1, &derrctl_sts);		
-		
-		// Parse the error location and error type 
+		pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, 0x5C, 1, &derrctl_sts);
+
+		// Parse the error location and error type
 		channel = eap & 1;
 		eap = eap & 0xFFFFFF80;
 		page = eap >> 12;
 		offset = eap & 0xFFF;
-		syndrome = derrctl_sts & 0xFF;		
+		syndrome = derrctl_sts & 0xFF;
 		bits = errocc & 1;
 
-		// Report the error 
+		// Report the error
 		print_ecc_err(page, offset, bits, syndrome, channel);
 
-		// Clear the error status 
+		// Clear the error status
 		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);
-	} 
-	
+	}
+
 	else if (errocc == 3) {
-	
-		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);	
-	
+
+		pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn, 0xC8, 2, errsts & 3);
+
 	}
 }
 
@@ -1256,45 +1256,45 @@
 	pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, &nerr);
 
 	if (ferr & 0x0101) {
-			// Find out about the first correctable error 
+			// Find out about the first correctable error
 			unsigned long celog_add;
 			unsigned long celog_syndrome;
 			unsigned long page;
 
-			// Read the error location 
+			// Read the error location
 			pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA0, 4,&celog_add);
-			// Read the syndrome 
+			// Read the syndrome
 			pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xC4, 2, &celog_syndrome);
 
-			// Parse the error location 
+			// Parse the error location
 			page = (celog_add & 0x7FFFFFFC) >> 2;
 
-			// Report the error 
+			// Report the error
 			print_ecc_err(page, 0, 1, celog_syndrome, 0);
 
-			// Clear Bit 
+			// Clear Bit
 			pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, ferr& 0x0101);
 	}
 
 	if (ferr & 0x4646) {
-			// Found out about the first uncorrectable error 
+			// Found out about the first uncorrectable error
 			unsigned long uccelog_add;
 			unsigned long page;
 
-			// Read the error location 
+			// Read the error location
 			pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn +1, 0xA4, 4, &uccelog_add);
 
-			// Parse the error location 
+			// Parse the error location
 			page = (uccelog_add & 0x7FFFFFFC) >> 2;
 
-			// Report the error 
+			// Report the error
 			print_ecc_err(page, 0, 0, 0, 0);
 
-			// Clear Bit 
+			// Clear Bit
 			pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x80, 2, ferr & 0x4646);
 	}
 
-	// Check if DRAM_NERR contains data 
+	// Check if DRAM_NERR contains data
 	if (nerr & 0x4747) {
 			 pci_conf_write(ctrl.bus, ctrl.dev, ctrl.fn +1, 0x82, 2, nerr & 0x4747);
 	}
@@ -1316,20 +1316,20 @@
 	int msr_lo, msr_hi;
 	float coef;
 
-	
+
 	/* Find multiplier (by MSR) */
-	if (cpu_id.vers.bits.family == 6) 
+	if (cpu_id.vers.bits.family == 6)
 	{
-		if(cpu_id.fid.bits.eist & 1) 
+		if(cpu_id.fid.bits.eist & 1)
 		{
 			rdmsr(0x198, msr_lo, msr_hi);
-			coef = ((msr_lo) >> 8) & 0x1F;							
-			if ((msr_lo >> 14) & 0x1) { coef += 0.5f; }		
+			coef = ((msr_lo) >> 8) & 0x1F;
+			if ((msr_lo >> 14) & 0x1) { coef += 0.5f; }
 			// Atom Fix
 			if(coef == 6)
 			{
-				coef = ((msr_hi) >> 8) & 0x1F;							
-				if ((msr_hi >> 14) & 0x1) { coef += 0.5f; }							
+				coef = ((msr_hi) >> 8) & 0x1F;
+				if ((msr_hi >> 14) & 0x1) { coef += 0.5f; }
 			}
 		} else {
 			rdmsr(0x2A, msr_lo, msr_hi);
@@ -1350,7 +1350,7 @@
 			coef = (msr_lo >> 24) & 0x1F;
 		}
 	}
-	
+
 	return coef;
 }
 
@@ -1358,7 +1358,7 @@
 {
 	unsigned int msr_lo, msr_hi;
 	float coef;
-	
+
 	/* Find multiplier (by MSR) */
 	/* First, check if Flexible Ratio is Enabled */
 	rdmsr(0x194, msr_lo, msr_hi);
@@ -1375,14 +1375,14 @@
 {
 	unsigned int msr_lo, msr_hi;
 	float coef;
-	
+
 	rdmsr(0xCE, msr_lo, msr_hi);
-	coef = (msr_lo >> 8) & 0xFF;		
+	coef = (msr_lo >> 8) & 0xFF;
 
 	return coef;
 }
 
-static void poll_fsb_ct(void) 
+static void poll_fsb_ct(void)
 {
 	unsigned long mcr, mdr;
 	double dramratio, dramclock, fsb;
@@ -1392,17 +1392,17 @@
 	mcr = (0x10 << 24); // 10h = Read - 11h = Write
 	mcr += (0x01 << 16); // DRAM Registers located on port 01h
 	mcr += (0x01 << 8); // DRP = 00h, DTR0 = 01h, DTR1 = 02h, DTR2 = 03h
-	mcr &= 0xFFFFFFF0; // bit 03:00 RSVD	
-	
+	mcr &= 0xFFFFFFF0; // bit 03:00 RSVD
+
 	/* Send Message to GMCH */
-	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);	
-	
+	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);
+
 	/* Read Answer from Sideband bus */
-	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);			
-	
+	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);
+
 	/* Get RAM ratio */
 	switch (mdr & 0x3) {
-		default: 
+		default:
 		case 0:	dramratio = 3.0f; break;
 		case 1:	dramratio = 4.0f; break;
 		case 2:	dramratio = 5.0f; break;
@@ -1442,7 +1442,7 @@
 		rdmsr(0xc0010015, mcgsrl, mcgsth);
 		fid = ((mcgsrl >> 24)& 0x3F);
 	}
-	
+
 	/* Extreme simplification. */
 	coef = ( fid / 2 ) + 4.0;
 
@@ -1456,7 +1456,7 @@
 		temp2 = (dramchr & 0x7);
 		clockratio = coef;
 		ram_type = 2;
-	
+
 		switch (temp2) {
 			case 0x0:
 				clockratio = (int)(coef);
@@ -1470,15 +1470,15 @@
 			case 0x3:
 				clockratio = (int)(coef * 3.0f/6.0f);
 				break;
-			}	
-	
+			}
+
 	 } else {
 	 /* OLD K8 */
 		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 		temp2 = (dramchr >> 20) & 0x7;
 		ram_type = 1;
 		clockratio = coef;
-	
+
 		switch (temp2) {
 			case 0x0:
 				clockratio = (int)(coef * 2.0f);
@@ -1519,7 +1519,7 @@
 	double dramclock;
 	ulong offset = 0;
 	int ram_type = 2;
-	
+
 		/* First, we need the clock ratio */
 		pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 		temp2 = (dramchr & 0x7);
@@ -1530,7 +1530,7 @@
 			case 0x5: temp2++;
 			case 0x4: temp2++;
 			default:  temp2 += 3;
-		}	
+		}
 
 	/* Compute the final DRAM Clock */
 	if (((cpu_id.vers.bits.extendedModel >> 4) & 0xFF) == 1) {
@@ -1563,23 +1563,23 @@
 			if ( (dx / divisor) <= target )
 				break;
 
-		
+
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
-	
+
 	// If Channel A not enabled, switch to channel B
 	if(((dramchr>>14) & 0x1))
 	{
 		offset = 0x100;
-		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);	
+		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
 	}
-	
+
 	//DDR2 or DDR3
 	if ((dramchr >> 8)&1) {
 		ram_type = 3;
 	} else {
 		ram_type = 2;;
 	}
-		
+
 		dramclock = ((dx / divisor) / 6.0) + 0.25;
 }
 
@@ -1594,12 +1594,12 @@
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb, did;
 	unsigned int mcgsrl,mcgsth, fid, did_raw;
-	 
+
 	// Get current FID & DID
  	rdmsr(0xc0010071, mcgsrl, mcgsth);
  	did_raw = mcgsrl & 0xF;
  	fid = (mcgsrl >> 4) & 0xF;
-  
+
 	switch(did_raw)
 	{
 		default:
@@ -1611,10 +1611,10 @@
 			break;
 		case 0x2:
 			did = 2.0f;
-			break;					
+			break;
 		case 0x3:
 			did = 3.0f;
-			break;		
+			break;
 		case 0x4:
 			did = 4.0f;
 			break;
@@ -1623,82 +1623,82 @@
 			break;
 		case 0x6:
 			did = 8.0f;
-			break;			
+			break;
 		case 0x7:
 			did = 12.0f;
-			break;			
+			break;
 		case 0x8:
 			did = 16.0f;
-			break;	
+			break;
 	}
 
   fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / did));
-		
+
 	/* Finaly, we need the clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
-	
+
 	if(((dramchr >> 14) & 0x1) == 1)
 	{
-		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);				
+		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);
 	}
-	
+
 	temp2 = (dramchr & 0x1F);
 
 	switch (temp2) {
 		default:
-		case 0x06: 
-			dramratio = 4.0f; 
+		case 0x06:
+			dramratio = 4.0f;
 			break;
-		case 0x0A: 
-			dramratio = 16.0f / 3.0f; 
+		case 0x0A:
+			dramratio = 16.0f / 3.0f;
 			break;
-		case 0x0E: 
-			dramratio = 20.0f / 3.0f; 
+		case 0x0E:
+			dramratio = 20.0f / 3.0f;
 			break;
-		case 0x12: 
-			dramratio = 8.0f; 
+		case 0x12:
+			dramratio = 8.0f;
 			break;
-		case 0x16: 
-			dramratio = 28.0f / 3.0f; 
-			break;						
-	}	
-	
+		case 0x16:
+			dramratio = 28.0f / 3.0f;
+			break;
+	}
+
 	dramclock = fsb * dramratio;
-	
+
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
 
 }
 
-static void poll_fsb_k16(void) 
+static void poll_fsb_k16(void)
 {
 
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
 
-	// FIXME: Unable to find a real way to detect multiplier. 
+	// FIXME: Unable to find a real way to detect multiplier.
 	fsb = 100.0f;
-		
+
 	/* Clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
 	switch (dramchr & 0x1F) {
 		default:
 		case 0x04: /* 333 */
-			dramratio = 10.0f / 3.0f; 
-			break;			
+			dramratio = 10.0f / 3.0f;
+			break;
 		case 0x06: /* 400 */
-			dramratio = 4.0f; 
+			dramratio = 4.0f;
 			break;
 		case 0x0A: /* 533 */
-			dramratio = 16.0f / 3.0f; 
+			dramratio = 16.0f / 3.0f;
 			break;
 		case 0x0E: /* 667 */
-			dramratio = 20.0f / 3.0f; 
+			dramratio = 20.0f / 3.0f;
 			break;
 		case 0x12: /* 800 */
-			dramratio = 8.0f; 
-			break;	
+			dramratio = 8.0f;
+			break;
 		case 0x16: /* 933 */
 			dramratio = 28.0f / 3.0f;
 			break;
@@ -1707,11 +1707,11 @@
 			break;
 		case 0x1A: /* 1066 */
 			dramratio = 32.0f / 3.0f;
-			break;	
-	}	
-	
+			break;
+	}
+
 	dramclock = fsb * dramratio;
-	
+
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
 
@@ -1723,89 +1723,89 @@
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
 	unsigned int mcgsrl,mcgsth, fid, did;
-	 
+
 	// Get current FID & DID
  	rdmsr(0xc0010071, mcgsrl, mcgsth);
  	fid = mcgsrl & 0x3F;
  	did = (mcgsrl >> 6) & 0x7;
-  
+
   fsb = ((extclock / 1000.0f) / ((fid + 16.0f) / (2^did)) / 2);
-	
+
 	/* Finaly, we need the clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
-	
+
 	if(((dramchr >> 14) & 0x1) == 1)
 	{
-		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);				
+		pci_conf_read(0, 24, 2, 0x194, 4, &dramchr);
 	}
-	
+
 	temp2 = (dramchr & 0x1F);
 
 	switch (temp2) {
-		case 0x04: 
-			dramratio = 10.0f / 3.0f; 
+		case 0x04:
+			dramratio = 10.0f / 3.0f;
 			break;
 		default:
-		case 0x06: 
-			dramratio = 4.0f; 
+		case 0x06:
+			dramratio = 4.0f;
 			break;
-		case 0x0A: 
-			dramratio = 16.0f / 3.0f; 
+		case 0x0A:
+			dramratio = 16.0f / 3.0f;
 			break;
-		case 0x0E: 
-			dramratio = 20.0f / 3.0f; 
+		case 0x0E:
+			dramratio = 20.0f / 3.0f;
 			break;
-		case 0x12: 
-			dramratio = 8.0f; 
+		case 0x12:
+			dramratio = 8.0f;
 			break;
-		case 0x16: 
-			dramratio = 28.0f / 3.0f; 
-			break;						
-		case 0x1A: 
-			dramratio = 32.0f / 3.0f; 
-			break;	
-		case 0x1F: 
-			dramratio = 36.0f / 3.0f; 
-			break;				
-	}	
-	
+		case 0x16:
+			dramratio = 28.0f / 3.0f;
+			break;
+		case 0x1A:
+			dramratio = 32.0f / 3.0f;
+			break;
+		case 0x1F:
+			dramratio = 36.0f / 3.0f;
+			break;
+	}
+
 	dramclock = fsb * dramratio;
-	
+
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
 
 }
 
-static void poll_fsb_k14(void) 
+static void poll_fsb_k14(void)
 {
 
 	unsigned long dramchr;
 	double dramratio, dramclock, fsb;
 
-	// FIXME: Unable to find a real way to detect multiplier. 
+	// FIXME: Unable to find a real way to detect multiplier.
   fsb = 100.0f;
-		
+
 	/* Clock ratio */
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 
 	switch (dramchr & 0x1F) {
 		default:
-		case 0x06: 
-			dramratio = 4.0f; 
+		case 0x06:
+			dramratio = 4.0f;
 			break;
-		case 0x0A: 
-			dramratio = 16.0f / 3.0f; 
+		case 0x0A:
+			dramratio = 16.0f / 3.0f;
 			break;
-		case 0x0E: 
-			dramratio = 20.0f / 3.0f; 
+		case 0x0E:
+			dramratio = 20.0f / 3.0f;
 			break;
-		case 0x12: 
-			dramratio = 8.0f; 
-			break;					
-	}	
-	
+		case 0x12:
+			dramratio = 8.0f;
+			break;
+	}
+
 	dramclock = fsb * dramratio;
-	
+
 	/* print */
 	print_cpu_line(dramclock, fsb, 3);
 
@@ -1819,9 +1819,9 @@
 	float coef = getP4PMmultiplier();
 	long *ptr;
 	int ddr_type;
-	
+
 	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
-	
+
 	/* Find dramratio */
 	pci_conf_read( 0, 0, 0, 0x44, 4, &dev0);
 	dev0 = dev0 & 0xFFFFC000;
@@ -1832,7 +1832,7 @@
 	dramratio = 1;
 
 	mchcfg2 = (mchcfg >> 4)&3;
-	
+
 	if ((drc&3) != 2) {
 		// We are in DDR1 Mode
 		if (mchcfg2 == 1) { dramratio = 0.8; } else { dramratio = 1; }
@@ -1859,13 +1859,13 @@
 			}
 		}
 	}
-	// Compute RAM Frequency 
+	// Compute RAM Frequency
 	fsb = ((extclock / 1000) / coef);
 	dramclock = fsb * dramratio;
 
-	
+
 	print_cpu_line(dramclock, fsb, ddr_type);
-	
+
 }
 
 static void poll_fsb_i945(void) {
@@ -1917,7 +1917,7 @@
 		case 0: fsb_mch = 400; break;
 		default:
 		case 1: fsb_mch = 533; break;
-		case 2:	fsb_mch = 667; break;	
+		case 2:	fsb_mch = 667; break;
 	}
 
 
@@ -1929,7 +1929,7 @@
 			case 4:	dramratio = 5.0f/3.0f; break;
 		}
 		break;
-		
+
 	default:
 	case 533:
 		switch ((mchcfg >> 4)&7) {
@@ -1974,7 +1974,7 @@
 	switch (mchcfg & 7) {
 		case 1: fsb_mch = 533; break;
 		case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;				
+		case 3:	fsb_mch = 667; break;
 		default: fsb_mch = 1066; break;
 	}
 
@@ -1987,7 +1987,7 @@
 			case 2:	dramratio = 2.0; break;
 		}
 		break;
-		
+
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
@@ -2034,9 +2034,9 @@
 		case 0: fsb_mch = 1066; break;
 		case 1: fsb_mch = 533; break;
 		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;		
+		case 3:	fsb_mch = 667; break;
 		case 4: fsb_mch = 1333; break;
-		case 6: fsb_mch = 1600; break;					
+		case 6: fsb_mch = 1600; break;
 	}
 
 
@@ -2048,7 +2048,7 @@
 			case 3:	dramratio = 3.0; break;
 		}
 		break;
-		
+
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
@@ -2070,7 +2070,7 @@
 			case 5:	dramratio = 5.0f/2.0f; break;
 		}
 		break;
-	
+
 	case 1333:
 		switch ((mchcfg >> 4)&7) {
 			case 2:	dramratio = 1.0f; break;
@@ -2114,14 +2114,14 @@
 	/* Find dramratio */
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	dev0 &= 0xFFFFC000;
-	
-	ptr = (long*)(dev0+0x260);
-	c0ckectrl = *ptr & 0xFFFFFFFF;	
 
-	
+	ptr = (long*)(dev0+0x260);
+	c0ckectrl = *ptr & 0xFFFFFFFF;
+
+
 	// If DIMM 0 not populated, check DIMM 1
 	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
-	
+
 	ptr=(long*)(dev0+0xC00);
 	mchcfg = *ptr & 0xFFFF;
 	dramratio = 1;
@@ -2130,9 +2130,9 @@
 		case 0: fsb_mch = 1066; break;
 		case 1: fsb_mch = 533; break;
 		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;		
+		case 3:	fsb_mch = 667; break;
 		case 4: fsb_mch = 1333; break;
-		case 6: fsb_mch = 1600; break;					
+		case 6: fsb_mch = 1600; break;
 	}
 
 
@@ -2144,7 +2144,7 @@
 			case 3:	dramratio = 3.0; break;
 		}
 		break;
-		
+
 	default:
 	case 800:
 		switch ((mchcfg >> 4)&7) {
@@ -2166,7 +2166,7 @@
 			case 5:	dramratio = 5.0f/2.0f; break;
 		}
 		break;
-	
+
 	case 1333:
 		switch ((mchcfg >> 4)&7) {
 			case 2:	dramratio = 1.0f; break;
@@ -2190,18 +2190,18 @@
 	// On P45, check 1A8
 	if(Device_ID > 0x2E00 && imc_type != 8) {
 		ptr = (long*)(dev0+offset+0x1A8);
-		Memory_Check = *ptr & 0xFFFFFFFF;	
+		Memory_Check = *ptr & 0xFFFFFFFF;
 		Memory_Check >>= 2;
 		Memory_Check &= 1;
 		Memory_Check = !Memory_Check;
 	} else if (imc_type == 8) {
 		ptr = (long*)(dev0+offset+0x224);
-		Memory_Check = *ptr & 0xFFFFFFFF;	
+		Memory_Check = *ptr & 0xFFFFFFFF;
 		Memory_Check &= 1;
-		Memory_Check = !Memory_Check;		
+		Memory_Check = !Memory_Check;
 	} else {
 		ptr = (long*)(dev0+offset+0x1E8);
-		Memory_Check = *ptr & 0xFFFFFFFF;		
+		Memory_Check = *ptr & 0xFFFFFFFF;
 	}
 
 	//Determine DDR-II or DDR-III
@@ -2237,8 +2237,8 @@
 	switch (mchcfg & 7) {
 		case 1: fsb_mch = 533; break;
 		default: case 2:	fsb_mch = 800; break;
-		case 3:	fsb_mch = 667; break;				
-		case 6:	fsb_mch = 1066; break;			
+		case 3:	fsb_mch = 667; break;
+		case 6:	fsb_mch = 1066; break;
 	}
 
 
@@ -2304,17 +2304,17 @@
   dramratio = 1;
 
 	switch (ddrfrq) {
-			case 0:	
-			case 1:	
-			case 4:					
-				dramratio = 1.0; 
+			case 0:
+			case 1:
+			case 4:
+				dramratio = 1.0;
 				break;
-			case 2:	
-				dramratio = 5.0f/4.0f; 
+			case 2:
+				dramratio = 5.0f/4.0f;
 				break;
-			case 3:	
-			case 7:	
-				dramratio = 4.0f/5.0f; 
+			case 3:
+			case 7:
+				dramratio = 4.0f/5.0f;
 				break;
 		}
 
@@ -2335,7 +2335,7 @@
 	float mratio, nratio;
 	unsigned long reg74, reg60;
 	float coef = getP4PMmultiplier();
-	
+
 	/* Find dramratio */
 	pci_conf_read(0, 0, 2, 0x74, 2, &reg74);
 	pci_conf_read(0, 0, 2, 0x60, 4, &reg60);
@@ -2345,7 +2345,7 @@
 	// If M or N = 0, then M or N = 16
 	if (mratio == 0) { mratio = 16; }
 	if (nratio == 0) { nratio = 16; }
-	
+
 	// Check if synchro or pseudo-synchro mode
 	if((reg60 >> 22) & 1) {
 		dramratio = 1;
@@ -2359,7 +2359,7 @@
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 2);
-	
+
 }
 
 static void poll_fsb_i875(void) {
@@ -2406,13 +2406,13 @@
 
 	/* For synchro only chipsets */
 	pci_conf_read( 0, 0, 0, 0x02, 2, &idetect);
-	if (idetect == 0x2540 || idetect == 0x254C) 
+	if (idetect == 0x2540 || idetect == 0x254C)
 	{
 		print_cpu_line(fsb, fsb, 1);
 	} else {
 		/* Print the controller name */
 		col = COL_SPEC;
-		cprint(LINE_CPU, col, "Chipset:               ");	
+		cprint(LINE_CPU, col, "Chipset:               ");
 		col += 9;
 		/* Print the controller name */
 		name = controllers[ctrl.index].name;
@@ -2423,14 +2423,14 @@
 			col++;
 			temp++;
 		}
-		
+
 		if(temp < 36){
 			cprint(LINE_CPU, col +1, "- FSB : ");
 			col += 9;
 			dprint(LINE_CPU, col, fsb, 3,0);
 			col += 3;
 		}
-	
+
 	}
 }
 
@@ -2509,7 +2509,7 @@
 
 	/* Print the controller name */
 	col = COL_SPEC;
-	cprint(LINE_CPU, col, "Chipset:               ");	
+	cprint(LINE_CPU, col, "Chipset:               ");
 	col += 9;
 	/* Print the controller name */
 	name = controllers[ctrl.index].name;
@@ -2520,7 +2520,7 @@
 		col++;
 		temp++;
 	}
-	
+
 	if(temp < 36){
 		cprint(LINE_CPU, col +1, "- FSB : ");
 		col += 9;
@@ -2576,11 +2576,11 @@
 
 	/* Find dramratio */
 	/* D0 MsgRd, 05 Zunit, 03 MSR */
-	pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0050300 );		
-	pci_conf_read(0, 0, 0, 0xD4, 4, &msr );		
+	pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0050300 );
+	pci_conf_read(0, 0, 0, 0xD4, 4, &msr );
 	fsb = ( msr >> 3 ) & 1;
 
-	dramratio = 0.5; 
+	dramratio = 0.5;
 
 	// Compute RAM Frequency
 	if (( msr >> 3 ) & 1) {
@@ -2588,7 +2588,7 @@
 	} else {
 		fsb = 400;
 	}
-	
+
 /*
 	switch (( msr >> 0 ) & 7) {
 		case 0:
@@ -2612,9 +2612,9 @@
 		default:
 			gfx = 0;
 			break;
-	}	
+	}
 	*/
-	
+
 	dramclock = fsb * dramratio;
 
 	// Print DRAM Freq
@@ -2632,7 +2632,7 @@
 
 
 	fsb = ((extclock /1000) / coef);
-	
+
 	/* Print QPI Speed (if ECC not supported) */
 	/*
 	if(ctrl.mode == ECC_NONE && cpu_id.vers.bits.model == 10) {
@@ -2643,20 +2643,20 @@
 		dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0);
 		col += 1;
 		cprint(LINE_CPU+5, col, ".");
-		col += 1;		
+		col += 1;
 		qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10;
 		dprint(LINE_CPU+5, col, qpi_speed, 1,0);
-		col += 1;		
+		col += 1;
 		cprint(LINE_CPU+5, col +1, "GT/s");
-		col += 5;	
+		col += 5;
 	}
 	*/
-	
+
 	/* Get the clock ratio */
-	
+
 	pci_conf_read(nhm_bus, 3, 4, 0x54, 2, &mc_dimm_clk_ratio);
 	dramratio = (mc_dimm_clk_ratio & 0x1F);
-	
+
 	// Compute RAM Frequency
 	fsb = ((extclock / 1000) / coef);
 	dramclock = fsb * dramratio / 2;
@@ -2686,20 +2686,20 @@
 		dprint(LINE_CPU+5, col, qpi_speed/1000, 1,0);
 		col += 1;
 		cprint(LINE_CPU+5, col, ".");
-		col += 1;		
+		col += 1;
 		qpi_speed = ((qpi_speed / 1000) - (int)(qpi_speed / 1000)) * 10;
 		dprint(LINE_CPU+5, col, qpi_speed, 1,0);
-		col += 1;		
+		col += 1;
 		cprint(LINE_CPU+5, col +1, "GT/s");
-		col += 5;	
+		col += 5;
 	}
 	*/
-	
+
 	/* Get the clock ratio */
-	
+
 	pci_conf_read(nhm_bus, 3, 4, 0x50, 2, &mc_dimm_clk_ratio);
 	dramratio = (mc_dimm_clk_ratio & 0x1F);
-	
+
 	// Compute RAM Frequency
 	fsb = ((extclock / 1000) / coef);
 	dramclock = fsb * dramratio / 2;
@@ -2715,7 +2715,7 @@
 	unsigned long dev0;
 	float coef = getNHMmultiplier();
 	long *ptr;
-	
+
 	fsb = ((extclock / 1000) / coef);
 
 	/* Find dramratio */
@@ -2723,10 +2723,10 @@
 	dev0 &= 0xFFFFC000;
 	ptr=(long*)(dev0+0x2C20);
 	dramratio = 1;
-	
+
 	/* Get the clock ratio */
 	dramratio = 0.25 * (float)(*ptr & 0x1F);
-	
+
 	// Compute RAM Frequency
 	dramclock = fsb * dramratio;
 
@@ -2741,7 +2741,7 @@
 	unsigned long dev0;
 	float coef = getSNBmultiplier();
 	long *ptr;
-	
+
 	fsb = ((extclock / 1000) / coef);
 
 	/* Find dramratio */
@@ -2749,16 +2749,16 @@
 	dev0 &= 0xFFFFC000;
 	ptr=(long*)(dev0+0x5E04);
 	dramratio = 1;
-	
+
 	/* Get the clock ratio */
 	dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f);
-	
+
 	// Compute RAM Frequency
 	dramclock = fsb * dramratio;
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-	
+
 }
 
 static void poll_fsb_ivb(void) {
@@ -2767,7 +2767,7 @@
 	unsigned long dev0, mchcfg;
 	float coef = getSNBmultiplier();
 	long *ptr;
-	
+
 	fsb = ((extclock / 1000) / coef);
 
 	/* Find dramratio */
@@ -2776,7 +2776,7 @@
 	ptr=(long*)(dev0+0x5E04);
 	mchcfg = *ptr & 0xFFFF;
 	dramratio = 1;
-	
+
 	/* Get the clock ratio */
 	switch((mchcfg >> 8) & 0x01)
 	{
@@ -2784,16 +2784,16 @@
 			dramratio = (float)(*ptr & 0x1F) * (133.34f / 100.0f);
 			break;
 		case 0x1:
-			dramratio = (float)(*ptr & 0x1F) * (100.0f / 100.0f);	
+			dramratio = (float)(*ptr & 0x1F) * (100.0f / 100.0f);
 			break;
 	}
-	
+
 	// Compute RAM Frequency
 	dramclock = fsb * dramratio;
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-	
+
 }
 
 static void poll_fsb_snbe(void) {
@@ -2801,24 +2801,24 @@
 	double dramclock, dramratio, fsb;
 	unsigned long dev0;
 	float coef = getSNBmultiplier();
-	
+
 	fsb = ((extclock / 1000) / coef);
 
 	/* Find dramratio */
 	pci_conf_read( 0xFF, 10, 1, 0x98, 4, &dev0);
 	dev0 &= 0xFFFFFFFF;
 	dramratio = 1;
-	
+
 	/* Get the clock ratio */
 	dramratio = (float)(dev0 & 0x3F) * (66.67f / 100.0f);
-	
+
 	// Compute RAM Frequency
 	dramclock = fsb * dramratio;
 
 	// Print DRAM Freq
 	print_cpu_line(dramclock, fsb, 3);
-	
-	
+
+
 
 }
 
@@ -2842,7 +2842,7 @@
 	rcd = (reg8c >> 24) & 0xF;
 	rp = (reg9c >> 8) & 0xF;
 	ras = (reg8c >> 16) & 0x3F;
-	
+
 	if (reg80 & 0x3) {
 		chan = 2;
 	} else {
@@ -2884,7 +2884,7 @@
 	ras = 10 - temp;
 
 	// Print 64 or 128 bits mode
-	if (((*ptr2 >> 21)&3) > 0) { 
+	if (((*ptr2 >> 21)&3) > 0) {
 		chan = 2;
 	} else {
 		chan = 1;
@@ -2951,7 +2951,7 @@
 	if      (temp == 1) { chan = 2; }
 	else if (temp == 2) { chan = 2; }
 	else		    { chan = 1; }
-		
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 
 }
@@ -2970,18 +2970,18 @@
 	dev0 &= 0xFFFFC000;
 
 	ptr = (long*)(dev0+0x260);
-	c0ckectrl = *ptr & 0xFFFFFFFF;	
+	c0ckectrl = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+0x660);
 	c1ckectrl = *ptr & 0xFFFFFFFF;
-	
+
 	// If DIMM 0 not populated, check DIMM 1
 	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x29C);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
 
-	ptr = (long*)(dev0+offset+0x250);	
+	ptr = (long*)(dev0+offset+0x250);
 	Precharge_Register = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+offset+0x252);
@@ -3003,10 +3003,10 @@
 	// RAS Active to precharge (tRAS)
 	ras = (Precharge_Register >> 11) & 0x1F;
 
-	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { 
-		chan = 2; 
+	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+		chan = 2;
 	}	else {
-		chan = 1; 
+		chan = 1;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
@@ -3020,24 +3020,24 @@
 	long *ptr;
 	int rcd,rp,ras,chan;
 	float cas;
-	
+
 	//Now, read MMR Base Address
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	dev0 &= 0xFFFFC000;
 
 	ptr = (long*)(dev0+0x1200);
-	c0ckectrl = *ptr & 0xFFFFFFFF;	
+	c0ckectrl = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+0x1300);
 	c1ckectrl = *ptr & 0xFFFFFFFF;
-	
+
 	// If DIMM 0 not populated, check DIMM 1
 	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x100);
 
 	ptr = (long*)(dev0+offset+0x121C);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
 
-	ptr = (long*)(dev0+offset+0x1214);	
+	ptr = (long*)(dev0+offset+0x1214);
 	Precharge_Register = *ptr & 0xFFFFFFFF;
 
 	// CAS Latency (tCAS)
@@ -3053,7 +3053,7 @@
 	ras = (Precharge_Register >> 21) & 0x1F;
 
 
-	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { 
+	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
 		chan = 2;
 	}	else {
 		chan = 1;
@@ -3069,7 +3069,7 @@
 	ulong dev0, Device_ID, c0ckectrl, c1ckectrl, offset;
 	ulong ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register;
 	long *ptr;
-	
+
 	pci_conf_read( 0, 0, 0, 0x02, 2, &Device_ID);
 	Device_ID &= 0xFFFF;
 
@@ -3078,18 +3078,18 @@
 	dev0 &= 0xFFFFC000;
 
 	ptr = (long*)(dev0+0x260);
-	c0ckectrl = *ptr & 0xFFFFFFFF;	
+	c0ckectrl = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+0x660);
 	c1ckectrl = *ptr & 0xFFFFFFFF;
-	
+
 	// If DIMM 0 not populated, check DIMM 1
 	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x265);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
 
-	ptr = (long*)(dev0+offset+0x25D);	
+	ptr = (long*)(dev0+offset+0x25D);
 	Precharge_Register = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+offset+0x252);
@@ -3114,11 +3114,11 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = Precharge_Register & 0x3F;
-	
-	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { 
-		chan = 2; 
+
+	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+		chan = 2;
 	}	else {
-		chan = 1; 
+		chan = 1;
 	}
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
@@ -3136,18 +3136,18 @@
 	dev0 &= 0xFFFFC000;
 
 	ptr = (long*)(dev0+0x260);
-	c0ckectrl = *ptr & 0xFFFFFFFF;	
+	c0ckectrl = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+0x660);
 	c1ckectrl = *ptr & 0xFFFFFFFF;
-	
+
 	// If DIMM 0 not populated, check DIMM 1
 	((c0ckectrl) >> 20 & 0xF)?(offset = 0):(offset = 0x400);
 
 	ptr = (long*)(dev0+offset+0x265);
 	ODT_Control_Register = *ptr & 0xFFFFFFFF;
 
-	ptr = (long*)(dev0+offset+0x25D);	
+	ptr = (long*)(dev0+offset+0x25D);
 	Precharge_Register = *ptr & 0xFFFFFFFF;
 
 	ptr = (long*)(dev0+offset+0x252);
@@ -3174,11 +3174,11 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = Precharge_Register & 0x3F;
-	
-	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) { 
-		chan = 2; 
+
+	if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {
+		chan = 2;
 	}	else {
-		chan = 1; 
+		chan = 1;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
@@ -3196,7 +3196,7 @@
 	//Now, read MMR Base Address
 	pci_conf_read( 0, 0, 0, 0x48, 4, &dev0);
 	dev0 &= 0xFFFFC000;
-	
+
 	offset = 0x0000;
 
 	ptr = (long*)(dev0+offset+0x4000);
@@ -3213,19 +3213,19 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = (IMC_Register >> 16) & 0xFF;
-	
+
 	// Channels
 	ptr = (long*)(dev0+offset+0x5004);
 	MCMain0_Register = *ptr & 0xFFFF;
 	ptr = (long*)(dev0+offset+0x5008);
 	MCMain1_Register = *ptr & 0xFFFF;
-	
+
 	if(MCMain0_Register == 0 || MCMain1_Register == 0) {
-		chan = 1; 
+		chan = 1;
 	} else {
-		chan = 2; 
+		chan = 2;
 	}
-	
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
@@ -3244,18 +3244,18 @@
 	// Channels
 	ptr = (long*)(dev0+offset+0x5004);
 	MCMain0_Register = *ptr & 0xFFFF;
-	
+
 	ptr = (long*)(dev0+offset+0x5008);
 	MCMain1_Register = *ptr & 0xFFFF;
-	
+
 	if(MCMain0_Register && MCMain1_Register) {
-		chan = 2; 
+		chan = 2;
 	} else {
 		chan = 1;
 	}
-	
+
 	if(MCMain0_Register) { offset = 0x0000; } else {	offset = 0x0400; }
-	
+
 	// CAS Latency (tCAS)
 	ptr = (long*)(dev0+offset+0x4014);
 	IMC_Register = *ptr & 0xFFFFFFFF;
@@ -3272,7 +3272,7 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = (IMC_Register >> 10) & 0x3F;
-	
+
 
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
@@ -3284,7 +3284,7 @@
 	int nb_channel = 0, current_channel = 0;
 	ulong temp, IMC_Register;
 	long *ptr;
-	
+
 	//Read Channel #1
 	pci_conf_read(0xFF, 16, 2, 0x80, 4, &temp);
 	temp &= 0x3F;
@@ -3299,7 +3299,7 @@
 	pci_conf_read(0xFF, 16, 6, 0x80, 4, &temp);
 	temp &= 0x3F;
 	if(temp != 0xB) { current_channel = 4; nb_channel++; }
-	
+
 	//Read Channel #4
 	pci_conf_read(0xFF, 16, 7, 0x80, 4, &temp);
 	temp &= 0x3F;
@@ -3321,7 +3321,7 @@
 
 	// RAS Active to precharge (tRAS)
 	ras = (IMC_Register >> 19) & 0x3F;
-	
+
 
 	print_ram_line(cas, rcd, rp, ras, nb_channel);
 
@@ -3334,18 +3334,18 @@
 	long *ptr;
 	float cas;
 	int rcd, rp, ras, chan;
-	
+
 	//Hard-coded Ambase value (should not be realocated by software when using Memtest86+
 	ambase = 0xFE000000;
   offset = mtr1 = mtr2 = 0;
 
   // Will loop until a valid populated channel is found
-  // Bug  : DIMM 0 must be populated or it will fall in an endless loop  
+  // Bug  : DIMM 0 must be populated or it will fall in an endless loop
   while(((mtr2 & 0xF) < 3) || ((mtr2 & 0xF) > 6)) {
 		ptr = (long*)(ambase+0x378+offset);
 		mtr1 = *ptr & 0xFFFFFFFF;
-	
-		ptr = (long*)(ambase+0x37C+offset);	
+
+		ptr = (long*)(ambase+0x37C+offset);
 		mtr2 = *ptr & 0xFFFFFFFF;
 		offset += 0x8000;
 	}
@@ -3371,10 +3371,10 @@
   if(((mtr1 >> 12) & 3) == 3 && ((mtr1 >> 29) & 3) == 2) { ras = 9; }
 
 
-	if ((mca >> 14) & 1) { 
-		chan = 1; 
+	if ((mca >> 14) & 1) {
+		chan = 1;
 	}	else {
-		chan = 2; 
+		chan = 2;
 	}
 
 	print_ram_line(cas, rcd, rp, ras, chan);
@@ -3394,13 +3394,13 @@
 	rcd = ((drt >> 10) & 1) + 3;
 	rp = ((drt >> 9) & 1) + 3;
 	ras = ((drt >> 14) & 3) + 11;
-	
+
 	if ((ddrcsr & 0xF) >= 0xC) {
 		chan = 2;
 	} else {
 		chan = 1;
 	}
-	
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
@@ -3410,7 +3410,7 @@
 	ulong drt, temp;
 	float cas;
 	int rcd, rp, ras;
-	
+
 	pci_conf_read( 0, 0, 0, 0x78, 4, &drt);
 
 	/* Now, we could print some additionnals timings infos) */
@@ -3437,7 +3437,7 @@
 	if (temp == 0x0) { ras = 7; }
 	if (temp == 0x1) { ras = 6; }
 	if (temp == 0x2) { ras = 5; }
-	
+
 	print_ram_line(cas, rcd, rp, ras, 1);
 
 }
@@ -3473,7 +3473,7 @@
 	ulong drt, temp;
 	float cas;
 	int rcd, rp, ras;
-	
+
 	pci_conf_read( 0, 0, 1, 0x60, 4, &drt);
 
 	/* Now, we could print some additionnals timings infos) */
@@ -3517,22 +3517,22 @@
 
 	pci_conf_read(0, 24, 2, 0x88, 4, &dramtlr);
 	pci_conf_read(0, 24, 2, 0x90, 4, &dramclr);
-	
+
 	if (cpu_id.vers.bits.extendedModel >= 4) {
 		/* NEW K8 0Fh Family 90 nm (DDR2) */
 
 			// CAS Latency (tCAS)
 			tcas = (dramtlr & 0x7) + 1;
-		
+
 			// RAS-To-CAS (tRCD)
 			trcd = ((dramtlr >> 4) & 0x3) + 3;
-		
+
 			// RAS Precharge (tRP)
 			trp = ((dramtlr >> 8) & 0x3) + 3;
-		
+
 			// RAS Active to precharge (tRAS)
 			tras = ((dramtlr >> 12) & 0xF) + 3;
-		
+
 			// Print 64 or 128 bits mode
 			if ((dramclr >> 11)&1) {
 				chan = 2;
@@ -3548,16 +3548,16 @@
 			if (temp == 0x1) { tcas = 2; }
 			if (temp == 0x2) { tcas = 3; }
 			if (temp == 0x5) { tcas = 2.5; }
-		
+
 			// RAS-To-CAS (tRCD)
 			trcd = ((dramtlr >> 12) & 0x7);
-		
+
 			// RAS Precharge (tRP)
 			trp = ((dramtlr >> 24) & 0x7);
-		
+
 			// RAS Active to precharge (tRAS)
 			tras = ((dramtlr >> 20) & 0xF);
-		
+
 			// Print 64 or 128 bits mode
 			if (((dramclr >> 16)&1) == 1) {
 				chan = 2;
@@ -3565,9 +3565,9 @@
 				chan = 1;
 			}
 	}
-	
+
 	print_ram_line(tcas, trcd, trp, tras, chan);
-	
+
 }
 
 static void poll_timings_k10(void) {
@@ -3575,29 +3575,29 @@
 	ulong dramtlr, dramclr, dramchr, dramchrb;
 	ulong offset = 0;
 	int cas, rcd, rp, ras, chan;
-	
+
 	pci_conf_read(0, 24, 2, 0x94, 4, &dramchr);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dramchrb);
-	
+
 	if(((dramchr>>14) & 0x1) || ((dramchr>>14) & 0x1)) { chan = 1; } else { chan = 2; }
-	
+
 	// If Channel A not enabled, switch to channel B
 	if(((dramchr>>14) & 0x1))
 	{
 		offset = 0x100;
-		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);	
+		pci_conf_read(0, 24, 2, 0x94+offset, 4, &dramchr);
 	}
 
 	pci_conf_read(0, 24, 2, 0x88+offset, 4, &dramtlr);
 	pci_conf_read(0, 24, 2, 0x110, 4, &dramclr);
-	
+
 	// CAS Latency (tCAS)
 	if(((dramchr >> 8)&1) || ((dramchr & 0x7) == 0x4)){
 		// DDR3 or DDR2-1066
 		cas = (dramtlr & 0xF) + 4;
 		rcd = ((dramtlr >> 4) & 0x7) + 5;
 		rp = ((dramtlr >> 7) & 0x7) + 5;
-	  ras = ((dramtlr >> 12) & 0xF) + 15;	
+	  ras = ((dramtlr >> 12) & 0xF) + 15;
 	} else {
 	// DDR2-800 or less
 		cas = (dramtlr & 0xF) + 1;
@@ -3605,7 +3605,7 @@
 		rp = ((dramtlr >> 8) & 0x3) + 3;
 	  ras = ((dramtlr >> 12) & 0xF) + 3;
 	}
-		
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
@@ -3613,31 +3613,31 @@
 
 	ulong dramt0, dramlow, dimma, dimmb;
 	int cas, rcd, rp, ras, chan = 0;
-	
+
 	pci_conf_read(0, 24, 2, 0x94, 4, &dimma);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dimmb);
 
-	if(((dimma >> 14) & 0x1) == 0) 
-	{ 
-		chan++; 
-		pci_conf_read(0, 24, 2, 0x88, 4, &dramlow); 
+	if(((dimma >> 14) & 0x1) == 0)
+	{
+		chan++;
+		pci_conf_read(0, 24, 2, 0x88, 4, &dramlow);
 		pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040);
-		pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);	
+		pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);
 	}
-	
-	if(((dimmb >> 14) & 0x1) == 0) 
-	{ 
-		chan++; 
-		pci_conf_read(0, 24, 2, 0x188, 4, &dramlow); 
+
+	if(((dimmb >> 14) & 0x1) == 0)
+	{
+		chan++;
+		pci_conf_read(0, 24, 2, 0x188, 4, &dramlow);
 		pci_conf_write(0, 24, 2, 0x1F0, 4, 0x00000040);
-		pci_conf_read(0, 24, 2, 0x1F4, 4, &dramt0);	
+		pci_conf_read(0, 24, 2, 0x1F4, 4, &dramt0);
 	}
 
 	cas = (dramlow & 0xF) + 4;
 	rcd = (dramt0 & 0xF) + 5;
 	rp = ((dramt0 >> 8) & 0xF) + 5;
   ras = ((dramt0 >> 16) & 0x1F) + 15;
-	
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
@@ -3646,16 +3646,16 @@
 
 	ulong dramt0, dramlow;
 	int cas, rcd, rp, ras;
-	
-	pci_conf_read(0, 24, 2, 0x88, 4, &dramlow); 
+
+	pci_conf_read(0, 24, 2, 0x88, 4, &dramlow);
 	pci_conf_write(0, 24, 2, 0xF0, 4, 0x00000040);
-	pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);	
+	pci_conf_read(0, 24, 2, 0xF4, 4, &dramt0);
 
 	cas = (dramlow & 0xF) + 4;
 	rcd = (dramt0 & 0xF) + 5;
 	rp = ((dramt0 >> 8) & 0xF) + 5;
   ras = ((dramt0 >> 16) & 0x1F) + 15;
-	
+
 	print_ram_line(cas, rcd, rp, ras, 1);
 }
 
@@ -3663,19 +3663,19 @@
 
 	ulong dramp1, dramp2, dimma, dimmb;
 	int cas, rcd, rp, ras, chan = 0;
-	
+
 	pci_conf_read(0, 24, 2, 0x94, 4, &dimma);
 	pci_conf_read(0, 24, 2, 0x194, 4, &dimmb);
 	if(((dimma>>14) & 0x1) || ((dimmb>>14) & 0x1)) { chan = 1; } else { chan = 2; }
-		
-	pci_conf_read(0, 24, 2, 0x200, 4, &dramp1); 
-	pci_conf_read(0, 24, 2, 0x204, 4, &dramp2); 
-	
+
+	pci_conf_read(0, 24, 2, 0x200, 4, &dramp1);
+	pci_conf_read(0, 24, 2, 0x204, 4, &dramp2);
+
 	cas = dramp1 & 0x1F;
 	rcd = (dramp1 >> 8) & 0x1F;
 	rp = (dramp1 >> 16) & 0x1F;
   ras = (dramp1 >> 24) & 0x3F;
-	
+
 	print_ram_line(cas, rcd, rp, ras, chan);
 }
 
@@ -3683,17 +3683,17 @@
 
 	ulong dramt0, dramt1;
 	int cas, rcd, rp, rc, ras;
-	
+
 	pci_conf_read(0, 24, 2, 0x200, 4, &dramt0);
-	pci_conf_read(0, 24, 2, 0x204, 4, &dramt1);	
+	pci_conf_read(0, 24, 2, 0x204, 4, &dramt1);
 
 	cas = (dramt0 & 0x1F);
 	rcd = ((dramt0 >> 8) & 0x1F);
 	rp = ((dramt0 >> 16) & 0x1F);
 	ras = ((dramt0 >> 24) & 0x3F);
-	
-	rc = (dramt1 & 0x3F);	
-	
+
+	rc = (dramt1 & 0x3F);
+
 	print_ram_line(cas, rcd, rp, ras, 1);
 }
 
@@ -3720,7 +3720,7 @@
 	ulong dimm1p, dimm2p, dimm3p;
 	float cas;
 	int rcd, rp, ras, chan;
-	
+
 	pci_conf_read(0, 0, 1, 0x90, 4, &dramtlr);
 	pci_conf_read(0, 0, 1, 0xA0, 4, &dramtlr2);
 	pci_conf_read(0, 0, 1, 0x84, 4, &dramtlr3);
@@ -3733,7 +3733,7 @@
 	if (temp == 0x2) { cas = 2; }
 	if (temp == 0x3) { cas = 3; }
 	if (temp == 0x6) { cas = 2.5; }
-		
+
 	// RAS-To-CAS (tRCD)
 	rcd = ((dramtlr >> 20) & 0xF);
 
@@ -3760,11 +3760,11 @@
 	ulong dtr;
 	float cas;
 	int rcd, rp;
-	
+
 	/* Find dramratio */
 	/* D0 MsgRd, 01 Dunit, 01 DTR */
-	pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0010100 );		
-	pci_conf_read(0, 0, 0, 0xD4, 4, &dtr );		
+	pci_conf_write(0, 0, 0, 0xD0, 4, 0xD0010100 );
+	pci_conf_read(0, 0, 0, 0xD4, 4, &dtr );
 
 	// CAS Latency (tCAS)
 	cas = ((dtr >> 4) & 0x3) + 3;
@@ -3774,7 +3774,7 @@
 
 	// RAS Precharge (tRP)
 	rp = ((dtr >> 0) & 0x3) + 3;
-	
+
 	print_ram_line(cas, rcd, rp, 9, 1);
 
 }
@@ -3782,30 +3782,30 @@
 static void poll_timings_nhm(void) {
 
 	ulong mc_channel_bank_timing, mc_control, mc_channel_mrs_value;
-	float cas; 
+	float cas;
 	int rcd, rp, ras, chan;
 	int fvc_bn = 4;
 
 	/* Find which channels are populated */
-	pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);		
+	pci_conf_read(nhm_bus, 3, 0, 0x48, 2, &mc_control);
 	mc_control = (mc_control >> 8) & 0x7;
-	
+
 	/* Get the first valid channel */
-	if(mc_control & 1) { 
-		fvc_bn = 4; 
-	} else if(mc_control & 2) { 
-		fvc_bn = 5; 
-	}	else if(mc_control & 4) { 
-		fvc_bn = 6; 
+	if(mc_control & 1) {
+		fvc_bn = 4;
+	} else if(mc_control & 2) {
+		fvc_bn = 5;
+	}	else if(mc_control & 4) {
+		fvc_bn = 6;
 	}
 
 	// Now, detect timings
 	// CAS Latency (tCAS) / RAS-To-CAS (tRCD) / RAS Precharge (tRP) / RAS Active to precharge (tRAS)
-	pci_conf_read(nhm_bus, fvc_bn, 0, 0x88, 4, &mc_channel_bank_timing);	
-	pci_conf_read(nhm_bus, fvc_bn, 0, 0x70, 4, &mc_channel_mrs_value);	
+	pci_conf_read(nhm_bus, fvc_bn, 0, 0x88, 4, &mc_channel_bank_timing);
+	pci_conf_read(nhm_bus, fvc_bn, 0, 0x70, 4, &mc_channel_mrs_value);
 	cas = ((mc_channel_mrs_value >> 4) & 0xF ) + 4.0f;
-	rcd = (mc_channel_bank_timing >> 9) & 0xF; 
-	ras = (mc_channel_bank_timing >> 4) & 0x1F; 
+	rcd = (mc_channel_bank_timing >> 9) & 0xF;
+	ras = (mc_channel_bank_timing >> 4) & 0x1F;
 	rp = mc_channel_bank_timing & 0xF;
 
 	// Print 1, 2 or 3 Channels
@@ -3814,30 +3814,30 @@
 	} else if (mc_control == 7) {
 		chan = 3;
 	} else {
-		chan = 2;	
+		chan = 2;
 	}
 	print_ram_line(cas, rcd, rp, ras, chan);
-	
+
 }
 
-static void poll_timings_ct(void) 
+static void poll_timings_ct(void)
 {
 
 	unsigned long mcr,mdr;
-	float cas; 
+	float cas;
 	int rcd, rp, ras;
-	
+
 	/* Build the MCR Message*/
 	mcr = (0x10 << 24); // 10h = Read - 11h = Write
 	mcr += (0x01 << 16); // DRAM Registers located on port 01h
 	mcr += (0x01 << 8); // DRP = 00h, DTR0 = 01h, DTR1 = 02h, DTR2 = 03h
 	mcr &= 0xFFFFFFF0; // bit 03:00 RSVD
-	
+
 	/* Send Message to GMCH */
-	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);	
-	
+	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);
+
 	/* Read Answer from Sideband bus */
-	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);			
+	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);
 
 	// CAS Latency (tCAS)
 	cas = ((mdr >> 12)& 0x7) + 5.0f;
@@ -3850,10 +3850,10 @@
 
 	// RAS is in DTR1. Read Again.
 	mcr = 0x10010200; // Quick Mode ! Awesome !
-	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);	
-	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);	
-			
-	// RAS Active to precharge (tRAS)		
+	pci_conf_write(0, 0, 0, 0xD0, 4, mcr);
+	pci_conf_read(0, 0, 0, 0xD4, 4, &mdr);
+
+	// RAS Active to precharge (tRAS)
 	ras = (mdr >> 20) & 0xF;
 
 	// Print
@@ -3893,7 +3893,7 @@
 	{ 0x1039, 0x0649, "SiS 649","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1039, 0x0661, "SiS 661","DDR-SDRAM",   			0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
 	{ 0x1039, 0x0671, "SiS 671","DDR2-SDRAM",   		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
-	{ 0x1039, 0x0672, "SiS 672","DDR2-SDRAM",   		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },	
+	{ 0x1039, 0x0672, "SiS 672","DDR2-SDRAM",   		0, poll_fsb_p4, poll_timings_nothing, setup_nothing, poll_nothing },
 
 	/* ALi */
 	{ 0x10b9, 0x1531, "ALi Aladdin 4","EDO/SDRAM", 0, poll_fsb_nothing, poll_timings_nothing, setup_nothing, poll_nothing },
@@ -3985,22 +3985,22 @@
 	{ 0x8086, 0x2990, "Intel Q963/Q965","", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
 	{ 0x8086, 0x29A0, "Intel P965/G965","", 		0, poll_fsb_i965, poll_timings_i965, setup_p35, poll_nothing},
 	{ 0x8086, 0x2A00, "Intel GM965/GL960","", 	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
-	{ 0x8086, 0x2A10, "Intel GME965/GLE960","",	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},	
-	{ 0x8086, 0x2A40, "Intel PM/GM45/47","",		0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},	
-	{ 0x8086, 0x29B0, "Intel Q35","", 	 		 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x29C0, "Intel P35/G33","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x29D0, "Intel Q33","",	  	 			0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x29E0, "Intel X38/X48","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},			
-	{ 0x8086, 0x29F0, "Intel 3200/3210","", 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x2E10, "Intel Q45/Q43","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x2E20, "Intel P45/G45","",	  		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x2E30, "Intel G41","", 	 				0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},	
-	{ 0x8086, 0x4001, "Intel 5400A","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
-	{ 0x8086, 0x4003, "Intel 5400B","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
-	{ 0x8086, 0x25D8, "Intel 5000P","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
-	{ 0x8086, 0x25D4, "Intel 5000V","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},	
-	{ 0x8086, 0x25C0, "Intel 5000X","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},		
-	{ 0x8086, 0x25D0, "Intel 5000Z","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},	
+	{ 0x8086, 0x2A10, "Intel GME965/GLE960","",	0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
+	{ 0x8086, 0x2A40, "Intel PM/GM45/47","",		0, poll_fsb_im965, poll_timings_im965, setup_p35, poll_nothing},
+	{ 0x8086, 0x29B0, "Intel Q35","", 	 		 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x29C0, "Intel P35/G33","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x29D0, "Intel Q33","",	  	 			0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x29E0, "Intel X38/X48","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x29F0, "Intel 3200/3210","", 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x2E10, "Intel Q45/Q43","", 	 		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x2E20, "Intel P45/G45","",	  		0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x2E30, "Intel G41","", 	 				0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
+	{ 0x8086, 0x4001, "Intel 5400A","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+	{ 0x8086, 0x4003, "Intel 5400B","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+	{ 0x8086, 0x25D8, "Intel 5000P","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+	{ 0x8086, 0x25D4, "Intel 5000V","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+	{ 0x8086, 0x25C0, "Intel 5000X","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
+	{ 0x8086, 0x25D0, "Intel 5000Z","", 		 		0, poll_fsb_5400, poll_timings_5400, setup_E5400, poll_nothing},
 	{ 0x8086, 0x5020, "Intel EP80579","",    		0, poll_fsb_p4, 	poll_timings_EP80579, setup_nothing, poll_nothing },
 	{ 0x8086, 0x8100, "Intel US15W","",					0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
 	{ 0x8086, 0x8101, "Intel UL11L/US15L","", 	0, poll_fsb_us15w, poll_timings_us15w, setup_nothing, poll_nothing},
@@ -4012,10 +4012,10 @@
 	{ 0xFFFF, 0x0004, "SNB IMC","", 	 				0, poll_fsb_snb, 	poll_timings_snb, setup_wmr, poll_nothing},
 	{ 0xFFFF, 0x0005, "SNB-E IMC","",		 	 		0, poll_fsb_snbe, poll_timings_snbe, setup_wmr, poll_nothing},
 	{ 0xFFFF, 0x0006, "IVB IMC","",			 	 		0, poll_fsb_ivb, 	poll_timings_snb, setup_wmr, poll_nothing},
-	{ 0xFFFF, 0x0007, "HSW IMC","",			 	 		0, poll_fsb_ivb, 	poll_timings_hsw, setup_wmr, poll_nothing},		
+	{ 0xFFFF, 0x0007, "HSW IMC","",			 	 		0, poll_fsb_ivb, 	poll_timings_hsw, setup_wmr, poll_nothing},
 	{ 0xFFFF, 0x0008, "PineView IMC","", 			0, poll_fsb_p35, poll_timings_p35, setup_p35, poll_nothing},
 	{ 0xFFFF, 0x0009, "CedarTrail IMC","",		0, poll_fsb_ct, poll_timings_ct, setup_nothing, poll_nothing},
-	
+
 	/* AMD IMC (Integrated Memory Controllers) */
 	{ 0xFFFF, 0x0100, "AMD K8 IMC","",				0, poll_fsb_amd64, poll_timings_amd64, setup_amd64, poll_nothing },
 	{ 0xFFFF, 0x0101, "AMD K10 IMC","",			  0, poll_fsb_k10, poll_timings_k10, setup_k10, poll_nothing },
@@ -4023,7 +4023,7 @@
 	{ 0xFFFF, 0x0103, "AMD K14 IMC","",				0, poll_fsb_k14, poll_timings_k14, setup_apu, poll_nothing },
 	{ 0xFFFF, 0x0104, "AMD K15 IMC","",				0, poll_fsb_k15, poll_timings_k15, setup_apu, poll_nothing },
 	{ 0xFFFF, 0x0105, "AMD K16 IMC","",				0, poll_fsb_k16, poll_timings_k16, setup_apu, poll_nothing }
-};	
+};
 
 static void print_memory_controller(void)
 {
@@ -4081,9 +4081,9 @@
 		col += 9;
 	}
 	*/
-	
-	
-	
+
+
+
 	/* Print advanced caracteristics  */
 	col2 = 0;
 
@@ -4101,14 +4101,14 @@
 	int result;
 	result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_VENDOR_ID, 2, &vendor);
 	result = pci_conf_read(ctrl.bus, ctrl.dev, ctrl.fn, PCI_DEVICE_ID, 2, &device);
-	
+
 	// Detect IMC by CPUID
 	if(imc_type) { vendor = 0xFFFF; device = imc_type; }
 	if(v->fail_safe & 1) { vendor = 0xFFFF; device = 0xFFFF; }
-		
+
 	//hprint(11,0,vendor); hprint(11,10,device);
-		
-	ctrl.index = 0;	
+
+	ctrl.index = 0;
 		if (result == 0 || imc_type) {
 			for(i = 1; i < sizeof(controllers)/sizeof(controllers[0]); i++) {
 				if ((controllers[i].vendor == vendor) && (controllers[i].device == device)) {
@@ -4117,14 +4117,14 @@
 				}
 			}
 		}
-	
+
 	controllers[ctrl.index].setup_ecc();
 	/* Don't enable ECC polling by default unless it has
 	 * been well tested.
 	 */
 	//set_ecc_polling(-1);
 	print_memory_controller();
-	
+
 	if(imc_type) { print_dmi_startup_info(); }
 
 }
diff --git a/cpuid.c b/cpuid.c
index 4c25ede..088d8f3 100644
--- a/cpuid.c
+++ b/cpuid.c
@@ -29,7 +29,7 @@
 	if(cpu_id.max_cpuid >= 6)	{
 		cpuid(0x00000006, &cpu_id.dts_pmp, &dummy[0], &dummy[1], &dummy[2]);
 	}
-	
+
 	/* Get the max extended cpuid */
 	cpuid(0x80000000, &cpu_id.max_xcpuid, &dummy[0], &dummy[1], &dummy[2]);
 
diff --git a/cpuid.h b/cpuid.h
index caace1e..873d479 100644
--- a/cpuid.h
+++ b/cpuid.h
@@ -1,6 +1,6 @@
 /*
  * cpuid.h --
- *      contains the data structures required for CPUID 
+ *      contains the data structures required for CPUID
  *      implementation.
  */
 
@@ -50,11 +50,11 @@
    struct {
       uint32_t    fill1:24;      /* Bit 0 */
       uint32_t    l1_i_sz:8;
-      uint32_t    fill2:24; 
+      uint32_t    fill2:24;
       uint32_t    l1_d_sz:8;
-      uint32_t    fill3:16; 
+      uint32_t    fill3:16;
       uint32_t    l2_sz:16;
-      uint32_t    fill4:18; 
+      uint32_t    fill4:18;
       uint32_t    l3_sz:14;
       uint32_t    fill5[8];
    } amd;
@@ -86,7 +86,7 @@
       uint32_t    extendedModel:4;
       uint32_t    extendedFamily:8;
       uint32_t    reserved3128:4;  /* Bit 31 */
-   } bits;      
+   } bits;
 } cpuid_version_t;
 
 /* Typedef for storing CPUID Processor Information */
@@ -97,14 +97,14 @@
       uint32_t    cflushLineSize:8;
       uint32_t    logicalProcessorCount:8;
       uint32_t    apicID:8;        /* Bit 31 */
-   } bits;      
+   } bits;
 } cpuid_proc_info_t;
 
 /* Typedef for storing CPUID Feature flags */
 typedef union {
    uint32_t flat;
    struct {
-      uint32_t    :1;           
+      uint32_t    :1;
    } bits;
 } cpuid_custom_features;
 
@@ -150,9 +150,9 @@
       uint32_t    mon:1;
       uint32_t    dscpl:1;
       uint32_t    vmx:1;
-     	uint32_t    smx:1;      	
-     	uint32_t    eist:1;  
-     	uint32_t    tm2:1;       		     		
+     	uint32_t    smx:1;
+     	uint32_t    eist:1;
+     	uint32_t    tm2:1;
       uint32_t    bits_9_31:23;
       uint32_t    bits0_28:29;     /* EDX extended feature flags, bit 0 */
       uint32_t    lm:1;		   /* Long Mode */
diff --git a/defs.h b/defs.h
index 3891699..b69c167 100644
--- a/defs.h
+++ b/defs.h
@@ -3,13 +3,13 @@
  *
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady
- */ 
+ */
 
 #define SETUPSECS	4		/* Number of setup sectors */
 
 /*
  * Caution!! There is magic in the build process.  Read
- * README.build-process before you change anything.  
+ * README.build-process before you change anything.
  * Unlike earlier versions all of the settings are in defs.h
  * so the build process should be more robust.
  */
diff --git a/dmi.c b/dmi.c
index 1f11008..9f781c1 100644
--- a/dmi.c
+++ b/dmi.c
@@ -67,14 +67,14 @@
 	uint16_t l1_handle;
 	uint16_t l2_handle;
 	uint16_t l3_handle;
-	uint8_t	cpu_serial;	
+	uint8_t	cpu_serial;
 	uint8_t	cpu_asset_tag;
 	uint8_t cpu_part_number;
 	uint8_t	core_count;
 	uint8_t	core_enabled;
 	uint8_t	thread_count;
 	uint16_t cpu_specs;
-	uint16_t cpu_family_2;	
+	uint16_t cpu_family_2;
 } __attribute__((packed));
 
 struct mem_dev {
@@ -204,10 +204,10 @@
 //look at all structs
 	while(dmi < table_start + eps->tablelength){
 		struct tstruct_header *header = (struct tstruct_header *)dmi;
-		
+
 		if (header->type == 17)
 			mem_devs[mem_devs_count++] = (struct mem_dev *)dmi;
-		
+
 		// Need fix (SMBIOS/DDR3)
 		if (header->type == 20 || header->type == 1)
 			md_maps[md_maps_count++] = (struct md_map *)dmi;
@@ -223,9 +223,9 @@
 		{
 			dmi_cpu_info = (struct cpu_map *)dmi;
 		}
-			
+
 		dmi+=header->length;
-		
+
 		while( ! (*dmi == 0  && *(dmi+1) == 0 ) )
 			dmi++;
 		dmi+=2;
@@ -252,19 +252,19 @@
 	int dmicol = 78;
 	int slenght;
 	int sl1, sl2, sl3;
-	
+
 	if(!dmi_initialized) { init_dmi(); }
-		
+
 	string1 = get_tstruct_string(&dmi_system_info->header,dmi_system_info->manufacturer);
 	sl1 = strlen(string1);
-	string2 = get_tstruct_string(&dmi_system_info->header,dmi_system_info->productname);	
+	string2 = get_tstruct_string(&dmi_system_info->header,dmi_system_info->productname);
 	sl2 = strlen(string2);
 	string3 = get_tstruct_string(&dmi_cpu_info->header,dmi_cpu_info->cpu_socket);
 	sl3 = strlen(string3);
 
 	slenght = sl1 + sl2;
 	if(sl3 > 2) { slenght += sl3 + 4; } else { slenght++; }
-	
+
 	if(sl1 && sl2)
 		{
 			//dmicol -= slenght; // right align
@@ -273,7 +273,7 @@
 			dmicol += sl1 + 1;
 			cprint(LINE_DMI, dmicol, string2);
 			dmicol += sl2 + 1;
-			
+
 			if(sl3 > 2){
 				cprint(LINE_DMI, dmicol, "(");
 				dmicol++;
@@ -328,9 +328,9 @@
 				itoa(string, size_in_mb);
 				cprint(yof, POP2_X+4+18, string);
 			}
-			
-			//this is the only field that needs to be SMBIOS 2.3+ 
-			if ( mem_devs[i]->speed && 
+
+			//this is the only field that needs to be SMBIOS 2.3+
+			if ( mem_devs[i]->speed &&
 			     mem_devs[i]->header.length > 21){
 				itoa(string, mem_devs[i]->speed);
 				cprint(yof, POP2_X+4+27, string);
@@ -374,14 +374,14 @@
 		while (get_key() == 0);
 	}
 }
-	
+
 //return 1 if the list of bad memory devices changes, 0 otherwise, -1 if no mapped
 int add_dmi_err(ulong adr){
 	int i,j,found=-1;
-	
+
 	if(!dmi_initialized)
 		init_dmi();
-	
+
 	for(i=0; i < md_maps_count; i++){
 		if ( adr < (md_maps[i]->start<<10) ||
 		     adr > (md_maps[i]->end<<10) )
@@ -398,16 +398,16 @@
 			}
 		}
 	}
-	
+
 	return found;
 }
-	
+
 void print_dmi_err(void){
 	int i,count,of;
 	char *string;
-	
+
 	scroll();
-	
+
 	cprint(v->msg_line, 0,"Bad Memory Devices: ");
 	of=20;
 	for ( i=count=0; i < MAX_DMI_MEMDEVS; i++){
diff --git a/error.c b/error.c
index 4218d8c..31e3e4b 100644
--- a/error.c
+++ b/error.c
@@ -33,11 +33,11 @@
  */
 void error(ulong *adr, ulong good, ulong bad)
 {
-	
+
 	ulong xor;
 
 	spin_lock(&barr->mutex);
-	
+
 	xor = good ^ bad;
 
 #ifdef USB_WAR
@@ -54,17 +54,17 @@
 	/* A sporadic bug exists in test #6, with SMP enabled, that
 	 * reports false positives on < 65K-0.5MB range. I was
 	 * not able to solve this. After investigations, it seems
-	 * related to a BIOS issue similiar to the one solved by 
+	 * related to a BIOS issue similiar to the one solved by
 	 * USB_WAR, but for MP Table.
 	 */
-	/* Solved 
-	if (test == 6 && (ulong)adr <= 0x07FFFF && num_cpus > 1) 
+	/* Solved
+	if (test == 6 && (ulong)adr <= 0x07FFFF && num_cpus > 1)
 	{
 	  cprint(6,78,"-"); // Debug
 		return;
 	}
 	*/
-	
+
 	common_err(adr, good, bad, xor, 0);
 	spin_unlock(&barr->mutex);
 }
@@ -101,14 +101,14 @@
 		beep(600);
 		beep(1000);
 	}
-	
+
 	if (v->pass && v->ecount == 0) {
 		cprint(LINE_MSG, COL_MSG,
 			"                                            ");
 	}
 	++(v->ecount);
 	tseq[test].errors++;
-		
+
 }
 
 static void print_err_counts(void)
@@ -124,7 +124,7 @@
 */
 
 	/* Paint the error messages on the screen red to provide a vivid */
-	/* indicator that an error has occured */ 
+	/* indicator that an error has occured */
 	if ((v->printmode == PRINTMODE_ADDRESSES ||
 			v->printmode == PRINTMODE_PATTERNS) &&
 			v->msg_line < 24) {
@@ -138,7 +138,7 @@
 /*
  * Print an individual error
  */
-void common_err( ulong *adr, ulong good, ulong bad, ulong xor, int type) 
+void common_err( ulong *adr, ulong good, ulong bad, ulong xor, int type)
 {
 	int i, j, n, x, flag=0;
 	ulong page, offset;
@@ -171,7 +171,7 @@
 			page = page_of(adr);
 			offset = (ulong)adr & 0xFFF;
 		}
-			
+
 		/* Calc upper and lower error addresses */
 		if (v->erri.low_addr.page > page) {
 			v->erri.low_addr.page = page;
@@ -248,7 +248,7 @@
 			    x += 10;
 			  }
 			}
-			
+
 			cprint(LINE_HEADER+0, 64,   "Test  Errors");
 			v->erri.hdr_flag++;
 		}
@@ -293,7 +293,7 @@
 			}
 			x += 10;
 		  }
-		  			
+
 		  for (i=0; tseq[i].msg != NULL; i++) {
 			dprint(LINE_HEADER+1+i, 66, i, 2, 0);
 			dprint(LINE_HEADER+1+i, 68, tseq[i].errors, 8, 0);
@@ -321,7 +321,7 @@
 		/* Check for keyboard input */
 		check_input();
 		scroll();
-	
+
 		if ( type == 2 || type == 3) {
 			page = (ulong)adr;
 			offset = good;
@@ -340,10 +340,10 @@
 
 		if (type == 3) {
 			/* ECC error */
-			cprint(v->msg_line, 36, 
+			cprint(v->msg_line, 36,
 			  bad?"corrected           ": "uncorrected         ");
 			hprint2(v->msg_line, 60, syn, 4);
-			cprint(v->msg_line, 68, "ECC"); 
+			cprint(v->msg_line, 68, "ECC");
 			dprint(v->msg_line, 74, chan, 2, 0);
 		} else if (type == 2) {
 			cprint(v->msg_line, 36, "Parity error detected                ");
@@ -374,7 +374,7 @@
 		}
 		/* Process the address in the pattern administration */
 		patnchg=insertaddress ((ulong) adr);
-		if (patnchg) { 
+		if (patnchg) {
 			printpatn();
 		}
 		break;
@@ -391,7 +391,7 @@
 /*
  * Print an ecc error
  */
-void print_ecc_err(unsigned long page, unsigned long offset, 
+void print_ecc_err(unsigned long page, unsigned long offset,
 	int corrected, unsigned short syndrome, int channel)
 {
 	++(v->ecc_ecount);
@@ -404,7 +404,7 @@
 /*
  * Print a parity error message
  */
-void parity_err( unsigned long edi, unsigned long esi) 
+void parity_err( unsigned long edi, unsigned long esi)
 {
 	unsigned long addr;
 
@@ -451,7 +451,7 @@
                x+=22;
        }
 }
-	
+
 /*
  * Show progress by displaying elapsed time and update bar graphs
  */
@@ -468,8 +468,8 @@
 		spin_idx[me] = 0;
 	}
 	cplace(8, me+7, spin[spin_idx[me]]);
-	
-	
+
+
 	/* Check for keyboard input */
 	if (me == mstr_cpu) {
 		check_input();
@@ -487,7 +487,7 @@
 	if (v->ecount) {
 		print_err_counts();
 	}
-	
+
 	nticks++;
 	v->total_ticks++;
 
@@ -508,7 +508,7 @@
 		cprint(2, COL_MID+9+v->tptr, "#");
 		v->tptr++;
 	}
-	
+
 	if (v->pass_ticks) {
 		pct = 100*v->total_ticks/v->pass_ticks;
 		if (pct > 100) {
@@ -553,7 +553,7 @@
 				}
 			}
 			pct += n*2;
-			
+
 		}
 
 		/* Only some bits in error */
@@ -577,7 +577,7 @@
 */
 		dprint(LINE_HEADER+0, 25, pct, 3, 1);
 	}
-		
+
 
 	/* We can't do the elapsed time unless the rdtsc instruction
 	 * is supported
@@ -595,10 +595,10 @@
 		t += (l / v->clks_msec) / 1000;
 		i = t % 60;
 		j = i % 10;
-	
+
 		if(j != v->each_sec)
-		{	
-			
+		{
+
 			dprint(LINE_TIME, COL_TIME+9, i % 10, 1, 0);
 			dprint(LINE_TIME, COL_TIME+8, i / 10, 1, 0);
 			t /= 60;
@@ -607,16 +607,16 @@
 			dprint(LINE_TIME, COL_TIME+5, i / 10, 1, 0);
 			t /= 60;
 			dprint(LINE_TIME, COL_TIME, t, 4, 0);
-		
+
 			if(v->check_temp > 0 && !(v->fail_safe & 4))
 				{
-					coretemp();	
-				}	
-			v->each_sec = j;	
+					coretemp();
+				}
+			v->each_sec = j;
 		}
-	
+
 	}
-	
+
 
 
 	/* Poll for ECC errors */
diff --git a/extra.h b/extra.h
index 9bd7045..08a76cc 100644
--- a/extra.h
+++ b/extra.h
@@ -11,7 +11,7 @@
 
 void change_timing(int cas, int rcd, int rp, int ras);
 void find_memctr(void);
-void disclaimer(void); 
+void disclaimer(void);
 void get_option(void);
 void get_menu(void);
 void a64_parameter(void);
diff --git a/head.S b/head.S
index 1fe3d2b..9e33721 100644
--- a/head.S
+++ b/head.S
@@ -265,7 +265,7 @@
 	leal	_dl_start@GOTOFF(%ebx), %eax
 	call	*%eax
 
-	/* Never forget to initialize the FPU ... Never ! */ 
+	/* Never forget to initialize the FPU ... Never ! */
 	finit
 
 	call	test_start
@@ -389,8 +389,8 @@
 	/* original boot_stack pointer */
 	leal	48(%esp), %eax
 	pushl	%eax
-	pushl	%ds  
-	pushl	%ss 
+	pushl	%ds
+	pushl	%ss
 	pushl	%esp /* pointer to trap regs struct on the boot_stack */
 	call	inter
 	addl	$8, %esp
@@ -468,7 +468,7 @@
 # Page Directory Tables:
 # There are 4 tables, the first two map the first 2 GB of memory. The last two are used with # PAE to map
 # the rest of memory in 2 GB segments. The last two tables are changed in vmem.c to map each segment.
-# We use 2 MB pages so only the Page Directory Table is used (no page tables). 
+# We use 2 MB pages so only the Page Directory Table is used (no page tables).
 .balign 4096
 .globl pd0
 pd0:
@@ -853,7 +853,7 @@
 	/* if we ever return, we'll just loop forever */
 	cli
 2:	hlt
-	jmp 2b	
+	jmp 2b
 .data
 zerobss:	.long	1
 .previous
diff --git a/init.c b/init.c
index 900ac9f..c1f44a7 100644
--- a/init.c
+++ b/init.c
@@ -10,7 +10,7 @@
  *
  * Edited by David McInnis October 4, 2014
  */
- 
+
 
 #include "stdin.h"
 #include "stddef.h"
@@ -60,22 +60,22 @@
 	ulong sh, sl, l, h, t;
 	unsigned char c;
 	volatile char *pp;
-	
+
 	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
 		*pp = 0x1E;
-	}	
+	}
 	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<3; i++, pp+=2) {
 		*pp = 0x9E;
-	}	
+	}
 	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(55*2)+1); i<3; i++, pp+=2) {
 		*pp = 0x9E;
-	}	
-	
+	}
+
 	cprint(18, 18, "==> Press F1 to enter Fail-Safe Mode <==");
-	
+
 	if(v->fail_safe & 2)
 	{
-	cprint(19, 15, "==> Press F2 to force Multi-Threading (SMP) <==");				
+	cprint(19, 15, "==> Press F2 to force Multi-Threading (SMP) <==");
 	}
 
 	/* save the starting time */
@@ -98,39 +98,39 @@
 
 		/* Is the time up? */
 		if (t >= msec) { break;	}
-		
+
 		/* Is expected Scan code pressed? */
 		c = get_key();
 		c &= 0x7f;
-		
+
 		/* F1 */
 		if(c == scs) { v->fail_safe |= 1;	break; }
-					
+
 		/* F2 */
-		if(c == scs+1) 
-		{ 
+		if(c == scs+1)
+		{
 			v->fail_safe ^= 2;
 			break;
 
 		}
-		
+
 		/* F3 */
-		if(c == scs+2) 
-		{ 
+		if(c == scs+2)
+		{
 			if(v->fail_safe & 2) { v->fail_safe ^= 2; }
 			v->fail_safe |= 8;
 			break;
-		}				
-			
+		}
+
 	}
-	
+
 	cprint(18, 18, "                                          ");
 	cprint(19, 15, "                                                ");
-	
+
 	for(i=0, pp=(char *)(SCREEN_ADR+(18*160)+(18*2)+1); i<40; i++, pp+=2) {
 		*pp = 0x17;
-	}		
-	
+	}
+
 }
 
 
@@ -139,7 +139,7 @@
 {
 	int i;
 	volatile char *pp;
-	
+
 	/* Set HW cursor out of screen boundaries */
 	__outb(0x0F, 0x03D4);
 	__outb(0xFF, 0x03D5);
@@ -187,7 +187,7 @@
 void init(void)
 {
 	int i;
-	
+
 	outb(0x8, 0x3f2);  /* Kill Floppy Motor */
 
 	/* Turn on cache */
@@ -195,7 +195,7 @@
 
 	/* Setup the display */
 	display_init();
-	
+
 	cprint(5, 60, "| Time:   0:00:00");
 	cprint(1, COL_MID,"Pass   %");
 	cprint(2, COL_MID,"Test   %");
@@ -213,7 +213,7 @@
 	cprint(9, 0, "Cores:    Active /    Total (Run: All) | Pass:       0        Errors:      0  ");
 	cprint(10, 0, "------------------------------------------------------------------------------");
 
-	/*	
+	/*
 	for(i=0, pp=(char *)(SCREEN_ADR+(5*160)+(53*2)+1); i<20; i++, pp+=2) {
 		*pp = 0x92;
 	}
@@ -222,15 +222,15 @@
 		*pp = 0x47;
 	}
 	*/
-	
+
 	cprint(7, 39, "| Chipset : Unknown");
 	cprint(8, 39, "| Memory Type : Unknown");
-	
+
 
 	for(i=0; i < 6; i++) {
 		cprint(i, COL_MID-2, "| ");
 	}
-	
+
 	footer();
 
   aprint(5, 10, v->test_pages);
@@ -265,45 +265,45 @@
 			}
 		}
 	}
-	
+
 	/* setup beep mode */
 	beepmode = BEEP_MODE;
-	
+
 	/* Get the cpu and cache information */
 	get_cpuid();
 
 	/* setup pci */
-	pci_init(); 
+	pci_init();
 
-	get_cache_size(); 
+	get_cache_size();
 
 	cpu_type();
 
 	cpu_cache_speed();
 
-  /* Check fail safe */	
+  /* Check fail safe */
 	failsafe(5000, 0x3B);
 
 	/* Initalize SMP */
 	initialise_cpus();
-	
+
 	for (i = 0; i <num_cpus; i++) {
 		dprint(7, i+7, i%10, 1, 0);
 		cprint(8, i+7, "S");
 	}
 
 	dprint(9, 19, num_cpus, 2, 0);
-	
+
 	if((v->fail_safe & 3) == 2)
 	{
 			cprint(LINE_CPU,9, "(SMP: Disabled)");
 			cprint(LINE_RAM,9, "Running...");
 	}
-	// dprint(10, 5, found_cpus, 2, 0); 
+	// dprint(10, 5, found_cpus, 2, 0);
 
 	/* Find Memory Specs */
-	if(v->fail_safe & 1) 
-		{ 	
+	if(v->fail_safe & 1)
+		{
 			cprint(LINE_CPU, COL_SPEC, " **** FAIL SAFE **** FAIL SAFE **** ");
 			cprint(LINE_RAM, COL_SPEC, "   No detection, same reliability   ");
 		} else {
@@ -311,16 +311,16 @@
 			get_spd_spec();
 			if(num_cpus <= 16 && !(v->fail_safe & 4)) { coretemp(); }
 		}
-	
+
 	if(v->check_temp > 0 && !(v->fail_safe & 4))
 	{
 		cprint(LINE_CPU, 26, "|  CPU Temp");
 		cprint(LINE_CPU+1, 26, "|      øC");
 	}
-	
+
 		beep(600);
 		beep(1000);
-	
+
 	/* Record the start time */
   asm __volatile__ ("rdtsc":"=a" (v->startl),"=d" (v->starth));
   v->snapl = v->startl;
@@ -362,7 +362,7 @@
 
 		   /* figure out how many cache leaves */
 		    n = -1;
-		    do 
+		    do
 		    {
 					++n;
 					/* Do cpuid(4) loop to find out num_cache_leaves */
@@ -370,12 +370,12 @@
 		    } while ((eax->ctype) != 0);
 
 		    /* loop through all of the leaves */
-		    for (i=0; i<n; i++) 
+		    for (i=0; i<n; i++)
 		    {
 					cpuid_count(4, i, &v[0], &v[1], &v[2], &v[3]);
 
 					/* Check for a valid cache type */
-					if (eax->ctype == 1 || eax->ctype == 3) 
+					if (eax->ctype == 1 || eax->ctype == 3)
 					{
 
 			    	/* Compute the cache size */
@@ -385,7 +385,7 @@
                 	          	  (ebx->ways_of_associativity + 1);
 			    	size /= 1024;
 
-				    switch (eax->level) 
+				    switch (eax->level)
 				    {
 					  	case 1:
 								l1_cache += size;
@@ -518,20 +518,20 @@
 			case 0xde:
 			case 0xe4:
 				l3_cache += 8192;
-				break;	
+				break;
 			case 0x4c:
 			case 0xea:
 				l3_cache += 12288;
-				break;	
+				break;
 			case 0x4d:
 				l3_cache += 16384;
-				break;	
+				break;
 			case 0xeb:
 				l3_cache += 18432;
-				break;	
+				break;
 			case 0xec:
 				l3_cache += 24576;
-				break;	
+				break;
 			} /* end switch */
 		    } /* end for 1-16 */
 		} /* end for 0 - n */
@@ -544,7 +544,7 @@
 void detect_imc(void)
 {
 	// Check AMD IMC
-	if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF) 
+	if(cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF)
 		{
 			switch(cpu_id.vers.bits.extendedFamily)
 					{
@@ -560,20 +560,20 @@
 							break;
 						case 0x5:
 							imc_type = 0x0103; // C- / E- / Z- Series APU (Family 14h)
-							break;	
+							break;
 						case 0x6:
 							imc_type = 0x0104; // FX Series (Family 15h)
-							break;								
+							break;
 						case 0x7:
 							imc_type = 0x0105; // Kabini & related (Family 16h)
-							break;			
-					}	
+							break;
+					}
 			return;
 		}
-					
-	// Check Intel IMC	
-	if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.vers.bits.family == 6 && cpu_id.vers.bits.extendedModel) 
-		{					
+
+	// Check Intel IMC
+	if(cpu_id.vend_id.char_array[0] == 'G' && cpu_id.vers.bits.family == 6 && cpu_id.vers.bits.extendedModel)
+		{
 			switch(cpu_id.vers.bits.model)
 			{
 				case 0x5:
@@ -582,7 +582,7 @@
 					if(cpu_id.vers.bits.extendedModel == 4) { imc_type = 0x0007; } // HSW-ULT
 					break;
 				case 0x6:
-					if(cpu_id.vers.bits.extendedModel == 3) { 
+					if(cpu_id.vers.bits.extendedModel == 3) {
 						imc_type = 0x0009;  // Atom Cedar Trail
 						v->fail_safe |= 4; // Disable Core temp
 					}
@@ -595,9 +595,9 @@
 							break;
 						case 0x2:
 							imc_type = 0x0004; // Core 2nd Gen (SNB)
-							break;	
+							break;
 						case 0x3:
-							imc_type = 0x0006; // Core 3nd Gen (IVB)						
+							imc_type = 0x0006; // Core 3nd Gen (IVB)
 							break;
 					}
 					break;
@@ -605,25 +605,25 @@
 					switch(cpu_id.vers.bits.extendedModel)
 					{
 						case 0x1:
-							if(cpu_id.vers.bits.stepping > 9) { imc_type = 0x0008; } // Atom PineView	
+							if(cpu_id.vers.bits.stepping > 9) { imc_type = 0x0008; } // Atom PineView
 							v->fail_safe |= 4; // Disable Core temp
-							break;	
+							break;
 						case 0x2:
-							imc_type = 0x0002; // Core i7 1st Gen 32 nm (WMR)	
-							break;	
+							imc_type = 0x0002; // Core i7 1st Gen 32 nm (WMR)
+							break;
 						case 0x3:
-							imc_type = 0x0007; // Core 4nd Gen (HSW)						
+							imc_type = 0x0007; // Core 4nd Gen (HSW)
 							break;
 					}
-					break;			
+					break;
 				case 0xD:
 					imc_type = 0x0005; // SNB-E
-					break;				
+					break;
 				case 0xE:
 					imc_type = 0x0001; // Core i7 1st Gen 45 nm (NHM)
-					break;				
+					break;
 			}
-		
+
 		if(imc_type) { tsc_invariable = 1; }
 		return;
 		}
@@ -634,16 +634,16 @@
 	int i, result;
 	char *cpupsn = cpu_id.brand_id.char_array;
   char *disabledcpu[] = { "Opteron", "Xeon", "Genuine Intel" };
-  
-  for(i = 0; i < 3; i++) 
+
+  for(i = 0; i < 3; i++)
   {
   	result = strstr(cpupsn , disabledcpu[i]);
   	if(result != -1) { v->fail_safe |= 0b10; }
   }
-  
+
   // For 5.01 release, SMP disabled by defualt by config.h toggle
   if(CONSERVATIVE_SMP) { v->fail_safe |= 0b10; }
-  	
+
 }
 
 /*
@@ -656,11 +656,11 @@
 		cprint(0, COL_MID, cpu_id.brand_id.char_array);
 		//If we have a brand string, maybe we have an IMC. Check that.
 		detect_imc();
-		smp_default_mode();	
+		smp_default_mode();
 		return;
 	}
 
-	/* The brand string is not available so we need to figure out 
+	/* The brand string is not available so we need to figure out
 	 * CPU what we have */
 	switch(cpu_id.vend_id.char_array[0]) {
 	/* AMD Processors */
@@ -708,8 +708,8 @@
 			case 9:
 				cprint(0, COL_MID, "AMD K6-III");
 				break;
-			case 13: 
-				cprint(0, COL_MID, "AMD K6-III+"); 
+			case 13:
+				cprint(0, COL_MID, "AMD K6-III+");
 				break;
 			}
 			break;
@@ -870,7 +870,7 @@
 			case 12:
 				l1_cache = 24;
 				cprint(0, COL_MID, "Atom (0.045)");
-				break;					
+				break;
 			case 13:
 				if (l2_cache == 1024) {
 					cprint(0, COL_MID, "Celeron M (0.09)");
@@ -880,7 +880,7 @@
 				break;
 			case 14:
 				cprint(0, COL_MID, "Intel Core");
-				break;				
+				break;
 			case 15:
 				if (l2_cache == 1024) {
 					cprint(0, COL_MID, "Pentium E");
@@ -893,7 +893,7 @@
 		case 15:
 			switch(cpu_id.vers.bits.model) {
 			case 0:
-			case 1:			
+			case 1:
 			case 2:
 				if (l2_cache == 128) {
 					cprint(0, COL_MID, "Celeron");
@@ -1066,14 +1066,14 @@
 	/* We measure the L3 cache speed by using a block size that is */
 	/* 2X the size of the L2 cache. */
 
-	if (l3_cache) 
+	if (l3_cache)
 	{
 		cprint(4, 0, "L3 Cache:     K  ");
    	aprint(4, 10, l3_cache/4);
     //dprint(4, 10, l3_cache, 4, 0);
-    
+
     		i = l2_cache*2;
-    
+
     		if ((speed=memspeed(STEST_ADDR, i*1024, 150))) {
     			cprint(4, 16, "       MB/s");
     			dprint(4, 16, speed, 6, 0);
@@ -1088,7 +1088,7 @@
 	int i;
 	ulong speed=0;
 
-   /* Determine memory speed.  To find the memory speed we use 
+   /* Determine memory speed.  To find the memory speed we use
    * A block size that is the sum of all the L1, L2 & L3 caches
 	 * in all cpus * 6 */
    i = (l3_cache + l2_cache + l1_cache) * 4;
@@ -1098,11 +1098,11 @@
 	if ((1 + (i * 2)) > (v->plim_upper << 2)) {
 		i = ((v->plim_upper <<2) - 1) / 2;
 	}
-	
+
 	speed = memspeed(STEST_ADDR, i * 1024, 100);
 	cprint(5, 16, "       MB/s");
 	dprint(5, 16, speed, 6, 0);
-	
+
 }
 
 /* #define TICKS 5 * 11832 (count = 6376)*/
@@ -1122,7 +1122,7 @@
 
 	/* Setup timer */
 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
-	outb(0xb0, 0x43); 
+	outb(0xb0, 0x43);
 	outb(TICKS & 0xff, 0x42);
 	outb(TICKS >> 8, 0x42);
 
@@ -1271,20 +1271,20 @@
 {
 	float coef_now, coef_max;
 	int msr_lo, msr_hi, is_xe;
-	
+
 	rdmsr(0x198, msr_lo, msr_hi);
-	is_xe = (msr_lo >> 31) & 0x1;		
-	
+	is_xe = (msr_lo >> 31) & 0x1;
+
 	if(is_xe){
 		rdmsr(0x198, msr_lo, msr_hi);
-		coef_max = ((msr_hi >> 8) & 0x1F);	
+		coef_max = ((msr_hi >> 8) & 0x1F);
 		if ((msr_hi >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
 	} else {
 		rdmsr(0x17, msr_lo, msr_hi);
 		coef_max = ((msr_lo >> 8) & 0x1F);
 		if ((msr_lo >> 14) & 0x1) { coef_max = coef_max + 0.5f; }
 	}
-	
+
 	if(cpu_id.fid.bits.eist) {
 		rdmsr(0x198, msr_lo, msr_hi);
 		coef_now = ((msr_lo >> 8) & 0x1F);
diff --git a/jedec_id.h b/jedec_id.h
index b670f96..50ba9f4 100644
--- a/jedec_id.h
+++ b/jedec_id.h
@@ -1,986 +1,986 @@
-/* MemTest86+ V5 Specific code (GPL V2.0)

- * By Samuel DEMEULEMEESTER, sdemeule@memtest.org

- * http://www.canardpc.com - http://www.memtest.org

- * ------------------------------------------------

- * Based on JEDEC JEP106-AG - January 2012

- * All mo

- */

-

-struct spd_jedec_manufacturer {

-    unsigned cont_code;

-    unsigned hex_byte;

-    char *name;

-};

-

-static struct spd_jedec_manufacturer jep106[] = {

-	 { 0, 0x01, "AMD"},

-	 { 0, 0x02, "AMI"},

-   { 0, 0x83, "Fairchild"},

-	 { 0, 0x04, "Fujitsu"},

-// { 0, 0x85, "GTE"},

-   { 0, 0x86, "Harris"},

-	 { 0, 0x07, "Hitachi"},

-   { 0, 0x08, "Inmos"},

-	 { 0, 0x89, "Intel"},

-   { 0, 0x8a, "I.T.T."},

-	 { 0, 0x0b, "Intersil"},

-   { 0, 0x8c, "Monolithic Memories"},

-	 { 0, 0x0d, "Mostek"},

-	 { 0, 0x0e, "Freescale"},

-	 { 0, 0x8f, "National"},

-	 { 0, 0x10, "NEC"},

-   { 0, 0x91, "RCA"},

-	 { 0, 0x92, "Raytheon"},

-	 { 0, 0x13, "Conexant"},

-// { 0, 0x94, "Seeq"},

-	 { 0, 0x15, "NXP"},

-   { 0, 0x16, "Synertek"},

-	 { 0, 0x97, "Texas Instruments"},

-	 { 0, 0x98, "Toshiba"},

-   { 0, 0x19, "Xicor"},

-   { 0, 0x1a, "Zilog"},

-// { 0, 0x9b, "Eurotechnique"},

-	 { 0, 0x1c, "Mitsubishi"},

-   { 0, 0x9d, "Lucent (AT&T)"},

-// { 0, 0x9e, "Exel"},

-	 { 0, 0x1f, "Atmel"},

-   { 0, 0x20, "SGS/Thomson"},

-// { 0, 0xa1, "Lattice Semi."},

-   { 0, 0xa2, "NCR"},

-// { 0, 0x23, "Wafer Scale Integration"},

-	 { 0, 0xa4, "IBM"},

-   { 0, 0x25, "Tristar"},

-// { 0, 0x26, "Visic"},

-	 { 0, 0xa7, "Intl. CMOS Technology"},

-// { 0, 0xa8, "SSSI"},

-	 { 0, 0x29, "MicrochipTechnology"},

-// { 0, 0x2a, "Ricoh"},

-// { 0, 0xab, "VLSI"},

-	 { 0, 0x2c, "Micron"},

-	 { 0, 0xad, "Hynix"},

-	 { 0, 0xae, "OKI Semiconductor"},

-// { 0, 0x2f, "ACTEL"},

-   { 0, 0xb0, "Sharp"},

-   { 0, 0x31, "Catalyst"},

-	 { 0, 0x32, "Panasonic"},

-	 { 0, 0xb3, "IDT"},

-   { 0, 0x34, "Cypress"},

-   { 0, 0xb5, "DEC"},

-   { 0, 0xb6, "LSI Logic"},

-// { 0, 0x37, "Zarlink (Plessey)"},

-   { 0, 0x38, "UTMC"},

-// { 0, 0xb9, "Thinking Machine"},

-   { 0, 0xba, "Thomson CSF"},

-// { 0, 0x3b, "Integrated CMOS (Vertex)"},

-// { 0, 0xbc, "Honeywell"},

-	 { 0, 0x3d, "Tektronix"},

-// { 0, 0x3e, "Oracle"},

-// { 0, 0xbf, "Silicon Storage Technology"},

-	 { 0, 0x40, "ProMos/Mosel"},

-	 { 0, 0xc1, "Infineon"},

-// { 0, 0xc2, "Macronix"},

-   { 0, 0x43, "Xerox"},

-// { 0, 0xc4, "Plus Logic"},

-	 { 0, 0x45, "SanDisk"},

-// { 0, 0x46, "Elan Circuit Tech."},

-// { 0, 0xc7, "European Silicon Str."},

-	 { 0, 0xc8, "Apple Computer"},

-	 { 0, 0x49, "Xilinx"},

-	 { 0, 0x4a, "Compaq"},

-// { 0, 0xcb, "Protocol Engines"},

-// { 0, 0x4c, "SCI"},

-	 { 0, 0xcd, "Seiko Instruments"},

-	 { 0, 0xce, "Samsung"},

-// { 0, 0x4f, "I3 Design System"},

-// { 0, 0xd0, "Klic"},

-// { 0, 0x51, "Crosspoint Solutions"},

-// { 0, 0x52, "Alliance Semiconductor"},

-// { 0, 0xd3, "Tandem"},

-	 { 0, 0x54, "Hewlett-Packard"},

-	 { 0, 0xd5, "Integrated Silicon Solutions"},

-// { 0, 0xd6, "Brooktree"},

-// { 0, 0x57, "New Media"},

-// { 0, 0x58, "MHS Electronic"},

-// { 0, 0xd9, "Performance Semi."},

-	 { 0, 0xda, "Winbond Electronic"},

-// { 0, 0x5b, "Kawasaki Steel"},

-// { 0, 0xdc, "Bright Micro"},

-// { 0, 0x5d, "TECMAR"},

-	 { 0, 0x5e, "Exar"},

-// { 0, 0xdf, "PCMCIA"},

-	 { 0, 0xe0, "LG"},

-// { 0, 0x61, "Northern Telecom"},

-	 { 0, 0x62, "Sanyo"},

-// { 0, 0xe3, "Array Microsystems"},

-// { 0, 0x64, "Crystal Semiconductor"},

-	 { 0, 0xe5, "Analog Devices"},

-// { 0, 0xe6, "PMC-Sierra"},

-// { 0, 0x67, "Asparix"},

-// { 0, 0x68, "Convex Computer"},

-// { 0, 0xe9, "Quality Semiconductor"},

-// { 0, 0xea, "Nimbus Technology"},

-// { 0, 0x6b, "Transwitch"},

-// { 0, 0xec, "Micronas (ITT Intermetall)"},

-   { 0, 0x6d, "Cannon"},

-// { 0, 0x6e, "Altera"},

-// { 0, 0xef, "NEXCOM"},

-// { 0, 0x70, "QUALCOMM"},

-	 { 0, 0xf1, "Sony"},

-// { 0, 0xf2, "Cray Research"},

-// { 0, 0x73, "AMS(Austria Micro)"},

-// { 0, 0xf4, "Vitesse"},

-// { 0, 0x75, "Aster Electronics"},

-// { 0, 0x76, "Bay Networks (Synoptic)"},

-// { 0, 0xf7, "Zentrum/ZMD"},

-// { 0, 0xf8, "TRW"},

-// { 0, 0x79, "Thesys"},

-// { 0, 0x7a, "Solbourne Computer"},

-   { 0, 0xfb, "Allied-Signal"},

-   { 0, 0x7c, "Dialog"},

-   { 0, 0xfd, "Media Vision"},

-// { 0, 0xfe, "Numonyx"},

-	 { 1, 0x01, "Cirrus Logic"},

-   { 1, 0x02, "National Instruments"},

-// { 1, 0x83, "ILC Data Device"},

-// { 1, 0x04, "Alcatel Mietec"},

-// { 1, 0x85, "Micro Linear"},

-// { 1, 0x86, "Univ. of NC"},

-// { 1, 0x07, "JTAG Technologies"},

-// { 1, 0x08, "BAE Systems (Loral)"},

-// { 1, 0x89, "Nchip"},

-// { 1, 0x8a, "Galileo Tech"},

-// { 1, 0x0b, "Bestlink Systems"},

-// { 1, 0x8c, "Graychip"},

-// { 1, 0x0d, "GENNUM"},

-// { 1, 0x0e, "VideoLogic"},

-// { 1, 0x8f, "Robert Bosch"},

-// { 1, 0x10, "Chip Express"},

-   { 1, 0x91, "DATARAM"},

-// { 1, 0x92, "United Microelectronics Corp."},

-// { 1, 0x13, "TCSI"},

-   { 1, 0x94, "Smart Modular"},

-// { 1, 0x15, "Hughes Aircraft"},

-// { 1, 0x16, "Lanstar Semiconductor"},

-// { 1, 0x97, "Qlogic"},

-	 { 1, 0x98, "Kingston"},

-// { 1, 0x19, "Music Semi"},

-// { 1, 0x1a, "Ericsson Components"},

-// { 1, 0x9b, "SpaSE"},

-// { 1, 0x1c, "Eon Silicon Devices"},

-// { 1, 0x9d, "Programmable Micro Corp"},

-// { 1, 0x9e, "DoD"},

-// { 1, 0x1f, "Integ. Memories Tech."},

-// { 1, 0x20, "Corollary"},

-// { 1, 0xa1, "Dallas Semiconductor"},

-// { 1, 0xa2, "Omnivision"},

-// { 1, 0x23, "EIV(Switzerland)"},

-// { 1, 0xa4, "Novatel Wireless"},

-// { 1, 0x25, "Zarlink (Mitel)"},

-// { 1, 0x26, "Clearpoint"},

-// { 1, 0xa7, "Cabletron"},

-// { 1, 0xa8, "STEC (Silicon Tech)"},

-// { 1, 0x29, "Vanguard"},

-// { 1, 0x2a, "Hagiwara Sys-Com"},

-// { 1, 0xab, "Vantis"},

-// { 1, 0x2c, "Celestica"},

-// { 1, 0xad, "Century"},

-// { 1, 0xae, "Hal Computers"},

-// { 1, 0x2f, "Rohm Company"},

-// { 1, 0xb0, "Juniper Networks"},

-// { 1, 0x31, "Libit Signal Processing"},

-	 { 1, 0x32, "Mushkin"},

-// { 1, 0xb3, "Tundra Semiconductor"},

-	 { 1, 0x34, "Adaptec"},

-// { 1, 0xb5, "LightSpeed Semi."},

-// { 1, 0xb6, "ZSP Corp."},

-// { 1, 0x37, "AMIC Technology"},

-// { 1, 0x38, "Adobe Systems"},

-// { 1, 0xb9, "Dynachip"},

-   { 1, 0xba, "PNY"},

-// { 1, 0x3b, "Newport Digital"},

-// { 1, 0xbc, "MMC Networks"},

-// { 1, 0x3d, "T Square"},

-// { 1, 0x3e, "Seiko Epson"},

-// { 1, 0xbf, "Broadcom"},

-// { 1, 0x40, "Viking Components"},

-// { 1, 0xc1, "V3 Semiconductor"},

-// { 1, 0xc2, "Flextronics (Orbit Semiconductor)"},

-// { 1, 0x43, "Suwa Electronics"},

-	 { 1, 0xc4, "Transmeta"},

-	 { 1, 0x45, "Micron CMS"},

-// { 1, 0x46, "American Computer & Digital Components"},

-// { 1, 0xc7, "Enhance 3000"},

-	 { 1, 0xc8, "Tower Semiconductor"},

-// { 1, 0x49, "CPU Design"},

-// { 1, 0x4a, "Price Point"},

-	 { 1, 0xcb, "Maxim Integrated Product"},

-// { 1, 0x4c, "Tellabs"},

-// { 1, 0xcd, "Centaur Technology"},

-   { 1, 0xce, "Unigen"},

-	 { 1, 0x4f, "Transcend"},

-   { 1, 0xd0, "Memory Card"},

-// { 1, 0x51, "CKD"},

-// { 1, 0x52, "Capital Instruments"},

-// { 1, 0xd3, "Aica Kogyo"},

-// { 1, 0x54, "Linvex Technology"},

-   { 1, 0xd5, "MSC"},

-// { 1, 0xd6, "AKM Company"},

-// { 1, 0x57, "Dynamem"},

-// { 1, 0x58, "NERA ASA"},

-// { 1, 0xd9, "GSI Technology"},

-	 { 1, 0xda, "Dane-Elec"},

-// { 1, 0x5b, "Acorn Computers"},

-// { 1, 0xdc, "Lara Technology"},

-// { 1, 0x5d, "Oak Technology"},

-   { 1, 0x5e, "Itec Memory"},

-// { 1, 0xdf, "Tanisys Technology"},

-// { 1, 0xe0, "Truevision"},

-   { 1, 0x61, "Wintec"},

-// { 1, 0x62, "Super PC Memory"},

-// { 1, 0xe3, "MGV Memory"},

-// { 1, 0x64, "Galvantech"},

-// { 1, 0xe5, "Gadzoox Networks"},

-// { 1, 0xe6, "Multi Dimensional Cons."},

-// { 1, 0x67, "GateField"},

-	 { 1, 0x68, "Integrated Memory System"},

-// { 1, 0xe9, "Triscend"},

-// { 1, 0xea, "XaQti"},

-// { 1, 0x6b, "Goldenram"},

-// { 1, 0xec, "Clear Logic"},

-// { 1, 0x6d, "Cimaron Communications"},

-// { 1, 0x6e, "Nippon Steel Semi. Corp."},

-// { 1, 0xef, "Advantage Memory"},

-// { 1, 0x70, "AMCC"},

-	 { 1, 0xf1, "LeCroy"},

-// { 1, 0xf2, "Yamaha"},

-// { 1, 0x73, "Digital Microwave"},

-// { 1, 0xf4, "NetLogic Microsystems"},

-// { 1, 0x75, "MIMOS Semiconductor"},

-// { 1, 0x76, "Advanced Fibre"},

-// { 1, 0xf7, "BF Goodrich Data."},

-// { 1, 0xf8, "Epigram"},

-// { 1, 0x79, "Acbel Polytech"},

-	 { 1, 0x7a, "Apacer Technology"},

-// { 1, 0xfb, "Admor Memory"},

-	 { 1, 0x7c, "FOXCONN"},

-// { 1, 0xfd, "Quadratics Superconductor"},

-// { 1, 0xfe, "3COM"},

-// { 2, 0x01, "Camintonn"},

-// { 2, 0x02, "ISOA"},

-// { 2, 0x83, "Agate Semiconductor"},

-// { 2, 0x04, "ADMtek"},

-// { 2, 0x85, "HYPERTEC"},

-// { 2, 0x86, "Adhoc Technologies"},

-// { 2, 0x07, "MOSAID Technologies"},

-// { 2, 0x08, "Ardent Technologies"},

-// { 2, 0x89, "Switchcore"},

-// { 2, 0x8a, "Cisco Systems"},

-// { 2, 0x0b, "Allayer Technologies"},

-// { 2, 0x8c, "WorkX AG (Wichman)"},

-// { 2, 0x0d, "Oasis Semiconductor"},

-// { 2, 0x0e, "Novanet Semiconductor"},

-// { 2, 0x8f, "E-M Solutions"},

-// { 2, 0x10, "Power General"},

-// { 2, 0x91, "Advanced Hardware Arch."},

-// { 2, 0x92, "Inova Semiconductors"},

-// { 2, 0x13, "Telocity"},

-// { 2, 0x94, "Delkin Devices"},

-// { 2, 0x15, "Symagery Microsystems"},

-// { 2, 0x16, "C-Port"},

-// { 2, 0x97, "SiberCore Technologies"},

-// { 2, 0x98, "Southland Microsystems"},

-// { 2, 0x19, "Malleable Technologies"},

-// { 2, 0x1a, "Kendin Communications"},

-// { 2, 0x9b, "Great Technology Microcomputer"},

-// { 2, 0x1c, "Sanmina"},

-// { 2, 0x9d, "HADCO"},

-	 { 2, 0x9e, "Corsair"},

-// { 2, 0x1f, "Actrans System"},

-// { 2, 0x20, "ALPHA Technologies"},

-// { 2, 0xa1, "Silicon Laboratories (Cygnal)"},

-// { 2, 0xa2, "Artesyn Technologies"},

-// { 2, 0x23, "Align Manufacturing"},

-// { 2, 0xa4, "Peregrine Semiconductor"},

-// { 2, 0x25, "Chameleon Systems"},

-// { 2, 0x26, "Aplus Flash Technology"},

-   { 2, 0xa7, "MIPS Technologies"},

-// { 2, 0xa8, "Chrysalis ITS"},

-// { 2, 0x29, "ADTEC"},

-   { 2, 0x2a, "Kentron Technologies"},

-// { 2, 0xab, "Win Technologies"},

-// { 2, 0x2c, "Tachyon Semiconductor (ASIC)"},

-// { 2, 0xad, "Extreme Packet Devices"},

-// { 2, 0xae, "RF Micro Devices"},

-   { 2, 0x2f, "Siemens AG"},

-// { 2, 0xb0, "Sarnoff"},

-// { 2, 0x31, "Itautec SA"},

-// { 2, 0x32, "Radiata"},

-// { 2, 0xb3, "Benchmark Elect. (AVEX)"},

-// { 2, 0x34, "Legend"},

-   { 2, 0xb5, "SpecTek"},

-// { 2, 0xb6, "Hi/fn"},

-// { 2, 0x37, "Enikia"},

-// { 2, 0x38, "SwitchOn Networks"},

-// { 2, 0xb9, "AANetcom"},

-// { 2, 0xba, "Micro Memory Bank"},

-   { 2, 0x3b, "ESS Technology"},

-// { 2, 0xbc, "Virata"},

-// { 2, 0x3d, "Excess Bandwidth"},

-// { 2, 0x3e, "West Bay Semiconductor"},

-// { 2, 0xbf, "DSP Group"},

-// { 2, 0x40, "Newport Communications"},

-// { 2, 0xc1, "Chip2Chip"},

-// { 2, 0xc2, "Phobos"},

-// { 2, 0x43, "Intellitech"},

-// { 2, 0xc4, "Nordic VLSI ASA"},

-// { 2, 0x45, "Ishoni Networks"},

-// { 2, 0x46, "Silicon Spice"},

-// { 2, 0xc7, "Alchemy Semiconductor"},

-   { 2, 0xc8, "Agilent Technologies"},

-// { 2, 0x49, "Centillium Communications"},

-// { 2, 0x4a, "W.L. Gore"},

-// { 2, 0xcb, "HanBit Electronics"},

-// { 2, 0x4c, "GlobeSpan"},

-// { 2, 0xcd, "Element 14"},

-// { 2, 0xce, "Pycon"},

-// { 2, 0x4f, "Saifun Semiconductors"},

-// { 2, 0xd0, "Sibyte,"},

-// { 2, 0x51, "MetaLink Technologies"},

-// { 2, 0x52, "Feiya Technology"},

-// { 2, 0xd3, "I & C Technology"},

-// { 2, 0x54, "Shikatronics"},

-// { 2, 0xd5, "Elektrobit"},

-// { 2, 0xd6, "Megic"},

-// { 2, 0x57, "Com-Tier"},

-// { 2, 0x58, "Malaysia Micro Solutions"},

-// { 2, 0xd9, "Hyperchip"},

-// { 2, 0xda, "Gemstone Communications"},

-// { 2, 0x5b, "Anadigm (Anadyne)"},

-// { 2, 0xdc, "3ParData"},

-// { 2, 0x5d, "Mellanox Technologies"},

-// { 2, 0x5e, "Tenx Technologies"},

-// { 2, 0xdf, "Helix AG"},

-// { 2, 0xe0, "Domosys"},

-// { 2, 0x61, "Skyup Technology"},

-// { 2, 0x62, "HiNT"},

-// { 2, 0xe3, "Chiaro"},

-   { 2, 0x64, "MDT"},

-// { 2, 0xe5, "Exbit Technology A/S"},

-// { 2, 0xe6, "Integrated Technology Express"},

-// { 2, 0x67, "AVED Memory"},

-// { 2, 0x68, "Legerity"},

-// { 2, 0xe9, "Jasmine Networks"},

-// { 2, 0xea, "Caspian Networks"},

-// { 2, 0x6b, "nCUBE"},

-// { 2, 0xec, "Silicon Access Networks"},

-// { 2, 0x6d, "FDK"},

-// { 2, 0x6e, "High Bandwidth Access"},

-// { 2, 0xef, "MultiLink Technology"},

-// { 2, 0x70, "BRECIS"},

-// { 2, 0xf1, "World Wide Packets"},

-// { 2, 0xf2, "APW"},

-// { 2, 0x73, "Chicory Systems"},

-// { 2, 0xf4, "Xstream Logic"},

-// { 2, 0x75, "Fast-Chip"},

-// { 2, 0x76, "Zucotto Wireless"},

-// { 2, 0xf7, "Realchip"},

-// { 2, 0xf8, "Galaxy Power"},

-// { 2, 0x79, "eSilicon"},

-// { 2, 0x7a, "Morphics Technology"},

-// { 2, 0xfb, "Accelerant Networks"},

-// { 2, 0x7c, "Silicon Wave"},

-// { 2, 0xfd, "SandCraft"},

-   { 2, 0xfe, "Elpida"},

-// { 3, 0x01, "Solectron"},

-   { 3, 0x02, "Optosys Technologies"},

-   { 3, 0x83, "Buffalo"},

-// { 3, 0x04, "TriMedia Technologies"},

-// { 3, 0x85, "Cyan Technologies"},

-// { 3, 0x86, "Global Locate"},

-// { 3, 0x07, "Optillion"},

-// { 3, 0x08, "Terago Communications"},

-// { 3, 0x89, "Ikanos Communications"},

-   { 3, 0x8a, "Princeton"},

-   { 3, 0x0b, "Nanya"},

-// { 3, 0x8c, "Elite Flash Storage"},

-// { 3, 0x0d, "Mysticom"},

-// { 3, 0x0e, "LightSand Communications"},

-   { 3, 0x8f, "ATI"},

-// { 3, 0x10, "Agere Systems"},

-// { 3, 0x91, "NeoMagic"},

-// { 3, 0x92, "AuroraNetics"},

-// { 3, 0x13, "Golden Empire"},

-   { 3, 0x94, "Mushkin"},

-// { 3, 0x15, "Tioga Technologies"},

-   { 3, 0x16, "Netlist"},

-// { 3, 0x97, "TeraLogic"},

-// { 3, 0x98, "Cicada Semiconductor"},

-   { 3, 0x19, "Centon"},

-   { 3, 0x1a, "Tyco Electronics"},

-// { 3, 0x9b, "Magis Works"},

-// { 3, 0x1c, "Zettacom"},

-// { 3, 0x9d, "Cogency Semiconductor"},

-// { 3, 0x9e, "Chipcon AS"},

-// { 3, 0x1f, "Aspex Technology"},

-// { 3, 0x20, "F5 Networks"},

-// { 3, 0xa1, "Programmable Silicon Solutions"},

-// { 3, 0xa2, "ChipWrights"},

-// { 3, 0x23, "Acorn Networks"},

-// { 3, 0xa4, "Quicklogic"},

-   { 3, 0x25, "Kingmax"},

-// { 3, 0x26, "BOPS"},

-// { 3, 0xa7, "Flasys"},

-// { 3, 0xa8, "BitBlitz Communications"},

-   { 3, 0x29, "eMemory Technology"},

-// { 3, 0x2a, "Procket Networks"},

-// { 3, 0xab, "Purple Ray"},

-// { 3, 0x2c, "Trebia Networks"},

-// { 3, 0xad, "Delta Electronics"},

-// { 3, 0xae, "Onex Communications"},

-// { 3, 0x2f, "Ample Communications"},

-   { 3, 0xb0, "Memory Experts"},

-// { 3, 0x31, "Astute Networks"},

-// { 3, 0x32, "Azanda Network Devices"},

-// { 3, 0xb3, "Dibcom"},

-// { 3, 0x34, "Tekmos"},

-// { 3, 0xb5, "API NetWorks"},

-// { 3, 0xb6, "Bay Microsystems"},

-// { 3, 0x37, "Firecron"},

-// { 3, 0x38, "Resonext Communications"},

-// { 3, 0xb9, "Tachys Technologies"},

-// { 3, 0xba, "Equator Technology"},

-// { 3, 0x3b, "Concept Computer"},

-// { 3, 0xbc, "SILCOM"},

-// { 3, 0x3d, "3Dlabs"},

-// { 3, 0x3e, "c’t Magazine"},

-// { 3, 0xbf, "Sanera Systems"},

-// { 3, 0x40, "Silicon Packets"},

-   { 3, 0xc1, "Viasystems Group"},

-   { 3, 0xc2, "Simtek"},

-// { 3, 0x43, "Semicon Devices Singapore"},

-// { 3, 0xc4, "Satron Handelsges"},

-// { 3, 0x45, "Improv Systems"},

-// { 3, 0x46, "INDUSYS"},

-// { 3, 0xc7, "Corrent"},

-// { 3, 0xc8, "Infrant Technologies"},

-// { 3, 0x49, "Ritek Corp"},

-// { 3, 0x4a, "empowerTel Networks"},

-// { 3, 0xcb, "Hypertec"},

-// { 3, 0x4c, "Cavium Networks"},

-   { 3, 0xcd, "PLX Technology"},

-// { 3, 0xce, "Massana Design"},

-// { 3, 0x4f, "Intrinsity"},

-// { 3, 0xd0, "Valence Semiconductor"},

-// { 3, 0x51, "Terawave Communications"},

-// { 3, 0x52, "IceFyre Semiconductor"},

-// { 3, 0xd3, "Primarion"},

-// { 3, 0x54, "Picochip Designs"},

-// { 3, 0xd5, "Silverback Systems"},

-   { 3, 0xd6, "Jade Star"},

-// { 3, 0x57, "Pijnenburg Securealink"},

-   { 3, 0x58, "takeMS"},

-// { 3, 0xd9, "Cambridge Silicon Radio"},

-   { 3, 0xda, "Swissbit"},

-// { 3, 0x5b, "Nazomi Communications"},

-// { 3, 0xdc, "eWave System"},

-// { 3, 0x5d, "Rockwell Collins"},

-// { 3, 0x5e, "Picocel (Paion)"},

-// { 3, 0xdf, "Alphamosaic"},

-// { 3, 0xe0, "Sandburst"},

-// { 3, 0x61, "SiCon Video"},

-// { 3, 0x62, "NanoAmp Solutions"},

-// { 3, 0xe3, "Ericsson Technology"},

-// { 3, 0x64, "PrairieComm"},

-   { 3, 0xe5, "Mitac International"},

-// { 3, 0xe6, "Layer N Networks"},

-// { 3, 0x67, "MtekVision (Atsana)"},

-// { 3, 0x68, "Allegro Networks"},

-// { 3, 0xe9, "Marvell Semiconductors"},

-// { 3, 0xea, "Netergy Microelectronic"},

-   { 3, 0x6b, "nVidia"},

-// { 3, 0xec, "Internet Machines"},

-// { 3, 0x6d, "Peak Electronics"},

-// { 3, 0x6e, "Litchfield Communication"},

-   { 3, 0xef, "Accton"},

-// { 3, 0x70, "Teradiant Networks"},

-// { 3, 0xf1, "Scaleo Chip"},

-// { 3, 0xf2, "Cortina Systems"},

-   { 3, 0x73, "RAM Components"},

-// { 3, 0xf4, "Raqia Networks"},

-// { 3, 0x75, "ClearSpeed"},

-// { 3, 0x76, "Matsushita Battery"},

-// { 3, 0xf7, "Xelerated"},

-// { 3, 0xf8, "SimpleTech"},

-   { 3, 0x79, "Utron"},

-// { 3, 0x7a, "Astec International"},

-// { 3, 0xfb, "AVM"},

-// { 3, 0x7c, "Redux Communications"},

-// { 3, 0xfd, "Dot Hill Systems"},

-   { 3, 0xfe, "TeraChip"},

-   { 4, 0x01, "T-RAM"},

-// { 4, 0x02, "Innovics Wireless"},

-// { 4, 0x83, "Teknovus"},

-// { 4, 0x04, "KeyEye Communications"},

-// { 4, 0x85, "Runcom Technologies"},

-// { 4, 0x86, "RedSwitch"},

-// { 4, 0x07, "Dotcast"},

-   { 4, 0x08, "Silicon Mountain Memory"},

-// { 4, 0x89, "Signia Technologies"},

-// { 4, 0x8a, "Pixim"},

-// { 4, 0x0b, "Galazar Networks"},

-// { 4, 0x8c, "White Electronic Designs"},

-// { 4, 0x0d, "Patriot Scientific"},

-// { 4, 0x0e, "Neoaxiom"},

-// { 4, 0x8f, "3Y Power Technology"},

-   { 4, 0x10, "Scaleo Chip"},

-// { 4, 0x91, "Potentia Power Systems"},

-// { 4, 0x92, "C-guys"},

-// { 4, 0x13, "Digital Communications Technology"},

-// { 4, 0x94, "Silicon-Based Technology"},

-// { 4, 0x15, "Fulcrum Microsystems"},

-// { 4, 0x16, "Positivo Informatica"},

-// { 4, 0x97, "XIOtech"},

-// { 4, 0x98, "PortalPlayer"},

-// { 4, 0x19, "Zhiying Software"},

-// { 4, 0x1a, "ParkerVision"},

-// { 4, 0x9b, "Phonex Broadband"},

-// { 4, 0x1c, "Skyworks Solutions"},

-// { 4, 0x9d, "Entropic Communications"},

-// { 4, 0x9e, "Pacific Force Technology"},

-// { 4, 0x1f, "Zensys A/S"},

-// { 4, 0x20, "Legend Silicon Corp."},

-// { 4, 0xa1, "Sci-worx"},

-// { 4, 0xa2, "SMSC (Standard Microsystems)"},

-   { 4, 0x23, "Renesas"},

-// { 4, 0xa4, "Raza Microelectronics"},

-// { 4, 0x25, "Phyworks"},

-// { 4, 0x26, "MediaTek"},

-// { 4, 0xa7, "Non-cents Productions"},

-// { 4, 0xa8, "US Modular"},

-// { 4, 0x29, "Wintegra"},

-// { 4, 0x2a, "Mathstar"},

-// { 4, 0xab, "StarCore"},

-// { 4, 0x2c, "Oplus Technologies"},

-// { 4, 0xad, "Mindspeed"},

-// { 4, 0xae, "Just Young Computer"},

-// { 4, 0x2f, "Radia Communications"},

-   { 4, 0xb0, "OCZ"},

-// { 4, 0x31, "Emuzed"},

-// { 4, 0x32, "LOGIC Devices"},

-// { 4, 0xb3, "Inphi"},

-// { 4, 0x34, "Quake Technologies"},

-// { 4, 0xb5, "Vixel"},

-// { 4, 0xb6, "SolusTek"},

-// { 4, 0x37, "Kongsberg Maritime"},

-// { 4, 0x38, "Faraday Technology"},

-   { 4, 0xb9, "Altium"},

-// { 4, 0xba, "Insyte"},

-   { 4, 0x3b, "ARM"},

-// { 4, 0xbc, "DigiVision"},

-// { 4, 0x3d, "Vativ Technologies"},

-// { 4, 0x3e, "Endicott Interconnect Technologies"},

-   { 4, 0xbf, "Pericom"},

-// { 4, 0x40, "Bandspeed"},

-// { 4, 0xc1, "LeWiz Communications"},

-// { 4, 0xc2, "CPU Technology"},

- 	 { 4, 0x43, "Ramaxel"},

-// { 4, 0xc4, "DSP Group"},

-// { 4, 0x45, "Axis Communications"},

-   { 4, 0x46, "Legacy Electronics"},

-// { 4, 0xc7, "Chrontel"},

-// { 4, 0xc8, "Powerchip Semiconductor"},

-// { 4, 0x49, "MobilEye Technologies"},

-   { 4, 0x4a, "Excel Semiconductor"},

-   { 4, 0xcb, "A-DATA"},

-// { 4, 0x4c, "VirtualDigm"},

-   { 4, 0xcd, "G.Skill"},

-// { 4, 0xce, "Quanta Computer"},

-// { 4, 0x4f, "Yield Microelectronics"},

-// { 4, 0xd0, "Afa Technologies"},

-   { 4, 0x51, "Kingbox"},

-// { 4, 0x52, "Ceva"},

-// { 4, 0xd3, "iStor Networks"},

-// { 4, 0x54, "Advance Modules"},

-   { 4, 0xd5, "Microsoft"},

-// { 4, 0xd6, "Open-Silicon"},

-// { 4, 0x57, "Goal Semiconductor"},

-// { 4, 0x58, "ARC International"},

-   { 4, 0xd9, "Simmtec"},

-// { 4, 0xda, "Metanoia"},

-// { 4, 0x5b, "Key Stream"},

-// { 4, 0xdc, "Lowrance Electronics"},

-// { 4, 0x5d, "Adimos"},

-// { 4, 0x5e, "SiGe Semiconductor"},

-// { 4, 0xdf, "Fodus Communications"},

-// { 4, 0xe0, "Credence Systems Corp."},

-// { 4, 0x61, "Genesis Microchip"},

-// { 4, 0x62, "Vihana"},

-// { 4, 0xe3, "WIS Technologies"},

-// { 4, 0x64, "GateChange Technologies"},

-// { 4, 0xe5, "High Density Devices AS"},

-// { 4, 0xe6, "Synopsys"},

-// { 4, 0x67, "Gigaram"},

-// { 4, 0x68, "Enigma Semiconductor"},

-// { 4, 0xe9, "Century Micro"},

-// { 4, 0xea, "Icera Semiconductor"},

-// { 4, 0x6b, "Mediaworks Integrated Systems"},

-// { 4, 0xec, "O’Neil Product Development"},

-// { 4, 0x6d, "Supreme Top Technology"},

-// { 4, 0x6e, "MicroDisplay"},

-   { 4, 0xef, "Team Group"},

-// { 4, 0x70, "Sinett"},

-   { 4, 0xf1, "Toshiba"},

-// { 4, 0xf2, "Tensilica"},

-// { 4, 0x73, "SiRF Technology"},

-// { 4, 0xf4, "Bacoc"},

-// { 4, 0x75, "SMaL Camera Technologies"},

-   { 4, 0x76, "Thomson SC"},

-// { 4, 0xf7, "Airgo Networks"},

-// { 4, 0xf8, "Wisair"},

-// { 4, 0x79, "SigmaTel"},

-// { 4, 0x7a, "Arkados"},

-// { 4, 0xfb, "Compete IT KG"},

-// { 4, 0x7c, "Eudar Technology"},

-// { 4, 0xfd, "Focus Enhancements"},

-// { 4, 0xfe, "Xyratex"},

-// { 5, 0x01, "Specular Networks"},

-   { 5, 0x02, "Patriot Memory"},

-// { 5, 0x83, "U-Chip Technology Corp."},

-// { 5, 0x04, "Silicon Optix"},

-// { 5, 0x85, "Greenfield Networks"},

-   { 5, 0x86, "CompuRAM"},

-// { 5, 0x07, "Stargen"},

-// { 5, 0x08, "NetCell"},

-// { 5, 0x89, "Excalibrus Technologies"},

-// { 5, 0x8a, "SCM Microsystems"},

-// { 5, 0x0b, "Xsigo Systems"},

-// { 5, 0x8c, "CHIPS & Systems"},

-// { 5, 0x0d, "Tier"},

-// { 5, 0x0e, "CWRL Labs"},

-// { 5, 0x8f, "Teradici"},

-// { 5, 0x10, "Gigaram"},

-// { 5, 0x91, "g2 Microsystems"},

-// { 5, 0x92, "PowerFlash Semiconductor"},

-// { 5, 0x13, "P.A. Semi"},

-   { 5, 0x94, "NovaTech"},

-// { 5, 0x15, "c2 Microsystems"},

-// { 5, 0x16, "Level5 Networks"},

-   { 5, 0x97, "COS Memory"},

-// { 5, 0x98, "Innovasic Semiconductor"},

-// { 5, 0x19, "02IC"},

-// { 5, 0x1a, "Tabula"},

-   { 5, 0x9b, "Crucial"},

-// { 5, 0x1c, "Chelsio Communications"},

-// { 5, 0x9d, "Solarflare Communications"},

-// { 5, 0x9e, "Xambala"},

-// { 5, 0x1f, "EADS Astrium"},

-// { 5, 0x20, "Terra Semiconductor"},

-// { 5, 0xa1, "Imaging Works"},

-// { 5, 0xa2, "Astute Networks"},

-// { 5, 0x23, "Tzero"},

-// { 5, 0xa4, "Emulex"},

-// { 5, 0x25, "Power-One"},

-// { 5, 0x26, "Pulse~LINK"},

-// { 5, 0xa7, "Hon Hai Precision Industry"},

-// { 5, 0xa8, "White Rock Networks"},

-// { 5, 0x29, "Telegent Systems USA"},

-// { 5, 0x2a, "Atrua Technologies"},

-// { 5, 0xab, "Acbel Polytech"},

-// { 5, 0x2c, "eRide"},

-   { 5, 0xad, "ULi"},

-// { 5, 0xae, "Magnum Semiconductor"},

-// { 5, 0x2f, "neoOne Technology"},

-// { 5, 0xb0, "Connex Technology"},

-// { 5, 0x31, "Stream Processors"},

-// { 5, 0x32, "Focus Enhancements"},

-// { 5, 0xb3, "Telecis Wireless"},

-// { 5, 0x34, "uNav Microelectronics"},

-// { 5, 0xb5, "Tarari"},

-// { 5, 0xb6, "Ambric"},

-// { 5, 0x37, "Newport Media"},

-// { 5, 0x38, "VMTS"},

-// { 5, 0xb9, "Enuclia Semiconductor"},

-// { 5, 0xba, "Virtium Technology"},

-// { 5, 0x3b, "Solid State System"},

-// { 5, 0xbc, "Kian Tech LLC"},

-// { 5, 0x3d, "Artimi"},

-   { 5, 0x3e, "PQI"},

-// { 5, 0xbf, "Avago Technologies"},

-// { 5, 0x40, "ADTechnology"},

-   { 5, 0xc1, "Sigma Designs"},

-// { 5, 0xc2, "SiCortex"},

-// { 5, 0x43, "Ventura Technology Group"},

-// { 5, 0xc4, "eASIC"},

-// { 5, 0x45, "M.H.S. SAS"},

-   { 5, 0x46, "MSI"},

-// { 5, 0xc7, "Rapport"},

-// { 5, 0xc8, "Makway International"},

-// { 5, 0x49, "Broad Reach Engineering"},

-// { 5, 0x4a, "Semiconductor Mfg Intl Corp"},

-// { 5, 0xcb, "SiConnect"},

-// { 5, 0x4c, "FCI USA"},

-// { 5, 0xcd, "Validity Sensors"},

-// { 5, 0xce, "Coney Technology"},

-// { 5, 0x4f, "Spans Logic"},

-// { 5, 0xd0, "Neterion"},

-   { 5, 0x51, "Qimonda"},

-// { 5, 0x52, "New Japan Radio"},

-// { 5, 0xd3, "Velogix"},

-// { 5, 0x54, "Montalvo Systems"},

-// { 5, 0xd5, "iVivity"},

-   { 5, 0xd6, "Walton Chaintech"},

-   { 5, 0x57, "AENEON"},

-// { 5, 0x58, "Lorom Industrial"},

-// { 5, 0xd9, "Radiospire Networks"},

-// { 5, 0xda, "Sensio Technologies"},

-// { 5, 0x5b, "Nethra Imaging"},

-   { 5, 0xdc, "Hexon"},

-// { 5, 0x5d, "CompuStocx (CSX)"},

-// { 5, 0x5e, "Methode Electronics"},

-// { 5, 0xdf, "Connect One"},

-// { 5, 0xe0, "Opulan Technologies"},

-// { 5, 0x61, "Septentrio NV"},

-   { 5, 0x62, "Goldenmars"},

-   { 5, 0xe3, "Kreton"},

-// { 5, 0x64, "Cochlear"},

-// { 5, 0xe5, "Altair Semiconductor"},

-// { 5, 0xe6, "NetEffect"},

-// { 5, 0x67, "Spansion"},

-// { 5, 0x68, "Taiwan Semiconductor Mfg"},

-// { 5, 0xe9, "Emphany Systems"},

-// { 5, 0xea, "ApaceWave Technologies"},

-// { 5, 0x6b, "Mobilygen"},

-// { 5, 0xec, "Tego"},

-// { 5, 0x6d, "Cswitch"},

-// { 5, 0x6e, "Haier (Beijing) IC Design"},

-// { 5, 0xef, "MetaRAM"},

-// { 5, 0x70, "Axel Electronics"},

-// { 5, 0xf1, "Tilera"},

-// { 5, 0xf2, "Aquantia"},

-// { 5, 0x73, "Vivace Semiconductor"},

-// { 5, 0xf4, "Redpine Signals"},

-// { 5, 0x75, "Octalica"},

-// { 5, 0x76, "InterDigital Communications"},

-   { 5, 0xf7, "Avant Technology"},

-   { 5, 0xf8, "Asrock"},

-// { 5, 0x79, "Availink"},

-// { 5, 0x7a, "Quartics"},

-// { 5, 0xfb, "Element CXI"},

-// { 5, 0x7c, "Innovaciones Microelectronicas"},

-// { 5, 0xfd, "VeriSilicon Microelectronics"},

-// { 5, 0xfe, "W5 Networks"},

-// { 6, 0x01, "MOVEKING"},

-// { 6, 0x02, "Mavrix Technology"},

-// { 6, 0x83, "CellGuide"},

-// { 6, 0x04, "Faraday Technology"},

-// { 6, 0x85, "Diablo Technologies"},

-// { 6, 0x86, "Jennic"},

-// { 6, 0x07, "Octasic"},

-   { 6, 0x08, "Molex"},

-// { 6, 0x89, "3Leaf Networks"},

-// { 6, 0x8a, "Bright Micron Technology"},

-// { 6, 0x0b, "Netxen"},

-// { 6, 0x8c, "NextWave Broadband"},

-// { 6, 0x0d, "DisplayLink"},

-// { 6, 0x0e, "ZMOS Technology"},

-// { 6, 0x8f, "Tec-Hill"},

-// { 6, 0x10, "Multigig"},

-// { 6, 0x91, "Amimon"},

-// { 6, 0x92, "Euphonic Technologies"},

-// { 6, 0x13, "BRN Phoenix"},

-// { 6, 0x94, "InSilica"},

-// { 6, 0x15, "Ember"},

-   { 6, 0x16, "Avexir"},

-// { 6, 0x97, "Echelon"},

-// { 6, 0x98, "Edgewater Computer Systems"},

-// { 6, 0x19, "XMOS Semiconductor"},

-// { 6, 0x1a, "GENUSION"},

-   { 6, 0x9b, "Memory Corp NV"},

-// { 6, 0x1c, "SiliconBlue Technologies"},

-// { 6, 0x9d, "Rambus"},

-// { 6, 0x9e, "Andes Technology"},

-// { 6, 0x1f, "Coronis Systems"},

-// { 6, 0x20, "Achronix Semiconductor"},

-// { 6, 0xa1, "Siano Mobile Silicon"},

-// { 6, 0xa2, "Semtech"},

-// { 6, 0x23, "Pixelworks"},

-// { 6, 0xa4, "Gaisler Research AB"},

-// { 6, 0x25, "Teranetics"},

-// { 6, 0x26, "Toppan Printing"},

-// { 6, 0xa7, "Kingxcon"},

-   { 6, 0xa8, "SiS"},

-// { 6, 0x29, "I-O Data Device"},

-// { 6, 0x2a, "NDS Americas"},

-// { 6, 0xab, "Solomon Systech Limited"},

-// { 6, 0x2c, "On Demand Microelectronics"},

-// { 6, 0xad, "Amicus Wireless"},

-// { 6, 0xae, "SMARDTV SNC"},

-// { 6, 0x2f, "Comsys Communication"},

-// { 6, 0xb0, "Movidia"},

-// { 6, 0x31, "Javad GNSS"},

-// { 6, 0x32, "Montage Technology Group"},

-   { 6, 0xb3, "Trident"},

-   { 6, 0x34, "Super Talent"},

-// { 6, 0xb5, "Optichron"},

-// { 6, 0xb6, "Future Waves UK"},

-// { 6, 0x37, "SiBEAM"},

-// { 6, 0x38, "Inicore,"},

-// { 6, 0xb9, "Virident Systems"},

-// { 6, 0xba, "M2000"},

-// { 6, 0x3b, "ZeroG Wireless"},

-   { 6, 0xbc, "Gingle"},

-// { 6, 0x3d, "Space Micro"},

-// { 6, 0x3e, "Wilocity"},

-// { 6, 0xbf, "Novafora, Ic."},

-// { 6, 0x40, "iKoa"},

-   { 6, 0xc1, "ASint"},

-   { 6, 0xc2, "Ramtron"},

-// { 6, 0x43, "Plato Networks"},

-// { 6, 0xc4, "IPtronics AS"},

-// { 6, 0x45, "Infinite-Memories"},

-// { 6, 0x46, "Parade Technologies"},

-// { 6, 0xc7, "Dune Networks"},

-// { 6, 0xc8, "GigaDevice Semiconductor"},

-// { 6, 0x49, "Modu"},

-// { 6, 0x4a, "CEITEC"},

-// { 6, 0xcb, "Northrop Grumman"},

-// { 6, 0x4c, "XRONET"},

-// { 6, 0xcd, "Sicon Semiconductor AB"},

-// { 6, 0xce, "Atla Electronics"},

-   { 6, 0x4f, "TOPRAM"},

-// { 6, 0xd0, "Silego Technology"},

-   { 6, 0x51, "Kinglife"},

-// { 6, 0x52, "Ability Industries"},

-// { 6, 0xd3, "Silicon Power Computer & Communications"},

-// { 6, 0x54, "Augusta Technology"},

-// { 6, 0xd5, "Nantronics Semiconductors"},

-// { 6, 0xd6, "Hilscher Gesellschaft"},

-// { 6, 0x57, "Quixant"},

-// { 6, 0x58, "Percello"},

-// { 6, 0xd9, "NextIO"},

-// { 6, 0xda, "Scanimetrics"},

-// { 6, 0x5b, "FS-Semi Company"},

-// { 6, 0xdc, "Infinera"},

-   { 6, 0x5d, "SandForce"},

-   { 6, 0x5e, "Lexar Media"},

-// { 6, 0xdf, "Teradyne"},

-   { 6, 0xe0, "Memory Exchange Corp."},

-// { 6, 0x61, "Suzhou Smartek Electronics"},

-   { 6, 0x62, "Avantium"},

-// { 6, 0xe3, "ATP Electronics"},

-// { 6, 0x64, "Valens Semiconductor"},

-// { 6, 0xe5, "Agate Logic"},

-// { 6, 0xe6, "Netronome"},

-// { 6, 0x67, "Zenverge"},

-// { 6, 0x68, "N-trig"},

-// { 6, 0xe9, "SanMax Technologies"},

-// { 6, 0xea, "Contour Semiconductor"},

-   { 6, 0x6b, "TwinMOS"},

-   { 6, 0xec, "Silicon Systems"},

-// { 6, 0x6d, "V-Color Technology"},

-// { 6, 0x6e, "Certicom"},

-// { 6, 0xef, "JSC ICC Milandr"},

-// { 6, 0x70, "PhotoFast Global"},

-   { 6, 0xf1, "InnoDisk"},

-   { 6, 0xf2, "Muscle Power"},

-// { 6, 0x73, "Energy Micro"},

-// { 6, 0xf4, "Innofidei"},

-// { 6, 0x75, "CopperGate Communications"},

-// { 6, 0x76, "Holtek Semiconductor"},

-// { 6, 0xf7, "Myson Century"},

-// { 6, 0xf8, "FIDELIX"},

-// { 6, 0x79, "Red Digital Cinema"},

-// { 6, 0x7a, "Densbits Technology"},

-// { 6, 0xfb, "Zempro"},

-// { 6, 0x7c, "MoSys"},

-// { 6, 0xfd, "Provigent"},

-// { 6, 0xfe, "Triad Semiconductor"},

-// { 8, 0x01, "Siklu Communication"},

-// { 8, 0x02, "A Force Manufacturing"},

-   { 8, 0x83, "Strontium"},

-// { 8, 0x04, "Abilis Systems"},

-// { 8, 0x85, "Siglead"},

-// { 8, 0x86, "Ubicom"},

-// { 8, 0x07, "Unifosa"},

-// { 8, 0x08, "Stretch"},

-// { 8, 0x89, "Lantiq Deutschland"},

-// { 8, 0x8a, "Visipro."},

-   { 8, 0x0b, "EKMemory"},

-// { 8, 0x8c, "Microelectronics Institute ZTE"},

-// { 8, 0x0d, "Cognovo"},

-// { 8, 0x0e, "Carry Technology"},

-   { 8, 0x8f, "Nokia"},

-   { 8, 0x10, "King Tiger"},

-// { 8, 0x91, "Sierra Wireless"},

-   { 8, 0x92, "HT Micron"},

-   { 8, 0x13, "Albatron"},

-// { 8, 0x94, "Leica Geosystems AG"},

-// { 8, 0x15, "BroadLight"},

-// { 8, 0x16, "AEXEA"},

-// { 8, 0x97, "ClariPhy Communications"},

-// { 8, 0x98, "Green Plug"},

-// { 8, 0x19, "Design Art Networks"},

-// { 8, 0x1a, "Mach Xtreme Technology"},

-// { 8, 0x9b, "ATO Solutions"},

-// { 8, 0x1c, "Ramsta"},

-// { 8, 0x9d, "Greenliant Systems"},

-// { 8, 0x9e, "Teikon"},

-// { 8, 0x1f, "Antec Hadron"},

-// { 8, 0x20, "NavCom Technology"},

-// { 8, 0xa1, "Shanghai Fudan Microelectronics"},

-// { 8, 0xa2, "Calxeda"},

-// { 8, 0x23, "JSC EDC Electronics"},

-// { 8, 0xa4, "Kandit Technology"},

-// { 8, 0x25, "Ramos Technology"},

-// { 8, 0x26, "Goldenmars Technology"},

-// { 8, 0xa7, "XeL Technology"},

-// { 8, 0xa8, "Newzone"},

-   { 8, 0x29, "MercyPower"},

-// { 8, 0x2a, "Nanjing Yihuo Technology."},

-// { 8, 0xab, "Nethra Imaging"},

-// { 8, 0x2c, "SiTel Semiconductor BV"},

-// { 8, 0xad, "SolidGear"},

-   { 8, 0xae, "Topower"},

-// { 8, 0x2f, "Wilocity"},

-// { 8, 0xb0, "Profichip"},

-// { 8, 0x31, "Gerad Technologies"},

-   { 8, 0x32, "Ritek"},

-// { 8, 0xb3, "Gomos Technology Limited"},

-   { 8, 0x34, "Memoright"},

-// { 8, 0xb5, "D-Broad"},

-// { 8, 0xb6, "HiSilicon Technologies"},

-// { 8, 0x37, "Syndiant ."},

-// { 8, 0x38, "Enverv"},

-// { 8, 0xb9, "Cognex"},

-// { 8, 0xba, "Xinnova Technology"},

-   { 8, 0x3b, "Ultron"},

-// { 8, 0xbc, "Concord Idea"},

-// { 8, 0x3d, "AIM"},

-// { 8, 0x3e, "Lifetime Memory Products"},

-// { 8, 0xbf, "Ramsway"},

-// { 8, 0x40, "Recore Systems B.V."},

-// { 8, 0xc1, "Haotian Jinshibo Science Tech"},

-// { 8, 0xc2, "Being Advanced Memory"},

-// { 8, 0x43, "Adesto Technologies"},

-// { 8, 0xc4, "Giantec Semiconductor"},

-// { 8, 0x45, "HMD Electronics AG"},

-// { 8, 0x46, "Gloway International (HK)"},

-// { 8, 0xc7, "Kingcore"},

-// { 8, 0xc8, "Anucell Technology Holding"},

-// { 8, 0x49, "Accord Software & Systems Pvt."},

-// { 8, 0x4a, "Active-Semi"},

-// { 8, 0xcb, "Denso"},

-// { 8, 0x4c, "TLSI"},

-// { 8, 0xcd, "Shenzhen Daling Electronic"},

-// { 8, 0xce, "Mustang"},

-// { 8, 0x4f, "Orca Systems"},

-// { 8, 0xd0, "Passif Semiconductor"},

-// { 8, 0x51, "GigaDevice Semiconductor (Beijing)"},

-// { 8, 0x52, "Memphis Electronic"},

-// { 8, 0xd3, "Beckhoff Automation"},

-// { 8, 0x54, "Harmony Semiconductor Corp"},

-// { 8, 0xd5, "Air Computers SRL"},

-   { 8, 0xd6, "TMT Memory"},

-	 { 9, 0xff, ""}

-};

-

+/* MemTest86+ V5 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ * ------------------------------------------------
+ * Based on JEDEC JEP106-AG - January 2012
+ * All mo
+ */
+
+struct spd_jedec_manufacturer {
+    unsigned cont_code;
+    unsigned hex_byte;
+    char *name;
+};
+
+static struct spd_jedec_manufacturer jep106[] = {
+	 { 0, 0x01, "AMD"},
+	 { 0, 0x02, "AMI"},
+   { 0, 0x83, "Fairchild"},
+	 { 0, 0x04, "Fujitsu"},
+// { 0, 0x85, "GTE"},
+   { 0, 0x86, "Harris"},
+	 { 0, 0x07, "Hitachi"},
+   { 0, 0x08, "Inmos"},
+	 { 0, 0x89, "Intel"},
+   { 0, 0x8a, "I.T.T."},
+	 { 0, 0x0b, "Intersil"},
+   { 0, 0x8c, "Monolithic Memories"},
+	 { 0, 0x0d, "Mostek"},
+	 { 0, 0x0e, "Freescale"},
+	 { 0, 0x8f, "National"},
+	 { 0, 0x10, "NEC"},
+   { 0, 0x91, "RCA"},
+	 { 0, 0x92, "Raytheon"},
+	 { 0, 0x13, "Conexant"},
+// { 0, 0x94, "Seeq"},
+	 { 0, 0x15, "NXP"},
+   { 0, 0x16, "Synertek"},
+	 { 0, 0x97, "Texas Instruments"},
+	 { 0, 0x98, "Toshiba"},
+   { 0, 0x19, "Xicor"},
+   { 0, 0x1a, "Zilog"},
+// { 0, 0x9b, "Eurotechnique"},
+	 { 0, 0x1c, "Mitsubishi"},
+   { 0, 0x9d, "Lucent (AT&T)"},
+// { 0, 0x9e, "Exel"},
+	 { 0, 0x1f, "Atmel"},
+   { 0, 0x20, "SGS/Thomson"},
+// { 0, 0xa1, "Lattice Semi."},
+   { 0, 0xa2, "NCR"},
+// { 0, 0x23, "Wafer Scale Integration"},
+	 { 0, 0xa4, "IBM"},
+   { 0, 0x25, "Tristar"},
+// { 0, 0x26, "Visic"},
+	 { 0, 0xa7, "Intl. CMOS Technology"},
+// { 0, 0xa8, "SSSI"},
+	 { 0, 0x29, "MicrochipTechnology"},
+// { 0, 0x2a, "Ricoh"},
+// { 0, 0xab, "VLSI"},
+	 { 0, 0x2c, "Micron"},
+	 { 0, 0xad, "Hynix"},
+	 { 0, 0xae, "OKI Semiconductor"},
+// { 0, 0x2f, "ACTEL"},
+   { 0, 0xb0, "Sharp"},
+   { 0, 0x31, "Catalyst"},
+	 { 0, 0x32, "Panasonic"},
+	 { 0, 0xb3, "IDT"},
+   { 0, 0x34, "Cypress"},
+   { 0, 0xb5, "DEC"},
+   { 0, 0xb6, "LSI Logic"},
+// { 0, 0x37, "Zarlink (Plessey)"},
+   { 0, 0x38, "UTMC"},
+// { 0, 0xb9, "Thinking Machine"},
+   { 0, 0xba, "Thomson CSF"},
+// { 0, 0x3b, "Integrated CMOS (Vertex)"},
+// { 0, 0xbc, "Honeywell"},
+	 { 0, 0x3d, "Tektronix"},
+// { 0, 0x3e, "Oracle"},
+// { 0, 0xbf, "Silicon Storage Technology"},
+	 { 0, 0x40, "ProMos/Mosel"},
+	 { 0, 0xc1, "Infineon"},
+// { 0, 0xc2, "Macronix"},
+   { 0, 0x43, "Xerox"},
+// { 0, 0xc4, "Plus Logic"},
+	 { 0, 0x45, "SanDisk"},
+// { 0, 0x46, "Elan Circuit Tech."},
+// { 0, 0xc7, "European Silicon Str."},
+	 { 0, 0xc8, "Apple Computer"},
+	 { 0, 0x49, "Xilinx"},
+	 { 0, 0x4a, "Compaq"},
+// { 0, 0xcb, "Protocol Engines"},
+// { 0, 0x4c, "SCI"},
+	 { 0, 0xcd, "Seiko Instruments"},
+	 { 0, 0xce, "Samsung"},
+// { 0, 0x4f, "I3 Design System"},
+// { 0, 0xd0, "Klic"},
+// { 0, 0x51, "Crosspoint Solutions"},
+// { 0, 0x52, "Alliance Semiconductor"},
+// { 0, 0xd3, "Tandem"},
+	 { 0, 0x54, "Hewlett-Packard"},
+	 { 0, 0xd5, "Integrated Silicon Solutions"},
+// { 0, 0xd6, "Brooktree"},
+// { 0, 0x57, "New Media"},
+// { 0, 0x58, "MHS Electronic"},
+// { 0, 0xd9, "Performance Semi."},
+	 { 0, 0xda, "Winbond Electronic"},
+// { 0, 0x5b, "Kawasaki Steel"},
+// { 0, 0xdc, "Bright Micro"},
+// { 0, 0x5d, "TECMAR"},
+	 { 0, 0x5e, "Exar"},
+// { 0, 0xdf, "PCMCIA"},
+	 { 0, 0xe0, "LG"},
+// { 0, 0x61, "Northern Telecom"},
+	 { 0, 0x62, "Sanyo"},
+// { 0, 0xe3, "Array Microsystems"},
+// { 0, 0x64, "Crystal Semiconductor"},
+	 { 0, 0xe5, "Analog Devices"},
+// { 0, 0xe6, "PMC-Sierra"},
+// { 0, 0x67, "Asparix"},
+// { 0, 0x68, "Convex Computer"},
+// { 0, 0xe9, "Quality Semiconductor"},
+// { 0, 0xea, "Nimbus Technology"},
+// { 0, 0x6b, "Transwitch"},
+// { 0, 0xec, "Micronas (ITT Intermetall)"},
+   { 0, 0x6d, "Cannon"},
+// { 0, 0x6e, "Altera"},
+// { 0, 0xef, "NEXCOM"},
+// { 0, 0x70, "QUALCOMM"},
+	 { 0, 0xf1, "Sony"},
+// { 0, 0xf2, "Cray Research"},
+// { 0, 0x73, "AMS(Austria Micro)"},
+// { 0, 0xf4, "Vitesse"},
+// { 0, 0x75, "Aster Electronics"},
+// { 0, 0x76, "Bay Networks (Synoptic)"},
+// { 0, 0xf7, "Zentrum/ZMD"},
+// { 0, 0xf8, "TRW"},
+// { 0, 0x79, "Thesys"},
+// { 0, 0x7a, "Solbourne Computer"},
+   { 0, 0xfb, "Allied-Signal"},
+   { 0, 0x7c, "Dialog"},
+   { 0, 0xfd, "Media Vision"},
+// { 0, 0xfe, "Numonyx"},
+	 { 1, 0x01, "Cirrus Logic"},
+   { 1, 0x02, "National Instruments"},
+// { 1, 0x83, "ILC Data Device"},
+// { 1, 0x04, "Alcatel Mietec"},
+// { 1, 0x85, "Micro Linear"},
+// { 1, 0x86, "Univ. of NC"},
+// { 1, 0x07, "JTAG Technologies"},
+// { 1, 0x08, "BAE Systems (Loral)"},
+// { 1, 0x89, "Nchip"},
+// { 1, 0x8a, "Galileo Tech"},
+// { 1, 0x0b, "Bestlink Systems"},
+// { 1, 0x8c, "Graychip"},
+// { 1, 0x0d, "GENNUM"},
+// { 1, 0x0e, "VideoLogic"},
+// { 1, 0x8f, "Robert Bosch"},
+// { 1, 0x10, "Chip Express"},
+   { 1, 0x91, "DATARAM"},
+// { 1, 0x92, "United Microelectronics Corp."},
+// { 1, 0x13, "TCSI"},
+   { 1, 0x94, "Smart Modular"},
+// { 1, 0x15, "Hughes Aircraft"},
+// { 1, 0x16, "Lanstar Semiconductor"},
+// { 1, 0x97, "Qlogic"},
+	 { 1, 0x98, "Kingston"},
+// { 1, 0x19, "Music Semi"},
+// { 1, 0x1a, "Ericsson Components"},
+// { 1, 0x9b, "SpaSE"},
+// { 1, 0x1c, "Eon Silicon Devices"},
+// { 1, 0x9d, "Programmable Micro Corp"},
+// { 1, 0x9e, "DoD"},
+// { 1, 0x1f, "Integ. Memories Tech."},
+// { 1, 0x20, "Corollary"},
+// { 1, 0xa1, "Dallas Semiconductor"},
+// { 1, 0xa2, "Omnivision"},
+// { 1, 0x23, "EIV(Switzerland)"},
+// { 1, 0xa4, "Novatel Wireless"},
+// { 1, 0x25, "Zarlink (Mitel)"},
+// { 1, 0x26, "Clearpoint"},
+// { 1, 0xa7, "Cabletron"},
+// { 1, 0xa8, "STEC (Silicon Tech)"},
+// { 1, 0x29, "Vanguard"},
+// { 1, 0x2a, "Hagiwara Sys-Com"},
+// { 1, 0xab, "Vantis"},
+// { 1, 0x2c, "Celestica"},
+// { 1, 0xad, "Century"},
+// { 1, 0xae, "Hal Computers"},
+// { 1, 0x2f, "Rohm Company"},
+// { 1, 0xb0, "Juniper Networks"},
+// { 1, 0x31, "Libit Signal Processing"},
+	 { 1, 0x32, "Mushkin"},
+// { 1, 0xb3, "Tundra Semiconductor"},
+	 { 1, 0x34, "Adaptec"},
+// { 1, 0xb5, "LightSpeed Semi."},
+// { 1, 0xb6, "ZSP Corp."},
+// { 1, 0x37, "AMIC Technology"},
+// { 1, 0x38, "Adobe Systems"},
+// { 1, 0xb9, "Dynachip"},
+   { 1, 0xba, "PNY"},
+// { 1, 0x3b, "Newport Digital"},
+// { 1, 0xbc, "MMC Networks"},
+// { 1, 0x3d, "T Square"},
+// { 1, 0x3e, "Seiko Epson"},
+// { 1, 0xbf, "Broadcom"},
+// { 1, 0x40, "Viking Components"},
+// { 1, 0xc1, "V3 Semiconductor"},
+// { 1, 0xc2, "Flextronics (Orbit Semiconductor)"},
+// { 1, 0x43, "Suwa Electronics"},
+	 { 1, 0xc4, "Transmeta"},
+	 { 1, 0x45, "Micron CMS"},
+// { 1, 0x46, "American Computer & Digital Components"},
+// { 1, 0xc7, "Enhance 3000"},
+	 { 1, 0xc8, "Tower Semiconductor"},
+// { 1, 0x49, "CPU Design"},
+// { 1, 0x4a, "Price Point"},
+	 { 1, 0xcb, "Maxim Integrated Product"},
+// { 1, 0x4c, "Tellabs"},
+// { 1, 0xcd, "Centaur Technology"},
+   { 1, 0xce, "Unigen"},
+	 { 1, 0x4f, "Transcend"},
+   { 1, 0xd0, "Memory Card"},
+// { 1, 0x51, "CKD"},
+// { 1, 0x52, "Capital Instruments"},
+// { 1, 0xd3, "Aica Kogyo"},
+// { 1, 0x54, "Linvex Technology"},
+   { 1, 0xd5, "MSC"},
+// { 1, 0xd6, "AKM Company"},
+// { 1, 0x57, "Dynamem"},
+// { 1, 0x58, "NERA ASA"},
+// { 1, 0xd9, "GSI Technology"},
+	 { 1, 0xda, "Dane-Elec"},
+// { 1, 0x5b, "Acorn Computers"},
+// { 1, 0xdc, "Lara Technology"},
+// { 1, 0x5d, "Oak Technology"},
+   { 1, 0x5e, "Itec Memory"},
+// { 1, 0xdf, "Tanisys Technology"},
+// { 1, 0xe0, "Truevision"},
+   { 1, 0x61, "Wintec"},
+// { 1, 0x62, "Super PC Memory"},
+// { 1, 0xe3, "MGV Memory"},
+// { 1, 0x64, "Galvantech"},
+// { 1, 0xe5, "Gadzoox Networks"},
+// { 1, 0xe6, "Multi Dimensional Cons."},
+// { 1, 0x67, "GateField"},
+	 { 1, 0x68, "Integrated Memory System"},
+// { 1, 0xe9, "Triscend"},
+// { 1, 0xea, "XaQti"},
+// { 1, 0x6b, "Goldenram"},
+// { 1, 0xec, "Clear Logic"},
+// { 1, 0x6d, "Cimaron Communications"},
+// { 1, 0x6e, "Nippon Steel Semi. Corp."},
+// { 1, 0xef, "Advantage Memory"},
+// { 1, 0x70, "AMCC"},
+	 { 1, 0xf1, "LeCroy"},
+// { 1, 0xf2, "Yamaha"},
+// { 1, 0x73, "Digital Microwave"},
+// { 1, 0xf4, "NetLogic Microsystems"},
+// { 1, 0x75, "MIMOS Semiconductor"},
+// { 1, 0x76, "Advanced Fibre"},
+// { 1, 0xf7, "BF Goodrich Data."},
+// { 1, 0xf8, "Epigram"},
+// { 1, 0x79, "Acbel Polytech"},
+	 { 1, 0x7a, "Apacer Technology"},
+// { 1, 0xfb, "Admor Memory"},
+	 { 1, 0x7c, "FOXCONN"},
+// { 1, 0xfd, "Quadratics Superconductor"},
+// { 1, 0xfe, "3COM"},
+// { 2, 0x01, "Camintonn"},
+// { 2, 0x02, "ISOA"},
+// { 2, 0x83, "Agate Semiconductor"},
+// { 2, 0x04, "ADMtek"},
+// { 2, 0x85, "HYPERTEC"},
+// { 2, 0x86, "Adhoc Technologies"},
+// { 2, 0x07, "MOSAID Technologies"},
+// { 2, 0x08, "Ardent Technologies"},
+// { 2, 0x89, "Switchcore"},
+// { 2, 0x8a, "Cisco Systems"},
+// { 2, 0x0b, "Allayer Technologies"},
+// { 2, 0x8c, "WorkX AG (Wichman)"},
+// { 2, 0x0d, "Oasis Semiconductor"},
+// { 2, 0x0e, "Novanet Semiconductor"},
+// { 2, 0x8f, "E-M Solutions"},
+// { 2, 0x10, "Power General"},
+// { 2, 0x91, "Advanced Hardware Arch."},
+// { 2, 0x92, "Inova Semiconductors"},
+// { 2, 0x13, "Telocity"},
+// { 2, 0x94, "Delkin Devices"},
+// { 2, 0x15, "Symagery Microsystems"},
+// { 2, 0x16, "C-Port"},
+// { 2, 0x97, "SiberCore Technologies"},
+// { 2, 0x98, "Southland Microsystems"},
+// { 2, 0x19, "Malleable Technologies"},
+// { 2, 0x1a, "Kendin Communications"},
+// { 2, 0x9b, "Great Technology Microcomputer"},
+// { 2, 0x1c, "Sanmina"},
+// { 2, 0x9d, "HADCO"},
+	 { 2, 0x9e, "Corsair"},
+// { 2, 0x1f, "Actrans System"},
+// { 2, 0x20, "ALPHA Technologies"},
+// { 2, 0xa1, "Silicon Laboratories (Cygnal)"},
+// { 2, 0xa2, "Artesyn Technologies"},
+// { 2, 0x23, "Align Manufacturing"},
+// { 2, 0xa4, "Peregrine Semiconductor"},
+// { 2, 0x25, "Chameleon Systems"},
+// { 2, 0x26, "Aplus Flash Technology"},
+   { 2, 0xa7, "MIPS Technologies"},
+// { 2, 0xa8, "Chrysalis ITS"},
+// { 2, 0x29, "ADTEC"},
+   { 2, 0x2a, "Kentron Technologies"},
+// { 2, 0xab, "Win Technologies"},
+// { 2, 0x2c, "Tachyon Semiconductor (ASIC)"},
+// { 2, 0xad, "Extreme Packet Devices"},
+// { 2, 0xae, "RF Micro Devices"},
+   { 2, 0x2f, "Siemens AG"},
+// { 2, 0xb0, "Sarnoff"},
+// { 2, 0x31, "Itautec SA"},
+// { 2, 0x32, "Radiata"},
+// { 2, 0xb3, "Benchmark Elect. (AVEX)"},
+// { 2, 0x34, "Legend"},
+   { 2, 0xb5, "SpecTek"},
+// { 2, 0xb6, "Hi/fn"},
+// { 2, 0x37, "Enikia"},
+// { 2, 0x38, "SwitchOn Networks"},
+// { 2, 0xb9, "AANetcom"},
+// { 2, 0xba, "Micro Memory Bank"},
+   { 2, 0x3b, "ESS Technology"},
+// { 2, 0xbc, "Virata"},
+// { 2, 0x3d, "Excess Bandwidth"},
+// { 2, 0x3e, "West Bay Semiconductor"},
+// { 2, 0xbf, "DSP Group"},
+// { 2, 0x40, "Newport Communications"},
+// { 2, 0xc1, "Chip2Chip"},
+// { 2, 0xc2, "Phobos"},
+// { 2, 0x43, "Intellitech"},
+// { 2, 0xc4, "Nordic VLSI ASA"},
+// { 2, 0x45, "Ishoni Networks"},
+// { 2, 0x46, "Silicon Spice"},
+// { 2, 0xc7, "Alchemy Semiconductor"},
+   { 2, 0xc8, "Agilent Technologies"},
+// { 2, 0x49, "Centillium Communications"},
+// { 2, 0x4a, "W.L. Gore"},
+// { 2, 0xcb, "HanBit Electronics"},
+// { 2, 0x4c, "GlobeSpan"},
+// { 2, 0xcd, "Element 14"},
+// { 2, 0xce, "Pycon"},
+// { 2, 0x4f, "Saifun Semiconductors"},
+// { 2, 0xd0, "Sibyte,"},
+// { 2, 0x51, "MetaLink Technologies"},
+// { 2, 0x52, "Feiya Technology"},
+// { 2, 0xd3, "I & C Technology"},
+// { 2, 0x54, "Shikatronics"},
+// { 2, 0xd5, "Elektrobit"},
+// { 2, 0xd6, "Megic"},
+// { 2, 0x57, "Com-Tier"},
+// { 2, 0x58, "Malaysia Micro Solutions"},
+// { 2, 0xd9, "Hyperchip"},
+// { 2, 0xda, "Gemstone Communications"},
+// { 2, 0x5b, "Anadigm (Anadyne)"},
+// { 2, 0xdc, "3ParData"},
+// { 2, 0x5d, "Mellanox Technologies"},
+// { 2, 0x5e, "Tenx Technologies"},
+// { 2, 0xdf, "Helix AG"},
+// { 2, 0xe0, "Domosys"},
+// { 2, 0x61, "Skyup Technology"},
+// { 2, 0x62, "HiNT"},
+// { 2, 0xe3, "Chiaro"},
+   { 2, 0x64, "MDT"},
+// { 2, 0xe5, "Exbit Technology A/S"},
+// { 2, 0xe6, "Integrated Technology Express"},
+// { 2, 0x67, "AVED Memory"},
+// { 2, 0x68, "Legerity"},
+// { 2, 0xe9, "Jasmine Networks"},
+// { 2, 0xea, "Caspian Networks"},
+// { 2, 0x6b, "nCUBE"},
+// { 2, 0xec, "Silicon Access Networks"},
+// { 2, 0x6d, "FDK"},
+// { 2, 0x6e, "High Bandwidth Access"},
+// { 2, 0xef, "MultiLink Technology"},
+// { 2, 0x70, "BRECIS"},
+// { 2, 0xf1, "World Wide Packets"},
+// { 2, 0xf2, "APW"},
+// { 2, 0x73, "Chicory Systems"},
+// { 2, 0xf4, "Xstream Logic"},
+// { 2, 0x75, "Fast-Chip"},
+// { 2, 0x76, "Zucotto Wireless"},
+// { 2, 0xf7, "Realchip"},
+// { 2, 0xf8, "Galaxy Power"},
+// { 2, 0x79, "eSilicon"},
+// { 2, 0x7a, "Morphics Technology"},
+// { 2, 0xfb, "Accelerant Networks"},
+// { 2, 0x7c, "Silicon Wave"},
+// { 2, 0xfd, "SandCraft"},
+   { 2, 0xfe, "Elpida"},
+// { 3, 0x01, "Solectron"},
+   { 3, 0x02, "Optosys Technologies"},
+   { 3, 0x83, "Buffalo"},
+// { 3, 0x04, "TriMedia Technologies"},
+// { 3, 0x85, "Cyan Technologies"},
+// { 3, 0x86, "Global Locate"},
+// { 3, 0x07, "Optillion"},
+// { 3, 0x08, "Terago Communications"},
+// { 3, 0x89, "Ikanos Communications"},
+   { 3, 0x8a, "Princeton"},
+   { 3, 0x0b, "Nanya"},
+// { 3, 0x8c, "Elite Flash Storage"},
+// { 3, 0x0d, "Mysticom"},
+// { 3, 0x0e, "LightSand Communications"},
+   { 3, 0x8f, "ATI"},
+// { 3, 0x10, "Agere Systems"},
+// { 3, 0x91, "NeoMagic"},
+// { 3, 0x92, "AuroraNetics"},
+// { 3, 0x13, "Golden Empire"},
+   { 3, 0x94, "Mushkin"},
+// { 3, 0x15, "Tioga Technologies"},
+   { 3, 0x16, "Netlist"},
+// { 3, 0x97, "TeraLogic"},
+// { 3, 0x98, "Cicada Semiconductor"},
+   { 3, 0x19, "Centon"},
+   { 3, 0x1a, "Tyco Electronics"},
+// { 3, 0x9b, "Magis Works"},
+// { 3, 0x1c, "Zettacom"},
+// { 3, 0x9d, "Cogency Semiconductor"},
+// { 3, 0x9e, "Chipcon AS"},
+// { 3, 0x1f, "Aspex Technology"},
+// { 3, 0x20, "F5 Networks"},
+// { 3, 0xa1, "Programmable Silicon Solutions"},
+// { 3, 0xa2, "ChipWrights"},
+// { 3, 0x23, "Acorn Networks"},
+// { 3, 0xa4, "Quicklogic"},
+   { 3, 0x25, "Kingmax"},
+// { 3, 0x26, "BOPS"},
+// { 3, 0xa7, "Flasys"},
+// { 3, 0xa8, "BitBlitz Communications"},
+   { 3, 0x29, "eMemory Technology"},
+// { 3, 0x2a, "Procket Networks"},
+// { 3, 0xab, "Purple Ray"},
+// { 3, 0x2c, "Trebia Networks"},
+// { 3, 0xad, "Delta Electronics"},
+// { 3, 0xae, "Onex Communications"},
+// { 3, 0x2f, "Ample Communications"},
+   { 3, 0xb0, "Memory Experts"},
+// { 3, 0x31, "Astute Networks"},
+// { 3, 0x32, "Azanda Network Devices"},
+// { 3, 0xb3, "Dibcom"},
+// { 3, 0x34, "Tekmos"},
+// { 3, 0xb5, "API NetWorks"},
+// { 3, 0xb6, "Bay Microsystems"},
+// { 3, 0x37, "Firecron"},
+// { 3, 0x38, "Resonext Communications"},
+// { 3, 0xb9, "Tachys Technologies"},
+// { 3, 0xba, "Equator Technology"},
+// { 3, 0x3b, "Concept Computer"},
+// { 3, 0xbc, "SILCOM"},
+// { 3, 0x3d, "3Dlabs"},
+// { 3, 0x3e, "c’t Magazine"},
+// { 3, 0xbf, "Sanera Systems"},
+// { 3, 0x40, "Silicon Packets"},
+   { 3, 0xc1, "Viasystems Group"},
+   { 3, 0xc2, "Simtek"},
+// { 3, 0x43, "Semicon Devices Singapore"},
+// { 3, 0xc4, "Satron Handelsges"},
+// { 3, 0x45, "Improv Systems"},
+// { 3, 0x46, "INDUSYS"},
+// { 3, 0xc7, "Corrent"},
+// { 3, 0xc8, "Infrant Technologies"},
+// { 3, 0x49, "Ritek Corp"},
+// { 3, 0x4a, "empowerTel Networks"},
+// { 3, 0xcb, "Hypertec"},
+// { 3, 0x4c, "Cavium Networks"},
+   { 3, 0xcd, "PLX Technology"},
+// { 3, 0xce, "Massana Design"},
+// { 3, 0x4f, "Intrinsity"},
+// { 3, 0xd0, "Valence Semiconductor"},
+// { 3, 0x51, "Terawave Communications"},
+// { 3, 0x52, "IceFyre Semiconductor"},
+// { 3, 0xd3, "Primarion"},
+// { 3, 0x54, "Picochip Designs"},
+// { 3, 0xd5, "Silverback Systems"},
+   { 3, 0xd6, "Jade Star"},
+// { 3, 0x57, "Pijnenburg Securealink"},
+   { 3, 0x58, "takeMS"},
+// { 3, 0xd9, "Cambridge Silicon Radio"},
+   { 3, 0xda, "Swissbit"},
+// { 3, 0x5b, "Nazomi Communications"},
+// { 3, 0xdc, "eWave System"},
+// { 3, 0x5d, "Rockwell Collins"},
+// { 3, 0x5e, "Picocel (Paion)"},
+// { 3, 0xdf, "Alphamosaic"},
+// { 3, 0xe0, "Sandburst"},
+// { 3, 0x61, "SiCon Video"},
+// { 3, 0x62, "NanoAmp Solutions"},
+// { 3, 0xe3, "Ericsson Technology"},
+// { 3, 0x64, "PrairieComm"},
+   { 3, 0xe5, "Mitac International"},
+// { 3, 0xe6, "Layer N Networks"},
+// { 3, 0x67, "MtekVision (Atsana)"},
+// { 3, 0x68, "Allegro Networks"},
+// { 3, 0xe9, "Marvell Semiconductors"},
+// { 3, 0xea, "Netergy Microelectronic"},
+   { 3, 0x6b, "nVidia"},
+// { 3, 0xec, "Internet Machines"},
+// { 3, 0x6d, "Peak Electronics"},
+// { 3, 0x6e, "Litchfield Communication"},
+   { 3, 0xef, "Accton"},
+// { 3, 0x70, "Teradiant Networks"},
+// { 3, 0xf1, "Scaleo Chip"},
+// { 3, 0xf2, "Cortina Systems"},
+   { 3, 0x73, "RAM Components"},
+// { 3, 0xf4, "Raqia Networks"},
+// { 3, 0x75, "ClearSpeed"},
+// { 3, 0x76, "Matsushita Battery"},
+// { 3, 0xf7, "Xelerated"},
+// { 3, 0xf8, "SimpleTech"},
+   { 3, 0x79, "Utron"},
+// { 3, 0x7a, "Astec International"},
+// { 3, 0xfb, "AVM"},
+// { 3, 0x7c, "Redux Communications"},
+// { 3, 0xfd, "Dot Hill Systems"},
+   { 3, 0xfe, "TeraChip"},
+   { 4, 0x01, "T-RAM"},
+// { 4, 0x02, "Innovics Wireless"},
+// { 4, 0x83, "Teknovus"},
+// { 4, 0x04, "KeyEye Communications"},
+// { 4, 0x85, "Runcom Technologies"},
+// { 4, 0x86, "RedSwitch"},
+// { 4, 0x07, "Dotcast"},
+   { 4, 0x08, "Silicon Mountain Memory"},
+// { 4, 0x89, "Signia Technologies"},
+// { 4, 0x8a, "Pixim"},
+// { 4, 0x0b, "Galazar Networks"},
+// { 4, 0x8c, "White Electronic Designs"},
+// { 4, 0x0d, "Patriot Scientific"},
+// { 4, 0x0e, "Neoaxiom"},
+// { 4, 0x8f, "3Y Power Technology"},
+   { 4, 0x10, "Scaleo Chip"},
+// { 4, 0x91, "Potentia Power Systems"},
+// { 4, 0x92, "C-guys"},
+// { 4, 0x13, "Digital Communications Technology"},
+// { 4, 0x94, "Silicon-Based Technology"},
+// { 4, 0x15, "Fulcrum Microsystems"},
+// { 4, 0x16, "Positivo Informatica"},
+// { 4, 0x97, "XIOtech"},
+// { 4, 0x98, "PortalPlayer"},
+// { 4, 0x19, "Zhiying Software"},
+// { 4, 0x1a, "ParkerVision"},
+// { 4, 0x9b, "Phonex Broadband"},
+// { 4, 0x1c, "Skyworks Solutions"},
+// { 4, 0x9d, "Entropic Communications"},
+// { 4, 0x9e, "Pacific Force Technology"},
+// { 4, 0x1f, "Zensys A/S"},
+// { 4, 0x20, "Legend Silicon Corp."},
+// { 4, 0xa1, "Sci-worx"},
+// { 4, 0xa2, "SMSC (Standard Microsystems)"},
+   { 4, 0x23, "Renesas"},
+// { 4, 0xa4, "Raza Microelectronics"},
+// { 4, 0x25, "Phyworks"},
+// { 4, 0x26, "MediaTek"},
+// { 4, 0xa7, "Non-cents Productions"},
+// { 4, 0xa8, "US Modular"},
+// { 4, 0x29, "Wintegra"},
+// { 4, 0x2a, "Mathstar"},
+// { 4, 0xab, "StarCore"},
+// { 4, 0x2c, "Oplus Technologies"},
+// { 4, 0xad, "Mindspeed"},
+// { 4, 0xae, "Just Young Computer"},
+// { 4, 0x2f, "Radia Communications"},
+   { 4, 0xb0, "OCZ"},
+// { 4, 0x31, "Emuzed"},
+// { 4, 0x32, "LOGIC Devices"},
+// { 4, 0xb3, "Inphi"},
+// { 4, 0x34, "Quake Technologies"},
+// { 4, 0xb5, "Vixel"},
+// { 4, 0xb6, "SolusTek"},
+// { 4, 0x37, "Kongsberg Maritime"},
+// { 4, 0x38, "Faraday Technology"},
+   { 4, 0xb9, "Altium"},
+// { 4, 0xba, "Insyte"},
+   { 4, 0x3b, "ARM"},
+// { 4, 0xbc, "DigiVision"},
+// { 4, 0x3d, "Vativ Technologies"},
+// { 4, 0x3e, "Endicott Interconnect Technologies"},
+   { 4, 0xbf, "Pericom"},
+// { 4, 0x40, "Bandspeed"},
+// { 4, 0xc1, "LeWiz Communications"},
+// { 4, 0xc2, "CPU Technology"},
+ 	 { 4, 0x43, "Ramaxel"},
+// { 4, 0xc4, "DSP Group"},
+// { 4, 0x45, "Axis Communications"},
+   { 4, 0x46, "Legacy Electronics"},
+// { 4, 0xc7, "Chrontel"},
+// { 4, 0xc8, "Powerchip Semiconductor"},
+// { 4, 0x49, "MobilEye Technologies"},
+   { 4, 0x4a, "Excel Semiconductor"},
+   { 4, 0xcb, "A-DATA"},
+// { 4, 0x4c, "VirtualDigm"},
+   { 4, 0xcd, "G.Skill"},
+// { 4, 0xce, "Quanta Computer"},
+// { 4, 0x4f, "Yield Microelectronics"},
+// { 4, 0xd0, "Afa Technologies"},
+   { 4, 0x51, "Kingbox"},
+// { 4, 0x52, "Ceva"},
+// { 4, 0xd3, "iStor Networks"},
+// { 4, 0x54, "Advance Modules"},
+   { 4, 0xd5, "Microsoft"},
+// { 4, 0xd6, "Open-Silicon"},
+// { 4, 0x57, "Goal Semiconductor"},
+// { 4, 0x58, "ARC International"},
+   { 4, 0xd9, "Simmtec"},
+// { 4, 0xda, "Metanoia"},
+// { 4, 0x5b, "Key Stream"},
+// { 4, 0xdc, "Lowrance Electronics"},
+// { 4, 0x5d, "Adimos"},
+// { 4, 0x5e, "SiGe Semiconductor"},
+// { 4, 0xdf, "Fodus Communications"},
+// { 4, 0xe0, "Credence Systems Corp."},
+// { 4, 0x61, "Genesis Microchip"},
+// { 4, 0x62, "Vihana"},
+// { 4, 0xe3, "WIS Technologies"},
+// { 4, 0x64, "GateChange Technologies"},
+// { 4, 0xe5, "High Density Devices AS"},
+// { 4, 0xe6, "Synopsys"},
+// { 4, 0x67, "Gigaram"},
+// { 4, 0x68, "Enigma Semiconductor"},
+// { 4, 0xe9, "Century Micro"},
+// { 4, 0xea, "Icera Semiconductor"},
+// { 4, 0x6b, "Mediaworks Integrated Systems"},
+// { 4, 0xec, "O’Neil Product Development"},
+// { 4, 0x6d, "Supreme Top Technology"},
+// { 4, 0x6e, "MicroDisplay"},
+   { 4, 0xef, "Team Group"},
+// { 4, 0x70, "Sinett"},
+   { 4, 0xf1, "Toshiba"},
+// { 4, 0xf2, "Tensilica"},
+// { 4, 0x73, "SiRF Technology"},
+// { 4, 0xf4, "Bacoc"},
+// { 4, 0x75, "SMaL Camera Technologies"},
+   { 4, 0x76, "Thomson SC"},
+// { 4, 0xf7, "Airgo Networks"},
+// { 4, 0xf8, "Wisair"},
+// { 4, 0x79, "SigmaTel"},
+// { 4, 0x7a, "Arkados"},
+// { 4, 0xfb, "Compete IT KG"},
+// { 4, 0x7c, "Eudar Technology"},
+// { 4, 0xfd, "Focus Enhancements"},
+// { 4, 0xfe, "Xyratex"},
+// { 5, 0x01, "Specular Networks"},
+   { 5, 0x02, "Patriot Memory"},
+// { 5, 0x83, "U-Chip Technology Corp."},
+// { 5, 0x04, "Silicon Optix"},
+// { 5, 0x85, "Greenfield Networks"},
+   { 5, 0x86, "CompuRAM"},
+// { 5, 0x07, "Stargen"},
+// { 5, 0x08, "NetCell"},
+// { 5, 0x89, "Excalibrus Technologies"},
+// { 5, 0x8a, "SCM Microsystems"},
+// { 5, 0x0b, "Xsigo Systems"},
+// { 5, 0x8c, "CHIPS & Systems"},
+// { 5, 0x0d, "Tier"},
+// { 5, 0x0e, "CWRL Labs"},
+// { 5, 0x8f, "Teradici"},
+// { 5, 0x10, "Gigaram"},
+// { 5, 0x91, "g2 Microsystems"},
+// { 5, 0x92, "PowerFlash Semiconductor"},
+// { 5, 0x13, "P.A. Semi"},
+   { 5, 0x94, "NovaTech"},
+// { 5, 0x15, "c2 Microsystems"},
+// { 5, 0x16, "Level5 Networks"},
+   { 5, 0x97, "COS Memory"},
+// { 5, 0x98, "Innovasic Semiconductor"},
+// { 5, 0x19, "02IC"},
+// { 5, 0x1a, "Tabula"},
+   { 5, 0x9b, "Crucial"},
+// { 5, 0x1c, "Chelsio Communications"},
+// { 5, 0x9d, "Solarflare Communications"},
+// { 5, 0x9e, "Xambala"},
+// { 5, 0x1f, "EADS Astrium"},
+// { 5, 0x20, "Terra Semiconductor"},
+// { 5, 0xa1, "Imaging Works"},
+// { 5, 0xa2, "Astute Networks"},
+// { 5, 0x23, "Tzero"},
+// { 5, 0xa4, "Emulex"},
+// { 5, 0x25, "Power-One"},
+// { 5, 0x26, "Pulse~LINK"},
+// { 5, 0xa7, "Hon Hai Precision Industry"},
+// { 5, 0xa8, "White Rock Networks"},
+// { 5, 0x29, "Telegent Systems USA"},
+// { 5, 0x2a, "Atrua Technologies"},
+// { 5, 0xab, "Acbel Polytech"},
+// { 5, 0x2c, "eRide"},
+   { 5, 0xad, "ULi"},
+// { 5, 0xae, "Magnum Semiconductor"},
+// { 5, 0x2f, "neoOne Technology"},
+// { 5, 0xb0, "Connex Technology"},
+// { 5, 0x31, "Stream Processors"},
+// { 5, 0x32, "Focus Enhancements"},
+// { 5, 0xb3, "Telecis Wireless"},
+// { 5, 0x34, "uNav Microelectronics"},
+// { 5, 0xb5, "Tarari"},
+// { 5, 0xb6, "Ambric"},
+// { 5, 0x37, "Newport Media"},
+// { 5, 0x38, "VMTS"},
+// { 5, 0xb9, "Enuclia Semiconductor"},
+// { 5, 0xba, "Virtium Technology"},
+// { 5, 0x3b, "Solid State System"},
+// { 5, 0xbc, "Kian Tech LLC"},
+// { 5, 0x3d, "Artimi"},
+   { 5, 0x3e, "PQI"},
+// { 5, 0xbf, "Avago Technologies"},
+// { 5, 0x40, "ADTechnology"},
+   { 5, 0xc1, "Sigma Designs"},
+// { 5, 0xc2, "SiCortex"},
+// { 5, 0x43, "Ventura Technology Group"},
+// { 5, 0xc4, "eASIC"},
+// { 5, 0x45, "M.H.S. SAS"},
+   { 5, 0x46, "MSI"},
+// { 5, 0xc7, "Rapport"},
+// { 5, 0xc8, "Makway International"},
+// { 5, 0x49, "Broad Reach Engineering"},
+// { 5, 0x4a, "Semiconductor Mfg Intl Corp"},
+// { 5, 0xcb, "SiConnect"},
+// { 5, 0x4c, "FCI USA"},
+// { 5, 0xcd, "Validity Sensors"},
+// { 5, 0xce, "Coney Technology"},
+// { 5, 0x4f, "Spans Logic"},
+// { 5, 0xd0, "Neterion"},
+   { 5, 0x51, "Qimonda"},
+// { 5, 0x52, "New Japan Radio"},
+// { 5, 0xd3, "Velogix"},
+// { 5, 0x54, "Montalvo Systems"},
+// { 5, 0xd5, "iVivity"},
+   { 5, 0xd6, "Walton Chaintech"},
+   { 5, 0x57, "AENEON"},
+// { 5, 0x58, "Lorom Industrial"},
+// { 5, 0xd9, "Radiospire Networks"},
+// { 5, 0xda, "Sensio Technologies"},
+// { 5, 0x5b, "Nethra Imaging"},
+   { 5, 0xdc, "Hexon"},
+// { 5, 0x5d, "CompuStocx (CSX)"},
+// { 5, 0x5e, "Methode Electronics"},
+// { 5, 0xdf, "Connect One"},
+// { 5, 0xe0, "Opulan Technologies"},
+// { 5, 0x61, "Septentrio NV"},
+   { 5, 0x62, "Goldenmars"},
+   { 5, 0xe3, "Kreton"},
+// { 5, 0x64, "Cochlear"},
+// { 5, 0xe5, "Altair Semiconductor"},
+// { 5, 0xe6, "NetEffect"},
+// { 5, 0x67, "Spansion"},
+// { 5, 0x68, "Taiwan Semiconductor Mfg"},
+// { 5, 0xe9, "Emphany Systems"},
+// { 5, 0xea, "ApaceWave Technologies"},
+// { 5, 0x6b, "Mobilygen"},
+// { 5, 0xec, "Tego"},
+// { 5, 0x6d, "Cswitch"},
+// { 5, 0x6e, "Haier (Beijing) IC Design"},
+// { 5, 0xef, "MetaRAM"},
+// { 5, 0x70, "Axel Electronics"},
+// { 5, 0xf1, "Tilera"},
+// { 5, 0xf2, "Aquantia"},
+// { 5, 0x73, "Vivace Semiconductor"},
+// { 5, 0xf4, "Redpine Signals"},
+// { 5, 0x75, "Octalica"},
+// { 5, 0x76, "InterDigital Communications"},
+   { 5, 0xf7, "Avant Technology"},
+   { 5, 0xf8, "Asrock"},
+// { 5, 0x79, "Availink"},
+// { 5, 0x7a, "Quartics"},
+// { 5, 0xfb, "Element CXI"},
+// { 5, 0x7c, "Innovaciones Microelectronicas"},
+// { 5, 0xfd, "VeriSilicon Microelectronics"},
+// { 5, 0xfe, "W5 Networks"},
+// { 6, 0x01, "MOVEKING"},
+// { 6, 0x02, "Mavrix Technology"},
+// { 6, 0x83, "CellGuide"},
+// { 6, 0x04, "Faraday Technology"},
+// { 6, 0x85, "Diablo Technologies"},
+// { 6, 0x86, "Jennic"},
+// { 6, 0x07, "Octasic"},
+   { 6, 0x08, "Molex"},
+// { 6, 0x89, "3Leaf Networks"},
+// { 6, 0x8a, "Bright Micron Technology"},
+// { 6, 0x0b, "Netxen"},
+// { 6, 0x8c, "NextWave Broadband"},
+// { 6, 0x0d, "DisplayLink"},
+// { 6, 0x0e, "ZMOS Technology"},
+// { 6, 0x8f, "Tec-Hill"},
+// { 6, 0x10, "Multigig"},
+// { 6, 0x91, "Amimon"},
+// { 6, 0x92, "Euphonic Technologies"},
+// { 6, 0x13, "BRN Phoenix"},
+// { 6, 0x94, "InSilica"},
+// { 6, 0x15, "Ember"},
+   { 6, 0x16, "Avexir"},
+// { 6, 0x97, "Echelon"},
+// { 6, 0x98, "Edgewater Computer Systems"},
+// { 6, 0x19, "XMOS Semiconductor"},
+// { 6, 0x1a, "GENUSION"},
+   { 6, 0x9b, "Memory Corp NV"},
+// { 6, 0x1c, "SiliconBlue Technologies"},
+// { 6, 0x9d, "Rambus"},
+// { 6, 0x9e, "Andes Technology"},
+// { 6, 0x1f, "Coronis Systems"},
+// { 6, 0x20, "Achronix Semiconductor"},
+// { 6, 0xa1, "Siano Mobile Silicon"},
+// { 6, 0xa2, "Semtech"},
+// { 6, 0x23, "Pixelworks"},
+// { 6, 0xa4, "Gaisler Research AB"},
+// { 6, 0x25, "Teranetics"},
+// { 6, 0x26, "Toppan Printing"},
+// { 6, 0xa7, "Kingxcon"},
+   { 6, 0xa8, "SiS"},
+// { 6, 0x29, "I-O Data Device"},
+// { 6, 0x2a, "NDS Americas"},
+// { 6, 0xab, "Solomon Systech Limited"},
+// { 6, 0x2c, "On Demand Microelectronics"},
+// { 6, 0xad, "Amicus Wireless"},
+// { 6, 0xae, "SMARDTV SNC"},
+// { 6, 0x2f, "Comsys Communication"},
+// { 6, 0xb0, "Movidia"},
+// { 6, 0x31, "Javad GNSS"},
+// { 6, 0x32, "Montage Technology Group"},
+   { 6, 0xb3, "Trident"},
+   { 6, 0x34, "Super Talent"},
+// { 6, 0xb5, "Optichron"},
+// { 6, 0xb6, "Future Waves UK"},
+// { 6, 0x37, "SiBEAM"},
+// { 6, 0x38, "Inicore,"},
+// { 6, 0xb9, "Virident Systems"},
+// { 6, 0xba, "M2000"},
+// { 6, 0x3b, "ZeroG Wireless"},
+   { 6, 0xbc, "Gingle"},
+// { 6, 0x3d, "Space Micro"},
+// { 6, 0x3e, "Wilocity"},
+// { 6, 0xbf, "Novafora, Ic."},
+// { 6, 0x40, "iKoa"},
+   { 6, 0xc1, "ASint"},
+   { 6, 0xc2, "Ramtron"},
+// { 6, 0x43, "Plato Networks"},
+// { 6, 0xc4, "IPtronics AS"},
+// { 6, 0x45, "Infinite-Memories"},
+// { 6, 0x46, "Parade Technologies"},
+// { 6, 0xc7, "Dune Networks"},
+// { 6, 0xc8, "GigaDevice Semiconductor"},
+// { 6, 0x49, "Modu"},
+// { 6, 0x4a, "CEITEC"},
+// { 6, 0xcb, "Northrop Grumman"},
+// { 6, 0x4c, "XRONET"},
+// { 6, 0xcd, "Sicon Semiconductor AB"},
+// { 6, 0xce, "Atla Electronics"},
+   { 6, 0x4f, "TOPRAM"},
+// { 6, 0xd0, "Silego Technology"},
+   { 6, 0x51, "Kinglife"},
+// { 6, 0x52, "Ability Industries"},
+// { 6, 0xd3, "Silicon Power Computer & Communications"},
+// { 6, 0x54, "Augusta Technology"},
+// { 6, 0xd5, "Nantronics Semiconductors"},
+// { 6, 0xd6, "Hilscher Gesellschaft"},
+// { 6, 0x57, "Quixant"},
+// { 6, 0x58, "Percello"},
+// { 6, 0xd9, "NextIO"},
+// { 6, 0xda, "Scanimetrics"},
+// { 6, 0x5b, "FS-Semi Company"},
+// { 6, 0xdc, "Infinera"},
+   { 6, 0x5d, "SandForce"},
+   { 6, 0x5e, "Lexar Media"},
+// { 6, 0xdf, "Teradyne"},
+   { 6, 0xe0, "Memory Exchange Corp."},
+// { 6, 0x61, "Suzhou Smartek Electronics"},
+   { 6, 0x62, "Avantium"},
+// { 6, 0xe3, "ATP Electronics"},
+// { 6, 0x64, "Valens Semiconductor"},
+// { 6, 0xe5, "Agate Logic"},
+// { 6, 0xe6, "Netronome"},
+// { 6, 0x67, "Zenverge"},
+// { 6, 0x68, "N-trig"},
+// { 6, 0xe9, "SanMax Technologies"},
+// { 6, 0xea, "Contour Semiconductor"},
+   { 6, 0x6b, "TwinMOS"},
+   { 6, 0xec, "Silicon Systems"},
+// { 6, 0x6d, "V-Color Technology"},
+// { 6, 0x6e, "Certicom"},
+// { 6, 0xef, "JSC ICC Milandr"},
+// { 6, 0x70, "PhotoFast Global"},
+   { 6, 0xf1, "InnoDisk"},
+   { 6, 0xf2, "Muscle Power"},
+// { 6, 0x73, "Energy Micro"},
+// { 6, 0xf4, "Innofidei"},
+// { 6, 0x75, "CopperGate Communications"},
+// { 6, 0x76, "Holtek Semiconductor"},
+// { 6, 0xf7, "Myson Century"},
+// { 6, 0xf8, "FIDELIX"},
+// { 6, 0x79, "Red Digital Cinema"},
+// { 6, 0x7a, "Densbits Technology"},
+// { 6, 0xfb, "Zempro"},
+// { 6, 0x7c, "MoSys"},
+// { 6, 0xfd, "Provigent"},
+// { 6, 0xfe, "Triad Semiconductor"},
+// { 8, 0x01, "Siklu Communication"},
+// { 8, 0x02, "A Force Manufacturing"},
+   { 8, 0x83, "Strontium"},
+// { 8, 0x04, "Abilis Systems"},
+// { 8, 0x85, "Siglead"},
+// { 8, 0x86, "Ubicom"},
+// { 8, 0x07, "Unifosa"},
+// { 8, 0x08, "Stretch"},
+// { 8, 0x89, "Lantiq Deutschland"},
+// { 8, 0x8a, "Visipro."},
+   { 8, 0x0b, "EKMemory"},
+// { 8, 0x8c, "Microelectronics Institute ZTE"},
+// { 8, 0x0d, "Cognovo"},
+// { 8, 0x0e, "Carry Technology"},
+   { 8, 0x8f, "Nokia"},
+   { 8, 0x10, "King Tiger"},
+// { 8, 0x91, "Sierra Wireless"},
+   { 8, 0x92, "HT Micron"},
+   { 8, 0x13, "Albatron"},
+// { 8, 0x94, "Leica Geosystems AG"},
+// { 8, 0x15, "BroadLight"},
+// { 8, 0x16, "AEXEA"},
+// { 8, 0x97, "ClariPhy Communications"},
+// { 8, 0x98, "Green Plug"},
+// { 8, 0x19, "Design Art Networks"},
+// { 8, 0x1a, "Mach Xtreme Technology"},
+// { 8, 0x9b, "ATO Solutions"},
+// { 8, 0x1c, "Ramsta"},
+// { 8, 0x9d, "Greenliant Systems"},
+// { 8, 0x9e, "Teikon"},
+// { 8, 0x1f, "Antec Hadron"},
+// { 8, 0x20, "NavCom Technology"},
+// { 8, 0xa1, "Shanghai Fudan Microelectronics"},
+// { 8, 0xa2, "Calxeda"},
+// { 8, 0x23, "JSC EDC Electronics"},
+// { 8, 0xa4, "Kandit Technology"},
+// { 8, 0x25, "Ramos Technology"},
+// { 8, 0x26, "Goldenmars Technology"},
+// { 8, 0xa7, "XeL Technology"},
+// { 8, 0xa8, "Newzone"},
+   { 8, 0x29, "MercyPower"},
+// { 8, 0x2a, "Nanjing Yihuo Technology."},
+// { 8, 0xab, "Nethra Imaging"},
+// { 8, 0x2c, "SiTel Semiconductor BV"},
+// { 8, 0xad, "SolidGear"},
+   { 8, 0xae, "Topower"},
+// { 8, 0x2f, "Wilocity"},
+// { 8, 0xb0, "Profichip"},
+// { 8, 0x31, "Gerad Technologies"},
+   { 8, 0x32, "Ritek"},
+// { 8, 0xb3, "Gomos Technology Limited"},
+   { 8, 0x34, "Memoright"},
+// { 8, 0xb5, "D-Broad"},
+// { 8, 0xb6, "HiSilicon Technologies"},
+// { 8, 0x37, "Syndiant ."},
+// { 8, 0x38, "Enverv"},
+// { 8, 0xb9, "Cognex"},
+// { 8, 0xba, "Xinnova Technology"},
+   { 8, 0x3b, "Ultron"},
+// { 8, 0xbc, "Concord Idea"},
+// { 8, 0x3d, "AIM"},
+// { 8, 0x3e, "Lifetime Memory Products"},
+// { 8, 0xbf, "Ramsway"},
+// { 8, 0x40, "Recore Systems B.V."},
+// { 8, 0xc1, "Haotian Jinshibo Science Tech"},
+// { 8, 0xc2, "Being Advanced Memory"},
+// { 8, 0x43, "Adesto Technologies"},
+// { 8, 0xc4, "Giantec Semiconductor"},
+// { 8, 0x45, "HMD Electronics AG"},
+// { 8, 0x46, "Gloway International (HK)"},
+// { 8, 0xc7, "Kingcore"},
+// { 8, 0xc8, "Anucell Technology Holding"},
+// { 8, 0x49, "Accord Software & Systems Pvt."},
+// { 8, 0x4a, "Active-Semi"},
+// { 8, 0xcb, "Denso"},
+// { 8, 0x4c, "TLSI"},
+// { 8, 0xcd, "Shenzhen Daling Electronic"},
+// { 8, 0xce, "Mustang"},
+// { 8, 0x4f, "Orca Systems"},
+// { 8, 0xd0, "Passif Semiconductor"},
+// { 8, 0x51, "GigaDevice Semiconductor (Beijing)"},
+// { 8, 0x52, "Memphis Electronic"},
+// { 8, 0xd3, "Beckhoff Automation"},
+// { 8, 0x54, "Harmony Semiconductor Corp"},
+// { 8, 0xd5, "Air Computers SRL"},
+   { 8, 0xd6, "TMT Memory"},
+	 { 9, 0xff, ""}
+};
+
diff --git a/lib.c b/lib.c
index a2b829d..10d0046 100644
--- a/lib.c
+++ b/lib.c
@@ -35,10 +35,10 @@
 
 inline void reboot(void)
 {
-	
+
 	/* tell the BIOS to do a cold start */
 	*((unsigned short *)0x472) = 0x0;
-	
+
 	while(1)
 	{
 		outb(0xFE, 0x64);
@@ -171,7 +171,7 @@
  * Scroll the error message area of the screen as needed
  * Starts at line LINE_SCROLL and ends at line 23
  */
-void scroll(void) 
+void scroll(void)
 {
 	int i, j;
 	char *s, tmp;
@@ -245,7 +245,7 @@
         tty_print_line(y, x, text);
 }
 
-void itoa(char s[], int n) 
+void itoa(char s[], int n)
 {
   int i, sign;
 
@@ -284,7 +284,7 @@
 	}
 	for (i = 0 ; i < len; i++) {
 		*d++ = *s++;
-	} 
+	}
 }
 
 /*
@@ -351,7 +351,7 @@
 					continue;
 				}
 				if (k == 0 && flag == 0) {
-					continue;				
+					continue;
 				}
 				buf[i++] = k + '0';
 				val -= k * j;
@@ -497,7 +497,7 @@
 	ulong cs;
 	ulong eflag;
 };
-	
+
 /* Handle an interrupt */
 void inter(struct eregs *trap_regs)
 {
@@ -588,11 +588,11 @@
 	}
 }
 
-void set_cache(int val) 
+void set_cache(int val)
 {
 	switch(val) {
 	case 0:
-		cache_off();	
+		cache_off();
 		break;
 	case 1:
 		cache_on();
@@ -629,7 +629,7 @@
 
 	if ((c = get_key())) {
 		switch(c & 0x7f) {
-		case 1:	
+		case 1:
 			/* "ESC" key was pressed, bail out.  */
 			cprint(LINE_RANGE, COL_MID+23, "Halting... ");
 			reboot();
@@ -680,7 +680,7 @@
 		buf[i] = ' ';
 	}
 	buf[sizeof(buf)/sizeof(buf[0]) -1] = '\0';
-	
+
 	wait_keyup();
 	done = 0;
 	n = 0;
@@ -734,7 +734,7 @@
 		}
 		/* Don't allow anything to be entered after a suffix */
 		if (n > 0 && (
-			(buf[n-1] == 'p') || (buf[n-1] == 'g') || 
+			(buf[n-1] == 'p') || (buf[n-1] == 'g') ||
 			(buf[n-1] == 'm') || (buf[n-1] == 'k'))) {
 			buf[n] = ' ';
 		}
@@ -788,7 +788,7 @@
 {
 	static char sx[3];
 	static char sy[3];
-	
+
 	sx[0]='\0';
 	sy[0]='\0';
 	x++; y++;
@@ -805,7 +805,7 @@
 void serial_echo_init(void)
 {
 	int comstat, hi, lo, serial_div;
-	unsigned char lcr;	
+	unsigned char lcr;
 
 	/* read the Divisor Latch */
 	comstat = serial_echo_inb(UART_LCR);
@@ -841,7 +841,7 @@
 {
 	int len = 0;
 	int i = 1;
-	
+
 	while(i <= val)
 	{
 		len++;
@@ -849,7 +849,7 @@
 	}
 
 	return len;
-		
+
 }
 
 
@@ -881,7 +881,7 @@
  */
 struct ascii_map_str ser_map[] =
 /*ascii keycode     ascii  keycode*/
-{ 
+{
   /* Special cases come first so I can leave
    * their ``normal'' mapping in the table,
    * without it being activated.
diff --git a/linuxbios.c b/linuxbios.c
index 75d9181..b70d7db 100644
--- a/linuxbios.c
+++ b/linuxbios.c
@@ -25,7 +25,7 @@
 			sum -= 0xFFFF;
 		length -= 1;
 		addr = ptr +1;
-		
+
 	}
 	len = length >> 1;
 	ptr = addr;
@@ -50,7 +50,7 @@
 			sum -= 0xFFFF;
 	}
 	return (~sum) & 0xFFFF;
-	
+
 }
 
 #define for_each_lbrec(head, rec) \
@@ -58,8 +58,8 @@
 		(((char *)rec) < (((char *)head) + sizeof(*head) + head->table_bytes))  && \
 		(rec->size >= 1) && \
 		((((char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) + head->table_bytes)); \
-		rec = (struct lb_record *)(((char *)rec) + rec->size)) 
-		
+		rec = (struct lb_record *)(((char *)rec) + rec->size))
+
 
 static int count_lb_records(struct lb_header *head)
 {
@@ -85,7 +85,7 @@
 			continue;
 		if (ip_compute_csum((unsigned char *)head, sizeof(*head)) != 0)
 			continue;
-		if (ip_compute_csum((unsigned char *)recs, head->table_bytes) 
+		if (ip_compute_csum((unsigned char *)recs, head->table_bytes)
 			!= head->table_checksum)
 			continue;
 		if (count_lb_records(head) != head->table_entries)
@@ -117,7 +117,7 @@
 	struct lb_memory *mem;
 	struct lb_forward *forward;
 	int i, entries;
-	
+
 	head = find_lb_table();
 	if (!head) {
 		return 0;
diff --git a/linuxbios_tables.h b/linuxbios_tables.h
index 38f2038..4ea484f 100644
--- a/linuxbios_tables.h
+++ b/linuxbios_tables.h
@@ -8,7 +8,7 @@
  * is expected to be information that cannot be discovered by
  * other means, such as quering the hardware directly.
  *
- * All of the information should be Position Independent Data.  
+ * All of the information should be Position Independent Data.
  * That is it should be safe to relocated any of the information
  * without it's meaning/correctnes changing.   For table that
  * can reasonably be used on multiple architectures the data
@@ -64,7 +64,7 @@
 	uint32_t type;
 #define LB_MEM_RAM      1
 #define LB_MEM_RESERVED 2
-	
+
 };
 
 struct lb_memory {
diff --git a/main.c b/main.c
index da09dc9..5a8a285 100644
--- a/main.c
+++ b/main.c
@@ -8,7 +8,7 @@
  * Released under version 2 of the Gnu Public License.
  * By Chris Brady
  */
- 
+
 #include "stdint.h"
 #include "stddef.h"
 #include "test.h"
@@ -57,8 +57,8 @@
 	{1, 32,  3,   6, 0, "[Moving inversions, 1s & 0s Parallel]  "},
 	{1, 32,  5,   3, 0, "[Moving inversions, 8 bit pattern]     "},
 	{1, 32,  6,  30, 0, "[Moving inversions, random pattern]    "},
-	{1, 32,  7,  81, 0, "[Block move]                           "}, 
-	{1,  1,  8,   3, 0, "[Moving inversions, 32 bit pattern]    "}, 
+	{1, 32,  7,  81, 0, "[Block move]                           "},
+	{1,  1,  8,   3, 0, "[Moving inversions, 32 bit pattern]    "},
 	{1, 32,  9,  48, 0, "[Random number sequence]               "},
   {1, 32, 10,   6, 0, "[Modulo 20, Random pattern]            "},
 	{1, 1,  11, 240, 0, "[Bit fade test, 2 patterns]            "},
@@ -217,7 +217,7 @@
 
 	/* We use a lock to insure that only one CPU at a time jumps to
 	 * the new code. Some of the startup stuff is not thread safe! */
-  spin_lock(&barr->mutex);   
+  spin_lock(&barr->mutex);
 
 	/* Jump to the start address */
 	goto *ja;
@@ -225,21 +225,21 @@
 
 /* Switch from the boot stack to the main stack. First the main stack
  * is allocated, then the contents of the boot stack are copied, then
- * ESP is adjusted to point to the new stack.  
+ * ESP is adjusted to point to the new stack.
  */
 static void
 switch_to_main_stack(unsigned cpu_num)
 {
 	extern uintptr_t boot_stack;
-	extern uintptr_t boot_stack_top; 
+	extern uintptr_t boot_stack_top;
 	uintptr_t *src, *dst;
 	int offs;
 	uint8_t * stackAddr, *stackTop;
-   
+
 	stackAddr = (uint8_t *) &stacks[cpu_num][0];
 
 	stackTop  = stackAddr + STACKSIZE;
-   
+
 	src = (uintptr_t*)&boot_stack_top;
 	dst = (uintptr_t*)stackTop;
 	do {
@@ -249,9 +249,9 @@
 
 	offs = (uint8_t *)&boot_stack_top - stackTop;
 	__asm__ __volatile__ (
-	"subl %%eax, %%esp" 
+	"subl %%eax, %%esp"
 		: /*no output*/
-		: "a" (offs) : "memory" 
+		: "a" (offs) : "memory"
 	);
 }
 
@@ -272,7 +272,7 @@
 /* command line passing using the 'old' boot protocol */
 #define MK_PTR(seg,off) ((void*)(((unsigned long)(seg) << 4) + (off)))
 #define OLD_CL_MAGIC_ADDR ((unsigned short*) MK_PTR(INITSEG,0x20))
-#define OLD_CL_MAGIC 0xA33F 
+#define OLD_CL_MAGIC 0xA33F
 #define OLD_CL_OFFSET_ADDR ((unsigned short*) MK_PTR(INITSEG,0x22))
 
 static void parse_command_line(void)
@@ -354,7 +354,7 @@
 		    cp += 8;
 		    if (cp[0] == '0' && toupper(cp[1]) == 'X') cp += 2;
 		    while (*cp && *cp != ' ' && isxdigit(*cp)) {
-			i = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10; 
+			i = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10;
 			bin_mask = bin_mask * 16 + i;
 			cp++;
 		    }
@@ -362,7 +362,7 @@
 		    bin_mask |= 1;
 		    for (i=0; i<32; i++) {
 			if (((bin_mask>>i) & 1) == 0) {
-			     cpu_mask[i] = 0; 
+			     cpu_mask[i] = 0;
 			}
 		    }
 		}
@@ -436,7 +436,7 @@
 
 		/* Set defaults and initialize variables */
 		set_defaults();
-	
+
 		/* Setup base address for testing, 1 MB */
 		win0_start = 0x100;
 
@@ -447,7 +447,7 @@
 			high_test_adr = 0x2000000;
 	        } else {
 			high_test_adr = 0x300000;
-		} 
+		}
 		win1_end = (high_test_adr >> 12);
 
 		/* Adjust the map to not test the page at 939k,
@@ -480,7 +480,7 @@
 	/* A barrier to insure that all of the CPUs are done with startup */
 	barrier();
 	btrace(my_cpu_num, __LINE__, "1st Barr  ", 1, my_cpu_num, my_cpu_ord);
-	
+
 
 	/* Setup Memory Management and measure memory speed, we do it here
 	 * because we need all of the available CPUs */
@@ -547,9 +547,9 @@
 		continue;
 	    }
             /* Skip single CPU tests if we are using only one CPU */
-            if (tseq[test].cpu_sel == -1 && 
+            if (tseq[test].cpu_sel == -1 &&
                     (num_cpus == 1 || cpu_mode != CPM_ALL)) {
-                test++; 
+                test++;
                 continue;
             }
 
@@ -618,7 +618,7 @@
 			if (my_cpu_ord >= tseq[test].cpu_sel) {
 				run = 0;
 			}
-			/* Set the master CPU to the highest CPU number 
+			/* Set the master CPU to the highest CPU number
 			 * that has been selected */
 			if (act_cpus < tseq[test].cpu_sel) {
 				mstr_cpu = act_cpus-1;
@@ -742,10 +742,10 @@
 		}
 		break;
 	    case CPM_ALL:
-	      if (tseq[test].cpu_sel == -1) 
+	      if (tseq[test].cpu_sel == -1)
 	      	{
 			    /* Do the same test for each CPU */
-			    if (++cpu_sel >= act_cpus) 
+			    if (++cpu_sel >= act_cpus)
 			    	{
 				cpu_sel = 0;
 			        next_test();
@@ -759,23 +759,23 @@
 	    btrace(my_cpu_num, __LINE__, "Next_CPU  ",1,cpu_sel,test);
 
 	    /* If this was the last test then we finished a pass */
-	  if (pass_flag) 
+	  if (pass_flag)
 	  	{
 			pass_flag = 0;
-			
+
 			v->pass++;
-			
+
 			dprint(LINE_INFO, 49, v->pass, 5, 0);
 			find_ticks_for_pass();
 			ltest = -1;
-			
-			if (v->ecount == 0) 
+
+			if (v->ecount == 0)
 				{
 			    /* If onepass is enabled and we did not get any errors
 			     * reboot to exit the test */
 			    if (onepass) {	reboot();   }
 			    if (!btflag) cprint(LINE_MSG, COL_MSG-8, "** Pass complete, no errors, press Esc to exit **");
-					if(BEEP_END_NO_ERROR) 
+					if(BEEP_END_NO_ERROR)
 						{
 							beep(1000);
 							beep(2000);
@@ -840,13 +840,13 @@
 	  if ((ulong)&_start > LOW_TEST_ADR) {
 		/* Relocated so we need to test all selected lower memory */
 		v->map[0].start = mapping(v->plim_lower);
-		
+
 		/* Good 'ol Legacy USB_WAR */
-		if (v->map[0].start < (ulong*)0x500) 
+		if (v->map[0].start < (ulong*)0x500)
 		{
     	v->map[0].start = (ulong*)0x500;
 		}
-		
+
 		cprint(LINE_PAT, COL_MID+25, " R");
 	    } else {
 		cprint(LINE_PAT, COL_MID+25, "  ");
@@ -862,7 +862,7 @@
 	    cprint(LINE_RANGE, COL_MID+30, " of ");
 	    aprint(LINE_RANGE, COL_MID+34, v->selected_pages);
 	}
-	
+
 	switch(tseq[test].pat) {
 
 	/* Do the testing according to the selected pattern */
@@ -888,13 +888,13 @@
 		s_barrier();
 		movinv1(c_iter,p1,p2,my_ord);
 		BAILOUT;
-	
+
 		/* Switch patterns */
 		s_barrier();
 		movinv1(c_iter,p2,p1,my_ord);
 		BAILOUT;
 		break;
-		
+
 	case 5: /* Moving inversions, 8 bit walking ones and zeros (test #5) */
 		p0 = 0x80;
 		for (i=0; i<8; i++, p0=p0>>1) {
@@ -903,14 +903,14 @@
 			s_barrier();
 			movinv1(c_iter,p1,p2, my_ord);
 			BAILOUT;
-	
+
 			/* Switch patterns */
 			s_barrier();
 			movinv1(c_iter,p2,p1, my_ord);
 			BAILOUT
 		}
 		break;
-		
+
 	case 6: /* Random Data (test #6) */
 		/* Seed the random number generator */
 		if (my_ord == mstr_cpu) {
@@ -1050,7 +1050,7 @@
 }
 
 /* Compute number of SPINSZ chunks being tested */
-int find_chunks(int tst) 
+int find_chunks(int tst)
 {
 	int i, j, sg, wmax, ch;
 	struct pmap twin={0,0};
@@ -1119,7 +1119,7 @@
 	i = 0;
 	while (tseq[i].cpu_sel != 0) {
 		/* Skip tests 2 and 4 if we are using 1 cpu */
-		if (act_cpus == 1 && (i == 2 || i == 4)) { 
+		if (act_cpus == 1 && (i == 2 || i == 4)) {
 		    i++;
 		    continue;
 		}
@@ -1260,11 +1260,11 @@
 
 		cprint(LINE_SCROLL+(2*i+1), 44, "i=");
 		hprint(LINE_SCROLL+(2*i+1), 46, i);
-		
-		cprint(LINE_SCROLL+(2*i+2), 0, 
+
+		cprint(LINE_SCROLL+(2*i+2), 0,
 			"                                        "
 			"                                        ");
-		cprint(LINE_SCROLL+(2*i+3), 0, 
+		cprint(LINE_SCROLL+(2*i+3), 0,
 			"                                        "
 			"                                        ");
 #endif
@@ -1279,7 +1279,7 @@
 		hprint(LINE_SCROLL+(sg+1), 32, end);
 		hprint(LINE_SCROLL+(sg+1), 42, mapping(start));
 		hprint(LINE_SCROLL+(sg+1), 52, emapping(end));
-		cprint(LINE_SCROLL+(sg+2), 0, 
+		cprint(LINE_SCROLL+(sg+2), 0,
 			"                                        "
 			"                                        ");
 #endif
diff --git a/make_buildnum.sh b/make_buildnum.sh
index 93927cd..692d359 100755
--- a/make_buildnum.sh
+++ b/make_buildnum.sh
@@ -1,20 +1,20 @@
-#!sh  
-# FILE: make_buildnum.sh  
-version="`sed  's/^ *//' major_version`"  
-old="`sed  's/^ *//' build.number` +1"  
-echo $old | bc > build.number.temp  
-mv build.number.temp build.number  
-#versión..  
-echo "$version`sed  's/^ *//' build.number` - `date`" > version.number  
-#header  
-echo "#ifndef BUILD_NUMBER_STR" > build_number.h  
-echo "#define BUILD_NUMBER_STR \"`sed  's/^ *//' build.number`\"" >> build_number.h  
-echo "#endif" >> build_number.h  
-  
-echo "#ifndef VERSION_STR" >> build_number.h  
-echo "#define VERSION_STR \"$version`sed  's/^ *//' build.number` - `date`\"" >> build_number.h  
-echo "#endif" >> build_number.h  
-  
-echo "#ifndef VERSION_STR_SHORT" >> build_number.h  
-echo "#define VERSION_STR_SHORT \"$version`sed  's/^ *//' build.number`\"" >> build_number.h  
+#!sh
+# FILE: make_buildnum.sh
+version="`sed  's/^ *//' major_version`"
+old="`sed  's/^ *//' build.number` +1"
+echo $old | bc > build.number.temp
+mv build.number.temp build.number
+#versión..
+echo "$version`sed  's/^ *//' build.number` - `date`" > version.number
+#header
+echo "#ifndef BUILD_NUMBER_STR" > build_number.h
+echo "#define BUILD_NUMBER_STR \"`sed  's/^ *//' build.number`\"" >> build_number.h
+echo "#endif" >> build_number.h
+
+echo "#ifndef VERSION_STR" >> build_number.h
+echo "#define VERSION_STR \"$version`sed  's/^ *//' build.number` - `date`\"" >> build_number.h
+echo "#endif" >> build_number.h
+
+echo "#ifndef VERSION_STR_SHORT" >> build_number.h
+echo "#define VERSION_STR_SHORT \"$version`sed  's/^ *//' build.number`\"" >> build_number.h
 echo "#endif" >> build_number.h
diff --git a/makeiso.sh b/makeiso.sh
index ae5a8c9..ea5ce65 100755
--- a/makeiso.sh
+++ b/makeiso.sh
@@ -9,12 +9,12 @@
 	elif [ ! -x $(which $X) ]; then
 		echo "makeiso.sh error: $X is not executable." >&2
 		exit 1
-	fi 
+	fi
 done
 
 #check to see if memtest.bin is present
-if [ ! -w memtest.bin ]; then 
-	echo "makeiso.sh error: cannot find memtest.bin, did you compile it?" >&2 
+if [ ! -w memtest.bin ]; then
+	echo "makeiso.sh error: cannot find memtest.bin, did you compile it?" >&2
 	exit 1
 fi
 
diff --git a/memsize.c b/memsize.c
index d4e0790..c9e9649 100644
--- a/memsize.c
+++ b/memsize.c
@@ -89,7 +89,7 @@
 		if (i != j) {
 			struct pmap temp;
 			temp = v->pmap[i];
-			memmove(&v->pmap[j], &v->pmap[j+1], 
+			memmove(&v->pmap[j], &v->pmap[j+1],
 				(i -j)* sizeof(temp));
 			v->pmap[j] = temp;
 		}
@@ -152,20 +152,20 @@
 			v->pmap[n].end = end >> 12;
 			v->test_pages += v->pmap[n].end - v->pmap[n].start;
 			n++;
-#if 0			
+#if 0
 	 		int epmap = 0;
 	 		int lpmap = 0;
 	 		if(n > 12) { epmap = 34; lpmap = -12; }
 			hprint (11+n+lpmap,0+epmap,v->pmap[n-1].start);
 			hprint (11+n+lpmap,10+epmap,v->pmap[n-1].end);
 			hprint (11+n+lpmap,20+epmap,v->pmap[n-1].end - v->pmap[n-1].start);
-			dprint (11+n+lpmap,30+epmap,nm[i].type,0,0);	
-#endif				
+			dprint (11+n+lpmap,30+epmap,nm[i].type,0,0);
+#endif
 		}
 	}
 	v->msegs = n;
 }
-	
+
 static void memsize_801(void)
 {
 	ulong mem_size;
@@ -193,7 +193,7 @@
 /*
  * Sanitize the BIOS e820 map.
  *
- * Some e820 responses include overlapping entries.  The following 
+ * Some e820 responses include overlapping entries.  The following
  * replaces the original e820 map with a new one, removing overlaps.
  *
  */
diff --git a/memtest.bin.lds b/memtest.bin.lds
index 702cdb1..7afb57b 100644
--- a/memtest.bin.lds
+++ b/memtest.bin.lds
@@ -6,9 +6,9 @@
 	. = 0;
 	.bootsect : { *(.bootsect) }
 	.setup : { *(.setup) }
-	.memtest : { 
+	.memtest : {
 		_start = . ;
-		*(.data) 
+		*(.data)
 		_end = . ;
 	}
 	_syssize = (_end - _start + 15) >> 4;
diff --git a/memtest.lds b/memtest.lds
index bbb190a..efe0ac5 100644
--- a/memtest.lds
+++ b/memtest.lds
@@ -1,7 +1,7 @@
 OUTPUT_FORMAT("elf32-i386");
 OUTPUT_ARCH(i386);
 
-ENTRY(_start); 
+ENTRY(_start);
 SECTIONS {
 	. = 0x10000;
 	_start = . ;
diff --git a/memtest_shared.lds b/memtest_shared.lds
index 603f012..af346bb 100644
--- a/memtest_shared.lds
+++ b/memtest_shared.lds
@@ -1,7 +1,7 @@
 OUTPUT_FORMAT("elf32-i386");
 OUTPUT_ARCH(i386);
 
-ENTRY(startup_32); 
+ENTRY(startup_32);
 SECTIONS {
 	. = 0;
 	.text : {
@@ -29,9 +29,9 @@
 
 	. = ALIGN(4);
 	.data : {
-		 _data = .; 
-		*(.data) 
-		*(.data.*) 
+		 _data = .;
+		*(.data)
+		*(.data.*)
 	}
 	.got : {
 		*(.got.plt)
@@ -39,15 +39,15 @@
 		_edata = . ;
 	}
 	. = ALIGN(4);
-	.bss : { 
+	.bss : {
 		_bss = .;
 		*(.dynbss)
-		*(.bss) 
-		*(.bss.*) 
-		*(COMMON) 
+		*(.bss)
+		*(.bss.*)
+		*(COMMON)
 		/* _end must be at least 256 byte aligned */
-		. = ALIGN(256); 
+		. = ALIGN(256);
 		_end = .;
 	}
-	/DISCARD/ : { *(*) }	
+	/DISCARD/ : { *(*) }
 }
diff --git a/msr.h b/msr.h
index af873a0..75d0f8a 100644
--- a/msr.h
+++ b/msr.h
@@ -6,8 +6,8 @@
  * Note: the rd* operations modify the parameters directly (without using
  * pointer indirection), this allows gcc to optimize better
  */
- 
-#define __FIXUP_ALIGN ".align 8" 
+
+#define __FIXUP_ALIGN ".align 8"
 #define __FIXUP_WORD ".quad"
 #define EFAULT	14 /* Bad address */
 
@@ -29,7 +29,7 @@
          ".previous\n" \
          : "=a" (val1), "=d" (val2), "=&r" (_rc) \
 				 : "c" (msr), "2" (0), "i" (-EFAULT)); \
-				 	_rc; })				 	
+				 	_rc; })
 */
 
 #define wrmsr(msr,val1,val2) \
diff --git a/mt86+_loader b/mt86+_loader
index 030ea1a..0cf81a4 100644
--- a/mt86+_loader
+++ b/mt86+_loader
Binary files differ
diff --git a/mt86+_loader.asm b/mt86+_loader.asm
index 8472262..c84fe78 100644
--- a/mt86+_loader.asm
+++ b/mt86+_loader.asm
@@ -46,7 +46,7 @@
 	; loaded part begins here (set CS so that IP is 100h here)
 
 start:	; entry point	; if you use obj + linker, use "..start:"
-  mov    ah, 01h      
+  mov    ah, 01h
   mov    bh, 00h
   mov   cx, 2000h
   int    10h
diff --git a/patn.c b/patn.c
index 0c5b490..57262e9 100644
--- a/patn.c
+++ b/patn.c
@@ -9,7 +9,7 @@
  * ----------------------------------------------------
  * MemTest86+ V1.60 Specific code (GPL V2.0)
  * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
- * http://www.x86-secret.com - http://www.memtest.org 
+ * http://www.x86-secret.com - http://www.memtest.org
  */
 
 
diff --git a/pci.c b/pci.c
index 075a07f..2d24453 100644
--- a/pci.c
+++ b/pci.c
@@ -43,7 +43,7 @@
 		if(reg < 256){
 			outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
 		}else{
-			outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);		
+			outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
 		}
 		switch(len) {
 		case 1:  *value = inb(0xCFC + (reg & 3)); result = 0; break;
@@ -74,14 +74,14 @@
 		return -1;
 
 	result = -1;
-	
-	switch(pci_conf_type) 
+
+	switch(pci_conf_type)
 	{
 		case PCI_CONF_TYPE_1:
 			if(reg < 256){
 				outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
 			}else{
-				outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);		
+				outl(PCI_CONF3_ADDRESS(bus, dev, fn, reg), 0xCF8);
 			}
 			switch(len) {
 			case 1:  outb(value, 0xCFC + (reg & 3)); result = 0; break;
@@ -92,7 +92,7 @@
 		case PCI_CONF_TYPE_2:
 			outb(0xF0 | (fn << 1), 0xCF8);
 			outb(bus, 0xCFA);
-	
+
 			switch(len) {
 			case 1: outb(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
 			case 2: outw(value, PCI_CONF2_ADDRESS(dev, reg)); result = 0; break;
@@ -127,10 +127,10 @@
 {
 	unsigned char tmpCFB;
 	unsigned int  tmpCF8;
-	
+
 	if (cpu_id.vend_id.char_array[0] == 'A' && cpu_id.vers.bits.family == 0xF) {
 			pci_conf_type = PCI_CONF_TYPE_1;
-			return 0;		
+			return 0;
 	} else {
 			/* Check if configuration type 1 works. */
 			pci_conf_type = PCI_CONF_TYPE_1;
@@ -144,9 +144,9 @@
 				return 0;
 			}
 			outl(tmpCF8, 0xCF8);
-		
+
 			/* Check if configuration type 2 works. */
-			
+
 			pci_conf_type = PCI_CONF_TYPE_2;
 			outb(0x00, 0xCFB);
 			outb(0x00, 0xCF8);
@@ -154,7 +154,7 @@
 			if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 && (pci_sanity_check() == 0)) {
 				outb(tmpCFB, 0xCFB);
 				return 0;
-				
+
 	}
 
 	outb(tmpCFB, 0xCFB);
@@ -162,7 +162,7 @@
 	/* Nothing worked return an error */
 	pci_conf_type = PCI_CONF_TYPE_NONE;
 	return -1;
-	
+
 	}
 }
 
diff --git a/pci.h b/pci.h
index f21c478..b93be63 100644
--- a/pci.h
+++ b/pci.h
@@ -1,9 +1,9 @@
 #ifndef MEMTEST_PCI_H
 #define MEMTEST_PCI_H
 
-int pci_conf_read(unsigned bus, unsigned dev, unsigned fn, unsigned reg, 
+int pci_conf_read(unsigned bus, unsigned dev, unsigned fn, unsigned reg,
 	unsigned len, unsigned long *value);
-int pci_conf_write(unsigned bus, unsigned dev, unsigned fn, unsigned reg, 
+int pci_conf_write(unsigned bus, unsigned dev, unsigned fn, unsigned reg,
 	unsigned len, unsigned long value);
 int pci_init(void);
 
@@ -34,7 +34,7 @@
 #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
 #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
 #define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
-#define  PCI_STATUS_DEVSEL_FAST	0x000	
+#define  PCI_STATUS_DEVSEL_FAST	0x000
 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
 #define  PCI_STATUS_DEVSEL_SLOW 0x400
 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
@@ -63,8 +63,8 @@
 
 /*
  * Base addresses specify locations in memory or I/O space.
- * Decoded size can be determined by writing a value of 
- * 0xffffffff to the register, and reading it back.  Only 
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
  * 1 bits are decoded.
  */
 #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
diff --git a/random.c b/random.c
index 69dd140..2fb1bc3 100644
--- a/random.c
+++ b/random.c
@@ -32,7 +32,7 @@
    int me;
 
    me = cpu*16;
-   SEED_X[me] = seed1;   
+   SEED_X[me] = seed1;
    SEED_Y[me] = seed2;
 }
 
diff --git a/reloc.c b/reloc.c
index 1b80731..085b231 100644
--- a/reloc.c
+++ b/reloc.c
@@ -27,7 +27,7 @@
      bootstrap relocation instead of general-purpose relocation.  */
 #define RTLD_BOOTSTRAP
 
-struct link_map 
+struct link_map
 {
 	ElfW(Addr) l_addr;  /* Current load address */
 	ElfW(Addr) ll_addr; /* Last load address */
@@ -132,7 +132,7 @@
 {
 	if (! dyn)
 		return;
-	
+
 	while (dyn->d_tag != DT_NULL)
 	{
 		if (dyn->d_tag < DT_NUM)
@@ -147,8 +147,8 @@
 			assert (! "bad dynamic tag");
 		++dyn;
 	}
-	
-	if (info[DT_PLTGOT] != NULL) 
+
+	if (info[DT_PLTGOT] != NULL)
 		info[DT_PLTGOT]->d_un.d_ptr += l_addr;
 	if (info[DT_STRTAB] != NULL)
 		info[DT_STRTAB]->d_un.d_ptr += l_addr;
@@ -199,7 +199,7 @@
 
 	const ElfW(Sym) *const symtab =
 		(const void *) map->l_info[DT_SYMTAB]->d_un.d_ptr;
-	
+
 	for (; r < end; ++r) {
 		elf_machine_rel (map, r, &symtab[ELFW(R_SYM) (r->r_info)],
 			(void *) (map->l_addr + r->r_offset));
@@ -226,32 +226,32 @@
 
 	/* Figure out the run-time load address of the dynamic linker itself.  */
 	last_load_address = map.l_addr = elf_machine_load_address();
-	
+
 	/* Read our own dynamic section and fill in the info array.  */
 	map.l_ld = (void *)map.l_addr + elf_machine_dynamic();
 
 	elf_get_dynamic_info (map.l_ld, map.l_addr - map.ll_addr, map.l_info);
 
 	/* Relocate ourselves so we can do normal function calls and
-	 * data access using the global offset table.  
+	 * data access using the global offset table.
 	 */
 #if !ELF_MACHINE_NO_REL
-	elf_dynamic_do_rel(&map, 
+	elf_dynamic_do_rel(&map,
 		map.l_info[DT_REL]->d_un.d_ptr,
 		map.l_info[DT_RELSZ]->d_un.d_val);
 	if (map.l_info[DT_PLTREL]->d_un.d_val == DT_REL) {
-		elf_dynamic_do_rel(&map, 
+		elf_dynamic_do_rel(&map,
 			map.l_info[DT_JMPREL]->d_un.d_ptr,
 			map.l_info[DT_PLTRELSZ]->d_un.d_val);
 	}
 #endif
 
 #if !ELF_MACHINE_NO_RELA
-	elf_dynamic_do_rela(&map, 
+	elf_dynamic_do_rela(&map,
 		map.l_info[DT_RELA]->d_un.d_ptr,
 		map.l_info[DT_RELASZ]->d_un.d_val);
 	if (map.l_info[DT_PLTREL]->d_un.d_val == DT_RELA) {
-		elf_dynamic_do_rela(&map, 
+		elf_dynamic_do_rela(&map,
 			map.l_info[DT_JMPREL]->d_un.d_ptr,
 			map.l_info[DT_PLTRELSZ]->d_un.d_val);
 	}
diff --git a/screen_buffer.c b/screen_buffer.c
index f9e01be..a301988 100644
--- a/screen_buffer.c
+++ b/screen_buffer.c
@@ -11,7 +11,7 @@
 #define SCREEN_Y 25
 #define Y_SIZE SCREEN_Y
 /*
- * X-size should by one of by screen size, 
+ * X-size should by one of by screen size,
  * so that there is room for ending '\0'
  */
 #define X_SIZE SCREEN_X+1
@@ -62,7 +62,7 @@
     }
 }
 
-void tty_print_region(const int pi_top, 
+void tty_print_region(const int pi_top,
                       const int pi_left,
                       const int pi_bottom,
                       const int pi_right)
@@ -72,12 +72,12 @@
 
     for (y=pi_top; y < pi_bottom; ++y){
         CHECK_BOUNDS(y, pi_right);
-        
+
         tmp = screen_buf[y][pi_right];
         screen_buf[y][pi_right] = '\0';
 
         CHECK_BOUNDS(y, pi_left);
-        ttyprint(y, pi_left, &(screen_buf[y][pi_left]));                
+        ttyprint(y, pi_left, &(screen_buf[y][pi_left]));
 
         screen_buf[y][pi_right] = tmp;
     }
@@ -105,7 +105,7 @@
 void tty_print_screen(void)
 {
 #ifdef SCRN_DEBUG
-    int i; 
+    int i;
 
     for (i=0; i < SCREEN_Y; ++i)
         ttyprint(i,0, padding);
@@ -121,7 +121,7 @@
     ttyprint(0,0, padding);
 #endif /* SCRN_DEBUG */
 
-    ttyprint(0,35, pstr);        
-    
+    ttyprint(0,35, pstr);
+
     while(1);
 }
diff --git a/screen_buffer.h b/screen_buffer.h
index 8ceba03..9a2e245 100644
--- a/screen_buffer.h
+++ b/screen_buffer.h
@@ -1,7 +1,7 @@
-/* --*- C -*-- 
- * 
+/* --*- C -*--
+ *
  * By Jani Averbach, Jaa@iki.fi, 2001
- * 
+ *
  * Released under version 2 of the Gnu Public License.
  *
  */
diff --git a/serial.h b/serial.h
index 0261073..a8a0f56 100644
--- a/serial.h
+++ b/serial.h
@@ -2,10 +2,10 @@
  * include/linux/serial.h
  *
  * Copyright (C) 1992, 1994 by Theodore Ts'o.
- * 
- * Redistribution of this file is permitted under the terms of the GNU 
+ *
+ * Redistribution of this file is permitted under the terms of the GNU
  * Public License (GPL)
- * 
+ *
  * These are the UART port assignments, expressed as offsets from the base
  * register.  These assignments should hold for any serial port based on
  * a 8250, 16450, or 16550(A).
@@ -56,8 +56,8 @@
 
 /*
  * These are the definitions for the Line Control Register
- * 
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  */
 #define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
diff --git a/setup.S b/setup.S
index f80875b..85592ad 100644
--- a/setup.S
+++ b/setup.S
@@ -13,7 +13,7 @@
 .section ".setup", "ax", @progbits
 .globl start
 start:
-# ok, the read went well 
+# ok, the read went well
 # now we want to move to protected mode ...
 
 
@@ -22,7 +22,7 @@
 	outb	%al, $0x70
 
 # The system will move itself to its rightful place.
-# reload the segment registers and the stack since the 
+# reload the segment registers and the stack since the
 # APs also execute this code
 #ljmp	$INITSEG, $(reload - start + 0x200)
 reload:
@@ -48,7 +48,7 @@
      	/* skip the port92 code if it's unimplemented (read returns 0xff) */
      	cmpb	$0xff, %al
      	jz	alt_a20_done
-     	
+
      	/* set or clear bit1, the ALT_A20_GATE bit */
      	movb	4(%esp), %ah
      	testb	%ah, %ah
@@ -67,10 +67,10 @@
 # end from grub-a20.patch
 
 	call    empty_8042
-	
+
 	movb	$0xD1, %al	# command write
 	outb	%al, $0x64
-	call    empty_8042	
+	call    empty_8042
 
 	movb	$0xDF, %al	# A20 on
 	outb	%al, $0x60
@@ -110,7 +110,7 @@
 	call	delay
 	inb	$0x60, %al	# read it
 	jmp	empty_8042
-	
+
 no_output:
 	testb	$2, %al		# is input buffer full?
 	jnz	empty_8042	# yes - loop
diff --git a/smp.c b/smp.c
index 48fbb09..c55bff4 100644
--- a/smp.c
+++ b/smp.c
@@ -63,16 +63,16 @@
                 barr->st1.slock = 0;   /* Hold up any processes re-entering */
                 barr->st2.slock = 1;   /* Release the other processes */
                 barr->count++;
-                spin_unlock(&barr->lck); 
+                spin_unlock(&barr->lck);
         } else {
-                spin_unlock(&barr->lck); 
+                spin_unlock(&barr->lck);
                 spin_wait(&barr->st2);	/* wait for peers to arrive */
-                spin_lock(&barr->lck);   
-                if (++barr->count == barr->maxproc) { 
-                        barr->st1.slock = 1; 
-                        barr->st2.slock = 0; 
+                spin_lock(&barr->lck);
+                if (++barr->count == barr->maxproc) {
+                        barr->st1.slock = 1;
+                        barr->st2.slock = 0;
                 }
-                spin_unlock(&barr->lck); 
+                spin_unlock(&barr->lck);
         }
 }
 
@@ -87,16 +87,16 @@
                 barr->s_st1.slock = 0;   /* Hold up any processes re-entering */
                 barr->s_st2.slock = 1;   /* Release the other processes */
                 barr->s_count++;
-                spin_unlock(&barr->s_lck); 
+                spin_unlock(&barr->s_lck);
         } else {
-                spin_unlock(&barr->s_lck); 
+                spin_unlock(&barr->s_lck);
                 spin_wait(&barr->s_st2);	/* wait for peers to arrive */
-                spin_lock(&barr->s_lck);   
-                if (++barr->s_count == barr->s_maxproc) { 
-                        barr->s_st1.slock = 1; 
-                        barr->s_st2.slock = 0; 
+                spin_lock(&barr->s_lck);
+                if (++barr->s_count == barr->s_maxproc) {
+                        barr->s_st1.slock = 1;
+                        barr->s_st2.slock = 0;
                 }
-                spin_unlock(&barr->s_lck); 
+                spin_unlock(&barr->s_lck);
         }
 }
 
@@ -119,20 +119,20 @@
    *((volatile uint32_t *)addr) = val;
 }
 
-static void inline 
+static void inline
 APIC_WRITE(unsigned reg, uint32_t val)
 {
    APIC[reg][0] = val;
 }
 
-static inline uint32_t 
+static inline uint32_t
 APIC_READ(unsigned reg)
 {
    return APIC[reg][0];
 }
 
 
-static void 
+static void
 SEND_IPI(unsigned apic_id, unsigned trigger, unsigned level, unsigned mode,
 	    uint8_t vector)
 {
@@ -142,7 +142,7 @@
    APIC_WRITE(APICR_ICRHI, v | (apic_id << 24));
 
    v = APIC_READ(APICR_ICRLO) & ~0xcdfff;
-   v |= (APIC_DEST_DEST << APIC_ICRLO_DEST_OFFSET) 
+   v |= (APIC_DEST_DEST << APIC_ICRLO_DEST_OFFSET)
       | (trigger << APIC_ICRLO_TRIGGER_OFFSET)
       | (level << APIC_ICRLO_LEVEL_OFFSET)
       | (mode << APIC_ICRLO_DELMODE_OFFSET)
@@ -152,7 +152,7 @@
 
 
 // Silly way of busywaiting, but we don't have a timer
-void delay(unsigned us) 
+void delay(unsigned us)
 {
    unsigned freq = 1000; // in MHz, assume 1GHz CPU speed
    uint64_t cycles = us * freq;
@@ -172,7 +172,7 @@
         int   len)
 {
    int i;
-   for (i = 0 ; i < len ; i++ ) { 
+   for (i = 0 ; i < len ; i++ ) {
       *((char *) dst + i) = value;
    }
 }
@@ -245,7 +245,7 @@
       if (send_pending) {
 	 cprint(LINE_STATUS+3, 0, "SMP: STARTUP IPI was never sent");
       }
-      
+
       delay(100000 / DELAY_FACTOR);
 
       err = APIC_READ(APICR_ESR) & 0xef;
@@ -265,7 +265,7 @@
 void boot_ap(unsigned cpu_num)
 {
    unsigned num_sipi, apic_id;
-   extern uint8_t gdt; 
+   extern uint8_t gdt;
    extern uint8_t _ap_trampoline_start;
    extern uint8_t _ap_trampoline_protmode;
    unsigned len = &_ap_trampoline_protmode - &_ap_trampoline_start;
@@ -316,7 +316,7 @@
       if (send_pending) {
 	 cprint(LINE_STATUS+3, 0, "SMP: STARTUP IPI was never sent");
       }
-      
+
       delay(100000 / DELAY_FACTOR);
 
       err = APIC_READ(APICR_ESR) & 0xef;
@@ -359,12 +359,12 @@
 
    tab_entry_ptr = ((uint8_t*)mpc) + sizeof(mp_config_table_header_t);
    mpc_table_end = ((uint8_t*)mpc) + mpc->length;
-      
+
    while (tab_entry_ptr < mpc_table_end) {
       switch (*tab_entry_ptr) {
 	      case MP_PROCESSOR: {
 		 			mp_processor_entry_t *pe = (mp_processor_entry_t*)tab_entry_ptr;
-	
+
 					 if (pe->cpu_flag & CPU_BOOTPROCESSOR) {
 					    // BSP is CPU 0
 					    cpu_num_to_apic_id[0] = pe->apic_id;
@@ -373,12 +373,12 @@
 					    num_cpus++;
 					 }
 					 found_cpus++;
-					    
+
 					 // we cannot handle non-local 82489DX apics
 					 if ((pe->apic_ver & 0xf0) != 0x10) {
 					    return 0;
 					 }
-				
+
 					 tab_entry_ptr += sizeof(mp_processor_entry_t);
 					 break;
 				}
@@ -396,7 +396,7 @@
 	      case MP_LINTSRC:
 					 tab_entry_ptr += sizeof(mp_local_interrupt_entry_t);
 					 break;
-	      default: 
+	      default:
 		 			 return FALSE;
       }
    }
@@ -430,7 +430,7 @@
 
    while ((uintptr_t)addr < end) {
       rp = (rsdp_t*)addr;
-      if (*(unsigned int *)addr == RSDPSignature && 
+      if (*(unsigned int *)addr == RSDPSignature &&
 		checksum((unsigned char*)addr, rp->length) == 0) {
 	   return rp;
       }
@@ -455,13 +455,13 @@
    tab_entry_ptr = ((uint8_t*)mpc) + sizeof(mp_config_table_header_t);
    mpc_table_end = ((uint8_t*)mpc) + mpc->length;
    	while (tab_entry_ptr < mpc_table_end) {
-		
+
 			madt_processor_entry_t *pe = (madt_processor_entry_t*)tab_entry_ptr;
 			if (pe->type == MP_PROCESSOR) {
 				if (pe->enabled) {
 					if (num_cpus < MAX_CPUS) {
 						cpu_num_to_apic_id[num_cpus] = pe->apic_id;
-		
+
 						/* the first CPU is the BSP, don't increment */
 						if (found_cpus) {
 							num_cpus++;
@@ -513,7 +513,7 @@
    memset(&AP, 0, sizeof AP);
 
 	if(v->fail_safe & 8)
-	{		
+	{
 	   // Search for the Floating MP structure pointer
 	   fp = scan_for_floating_ptr_struct(0x0, 0x400);
 	   if (fp == NULL) {
@@ -530,11 +530,11 @@
 	       		fp = scan_for_floating_ptr_struct(address, 0x400);
 	        }
 	   }
-	
+
 	   if (fp != NULL) {
 				// We have a floating MP pointer
 				// Is this a default configuration?
-				
+
 				if (fp->feature[0] > 0 && fp->feature[0] <=7) {
 				    // This is a default config so plug in the numbers
 				    num_cpus = 2;
@@ -543,7 +543,7 @@
 				    cpu_num_to_apic_id[1] = 1;
 				    return;
 				}
-				
+
 				// Do we have a pointer to a MP configuration table?
 				if ( fp->phys_addr != 0) {
 				    if (read_mp_config_table(fp->phys_addr)) {
@@ -569,7 +569,7 @@
        		rp = scan_for_rsdp(address, 0x400);
         }
    }
-    
+
    if (rp == NULL) {
 		/* RSDP not found, give up */
 		return;
@@ -578,18 +578,18 @@
    /* Found the RSDP, now get either the RSDT or XSDT */
    if (rp->revision >= 2) {
 			rt = (rsdt_t *)rp->xrsdt[0];
-			
+
 			if (rt == 0) {
 				return;
 			}
-			// Validate the XSDT 
+			// Validate the XSDT
 			if (*(unsigned int *)rt != XSDTSignature) {
 				return;
 			}
 			if ( checksum((unsigned char*)rt, rt->length) != 0) {
 				return;
 			}
-			
+
     } else {
 			rt = (rsdt_t *)rp->rsdt;
 			if (rt == 0) {
@@ -623,13 +623,13 @@
       tab_ptr += 4;
     }
 }
-	
+
 unsigned my_apic_id()
 {
    return (APIC[APICR_ID][0]) >> 24;
 }
 
-void smp_ap_booted(unsigned cpu_num) 
+void smp_ap_booted(unsigned cpu_num)
 {
    AP[cpu_num].started = TRUE;
 }
diff --git a/smp.h b/smp.h
index 5d07ce7..87a4cc1 100644
--- a/smp.h
+++ b/smp.h
@@ -50,7 +50,7 @@
    uint8_t cpu_flag;
 #define CPU_ENABLED             1       /* Processor is available */
 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
-   uint32_t cpu_signature;           
+   uint32_t cpu_signature;
 #define CPU_STEPPING_MASK 0x0F
 #define CPU_MODEL_MASK  0xF0
 #define CPU_FAMILY_MASK 0xF00
@@ -102,7 +102,7 @@
    uint16_t irqflag;
    uint8_t  srcbusid;
    uint8_t  srcbusirq;
-   uint8_t  destapic;     
+   uint8_t  destapic;
 #define MP_APIC_ALL     0xFF
    uint8_t  destapiclint;
 } mp_local_interrupt_entry_t;
@@ -112,7 +112,7 @@
    char signature[8];   // "RSD "
    uint8_t  checksum;
    char oemid[6];
-   uint8_t revision; 
+   uint8_t revision;
    uint32_t rsdt;
    uint32_t length;
    uint32_t xrsdt[2];
@@ -124,7 +124,7 @@
 typedef struct {
    char signature[4];   // "RSDT"
    uint32_t length;
-   uint8_t revision; 
+   uint8_t revision;
    uint8_t  checksum;
    char oemid[18];
    char cid[4];
@@ -133,7 +133,7 @@
 
 #define MADTSignature ('A' | ('P' << 8) | ('I' << 16) | ('C' << 24))
 typedef struct {
-   uint8_t type; 
+   uint8_t type;
    uint8_t length;
    uint8_t acpi_id;
    uint8_t apic_id;       /* Local APIC number */
diff --git a/spd.c b/spd.c
index fd3db9f..0159149 100644
--- a/spd.c
+++ b/spd.c
@@ -1,546 +1,546 @@
-/*

- * MemTest86+ V5 Specific code (GPL V2.0)

- * By Samuel DEMEULEMEESTER, sdemeule@memtest.org

- * http://www.canardpc.com - http://www.memtest.org

- */

-

- 

-#include "test.h"

-#include "io.h"

-#include "pci.h"

-#include "msr.h"

-#include "spd.h"

-#include "screen_buffer.h"

-#include "jedec_id.h"

-

-#define NULL 0

-

-#define SMBHSTSTS smbusbase

-#define SMBHSTCNT smbusbase + 2

-#define SMBHSTCMD smbusbase + 3

-#define SMBHSTADD smbusbase + 4

-#define SMBHSTDAT smbusbase + 5

-

-extern void wait_keyup();

-

-int smbdev, smbfun;

-unsigned short smbusbase;

-unsigned char spd_raw[256];

-char s[] = {'/', 0, '-', 0, '\\', 0, '|', 0};	

-

-static void ich5_get_smb(void)

-{

-    unsigned long x;

-    int result;

-    result = pci_conf_read(0, smbdev, smbfun, 0x20, 2, &x);

-    if (result == 0) smbusbase = (unsigned short) x & 0xFFFE;

-}

-

-static void piix4_get_smb(void)

-{

-    unsigned long x;

-    int result;

-    

-    result = pci_conf_read(0, smbdev, smbfun, 0x08, 1, &x);

-    

-    if(x < 0x40){   

- 			// SB600/700

- 			result = pci_conf_read(0, smbdev, smbfun, 0x90, 2, &x);

-  		if (result == 0) smbusbase = (unsigned short) x & 0xFFFE;

-  	} else {

-  		// SB800

-			sb800_get_smb();

-  	} 	

-}

-

-void sb800_get_smb(void)

-{

-	  int lbyte, hbyte;

-	

-		__outb(AMD_SMBUS_BASE_REG + 1, AMD_INDEX_IO_PORT);	

-		lbyte = __inb(AMD_DATA_IO_PORT);

-		__outb(AMD_SMBUS_BASE_REG, AMD_INDEX_IO_PORT);	

-		hbyte = __inb(AMD_DATA_IO_PORT);

-		

-		smbusbase = lbyte;

-		smbusbase <<= 8;

-		smbusbase += hbyte;

-		smbusbase &= 0xFFE0;

-		

-		if (smbusbase == 0xFFE0)	{ smbusbase = 0; }	

-}

-

-unsigned char ich5_smb_read_byte(unsigned char adr, unsigned char cmd)

-{

-    int l1, h1, l2, h2;

-    unsigned long long t;

-    __outb(0x1f, SMBHSTSTS);			// reset SMBus Controller

-    __outb(0xff, SMBHSTDAT);

-    while(__inb(SMBHSTSTS) & 0x01);		// wait until ready

-    __outb(cmd, SMBHSTCMD);

-    __outb((adr << 1) | 0x01, SMBHSTADD);

-    __outb(0x48, SMBHSTCNT);

-    rdtsc(l1, h1);

-    //cprint(POP2_Y, POP2_X + 16, s + cmd % 8);	// progress bar

-    while (!(__inb(SMBHSTSTS) & 0x02)) {	// wait til command finished

-			rdtsc(l2, h2);

-			t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;

-			if (t > 10) break;			// break after 10ms

-    }

-    return __inb(SMBHSTDAT);

-}

-

-static int ich5_read_spd(int dimmadr)

-{

-    int x;

-    spd_raw[0] = ich5_smb_read_byte(0x50 + dimmadr, 0);

-    if (spd_raw[0] == 0xff)	return -1;		// no spd here

-    for (x = 1; x < 256; x++) {

-			spd_raw[x] = ich5_smb_read_byte(0x50 + dimmadr, (unsigned char) x);

-    }

-    return 0;

-}

-

-static void us15w_get_smb(void)

-{

-    unsigned long x;

-    int result;

-    result = pci_conf_read(0, 0x1f, 0, 0x40, 2, &x);

-    if (result == 0) smbusbase = (unsigned short) x & 0xFFC0;

-}

-

-unsigned char us15w_smb_read_byte(unsigned char adr, unsigned char cmd)

-{

-    int l1, h1, l2, h2;

-    unsigned long long t;

-    //__outb(0x00, smbusbase + 1);			// reset SMBus Controller

-    //__outb(0x00, smbusbase + 6);

-    //while((__inb(smbusbase + 1) & 0x08) != 0);		// wait until ready

-    __outb(0x02, smbusbase + 0);    // Byte read

-    __outb(cmd, smbusbase + 5);     // Command

-    __outb(0x07, smbusbase + 1);    // Clear status

-    __outb((adr << 1) | 0x01, smbusbase + 4);   // DIMM address

-    __outb(0x12, smbusbase + 0);    // Start

-    //while (((__inb(smbusbase + 1) & 0x08) == 0)) {}	// wait til busy

-    rdtsc(l1, h1);

-    cprint(POP2_Y, POP2_X + 16, s + cmd % 8);	// progress bar

-    while (((__inb(smbusbase + 1) & 0x01) == 0) ||

-		((__inb(smbusbase + 1) & 0x08) != 0)) {	// wait til command finished

-	rdtsc(l2, h2);

-	t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;

-	if (t > 10) break;			// break after 10ms

-    }

-    return __inb(smbusbase + 6);

-}

-

-static int us15w_read_spd(int dimmadr)

-{

-    int x;

-    spd_raw[0] = us15w_smb_read_byte(0x50 + dimmadr, 0);

-    if (spd_raw[0] == 0xff)	return -1;		// no spd here

-    for (x = 1; x < 256; x++) {

-	spd_raw[x] = us15w_smb_read_byte(0x50 + dimmadr, (unsigned char) x);

-    }

-    return 0;

-}

-    

-struct pci_smbus_controller {

-    unsigned vendor;

-    unsigned device;

-    char *name;

-    void (*get_adr)(void);

-    int (*read_spd)(int dimmadr);

-};

-

-static struct pci_smbus_controller smbcontrollers[] = {

-	// Intel SMBUS

-	{0x8086, 0x9C22, "Intel HSW-ULT",	ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x8C22, "Intel HSW", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x1E22, "Intel Z77", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x1C22, "Intel P67", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x3B30, "Intel P55", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x3A60, "Intel ICH10B", 	ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x3A30, "Intel ICH10R", 	ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x2930, "Intel ICH9", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x283E, "Intel ICH8", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x27DA, "Intel ICH7", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x266A, "Intel ICH6", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x24D3, "Intel ICH5", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x24C3, "Intel ICH4", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x25A4, "Intel 6300ESB", ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x269B, "Intel ESB2", 		ich5_get_smb, ich5_read_spd},

-	{0x8086, 0x8119, "Intel US15W", 	us15w_get_smb, us15w_read_spd},

-	{0x8086, 0x5032, "Intel EP80579", ich5_get_smb, ich5_read_spd},

-	

-	// AMD SMBUS

-	{0x1002, 0x4385, "AMD SB600/700",	piix4_get_smb, ich5_read_spd},

-	{0x1022, 0x780B, "AMD SB800/900", sb800_get_smb, ich5_read_spd},

-	{0, 0, "", NULL, NULL}

-};

-

-

-int find_smb_controller(void)

-{

-    int i = 0;

-    unsigned long valuev, valued;

-    

-    for (smbdev = 0; smbdev < 32; smbdev++) {

-			for (smbfun = 0; smbfun < 8; smbfun++) {

-		    pci_conf_read(0, smbdev, smbfun, 0, 2, &valuev);

-		    if (valuev != 0xFFFF) {					// if there is something look what's it..

-					for (i = 0; smbcontrollers[i].vendor > 0; i++) {	// check if this is a known smbus controller

-			    	if (valuev == smbcontrollers[i].vendor) {

-							pci_conf_read(0, smbdev, smbfun, 2, 2, &valued);	// read the device id

-							if (valued == smbcontrollers[i].device) {

-				    		return i;

-							}

-			    	}

-					}

-		    }	

-			}

-    }

-    return -1;

-}

-

-

-

-void get_spd_spec(void)

-{

-	  int index;

-    int h, i, j, z;

-    int k = 0;

-    int module_size;

-    int curcol;

-    int temp_nbd;

-    int tck;

-

-    index = find_smb_controller();

-    

-    if (index == -1) 

-    {

-    	// Unknown SMBUS Controller, exit

-			return;

-    }

-

-    smbcontrollers[index].get_adr();

-		cprint(LINE_SPD-2, 0, "Memory SPD Informations");

-		cprint(LINE_SPD-1, 0, "--------------------------");    

-		

-    for (j = 0; j < 8; j++) {

-			if (smbcontrollers[index].read_spd(j) == 0) {	

-				curcol = 1;

-				if(spd_raw[2] == 0x0b){

-				  // We are here if DDR3 present

-				 

-				  // First print slot#, module capacity

-					cprint(LINE_SPD+k, curcol, " - Slot   :");

-					dprint(LINE_SPD+k, curcol+8, k, 1, 0);

-

-					module_size = get_ddr3_module_size(spd_raw[4] & 0xF, spd_raw[8] & 0x7, spd_raw[7] & 0x7, spd_raw[7] >> 3);

-					temp_nbd = getnum(module_size); curcol += 12;

-					dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;

-					cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;

-					

-					// If XMP is supported, check Tck in XMP reg					

-					if(spd_raw[176] == 0x0C && spd_raw[177] == 0x4A && spd_raw[12])

-						{

-							tck = spd_raw[186];

-						} else {

-							tck = spd_raw[12];

-						}

-					

-					// Then module jedec speed

-					switch(tck)

-					{

-						default:

-							cprint(LINE_SPD+k, curcol, "DDR3-????");

-							break;						

-						case 20:

-							cprint(LINE_SPD+k, curcol, "DDR3-800");

-							curcol--;

-							break;

-						case 15:

-							cprint(LINE_SPD+k, curcol, "DDR3-1066");

-							break;

-						case 12:

-							cprint(LINE_SPD+k, curcol, "DDR3-1333");

-							break;

-						case 10:

-							cprint(LINE_SPD+k, curcol, "DDR3-1600");

-							break;

-						case 9:

-							cprint(LINE_SPD+k, curcol, "DDR3-1866");

-							break;

-						case 8:

-							cprint(LINE_SPD+k, curcol, "DDR3-2133");

-							break;

-						case 7:

-							cprint(LINE_SPD+k, curcol, "DDR3-2400");

-							break;

-						case 6:

-							cprint(LINE_SPD+k, curcol, "DDR3-2533");

-							break;

-						case 5:

-							cprint(LINE_SPD+k, curcol, "DDR3-2666");

-							break;

-						}

-					

-					curcol += 10;

-					

-					if((spd_raw[8] >> 3) == 1) { cprint(LINE_SPD+k, curcol, "ECC"); curcol += 4; }

-					

-					// Then print module infos (manufacturer & part number)	

-					spd_raw[117] &= 0x0F; // Parity odd or even

-					for (i = 0; jep106[i].cont_code < 9; i++) {	

-			    	if (spd_raw[117] == jep106[i].cont_code && spd_raw[118] == jep106[i].hex_byte) {

-			    		// We are here if a Jedec manufacturer is detected

-							cprint(LINE_SPD+k, curcol, "-"); curcol += 2;							

-							cprint(LINE_SPD+k, curcol, jep106[i].name);

-							for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }

-							curcol++;

-							// Display module serial number

-							for (h = 128; h < 146; h++) {	

-								cprint(LINE_SPD+k, curcol, convert_hex_to_char(spd_raw[h]));

-								curcol++;		

-							}			

-

-							// Detect Week and Year of Manufacturing (Think to upgrade after 2015 !!!)

-							if(curcol <= 72 && spd_raw[120] > 3 && spd_raw[120] < 16 && spd_raw[121] < 55)

-							{

-								cprint(LINE_SPD+k, curcol, "(W");	

-								dprint(LINE_SPD+k, curcol+2, spd_raw[121], 2, 0);

-								if(spd_raw[121] < 10) { cprint(LINE_SPD+k, curcol+2, "0"); }

-								cprint(LINE_SPD+k, curcol+4, "'");	

-								dprint(LINE_SPD+k, curcol+5, spd_raw[120], 2, 0);

-								if(spd_raw[120] < 10) { cprint(LINE_SPD+k, curcol+5, "0"); }

-								cprint(LINE_SPD+k, curcol+7, ")");	

-								curcol += 9;

-							}															

-															

-							// Detect XMP Memory

-							if(spd_raw[176] == 0x0C && spd_raw[177] == 0x4A)

-								{

-									cprint(LINE_SPD+k, curcol, "*XMP*");					

-								}

-			    	}

-					}		

-				}

-			// We enter this function if DDR2 is detected

-			if(spd_raw[2] == 0x08){				

-					 // First print slot#, module capacity

-					cprint(LINE_SPD+k, curcol, " - Slot   :");

-					dprint(LINE_SPD+k, curcol+8, k, 1, 0);

-

-					module_size = get_ddr2_module_size(spd_raw[31], spd_raw[5]);

-					temp_nbd = getnum(module_size); curcol += 12;

-					dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;

-					cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;		

-

-					// Then module jedec speed

-					float ddr2_speed, byte1, byte2;

-					

-					byte1 = (spd_raw[9] >> 4) * 10;

-					byte2 = spd_raw[9] & 0xF;

-					

-					ddr2_speed = 1 / (byte1 + byte2) * 10000 * 2;

-

-					temp_nbd = getnum(ddr2_speed);

-					cprint(LINE_SPD+k, curcol, "DDR2-"); curcol += 5;	 

-					dprint(LINE_SPD+k, curcol, ddr2_speed, temp_nbd, 0); curcol += temp_nbd;

-

-					if((spd_raw[11] >> 1) == 1) { cprint(LINE_SPD+k, curcol+1, "ECC"); curcol += 4; }

-			

-					// Then print module infos (manufacturer & part number)	

-					int ccode = 0;

-					

-					for(i = 64; i < 72; i++)

-					{

-						if(spd_raw[i] == 0x7F) { ccode++; }			

-					}

-					

-					curcol++;

-					

-					for (i = 0; jep106[i].cont_code < 9; i++) {	

-			    	if (ccode == jep106[i].cont_code && spd_raw[64+ccode] == jep106[i].hex_byte) {

-			    		// We are here if a Jedec manufacturer is detected

-							cprint(LINE_SPD+k, curcol, "-"); curcol += 2;							

-							cprint(LINE_SPD+k, curcol, jep106[i].name);

-							for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }

-							curcol++;

-							// Display module serial number

-							for (h = 73; h < 91; h++) {	

-								cprint(LINE_SPD+k, curcol, convert_hex_to_char(spd_raw[h]));

-								curcol++;		

-							}			

-															

-			    	}

-					}				

-

-				}	

-			k++;

-			}

-    }

-}

-

-	        

-void show_spd(void)

-{

-    int index;

-    int i, j;

-    int flag = 0;

-    pop2up();

-    wait_keyup();

-    index = find_smb_controller();

-    if (index == -1) {

-	cprint(POP2_Y, POP2_X+1, "SMBus Controller not known");

-	while (!get_key());

-	wait_keyup();

-	pop2down();

-	return;

-    }

-    else cprint(POP2_Y, POP2_X+1, "SPD Data: Slot");    

-    smbcontrollers[index].get_adr();

-    for (j = 0; j < 16; j++) {

-	if (smbcontrollers[index].read_spd(j) == 0) {

-	    dprint(POP2_Y, POP2_X + 15, j, 2, 0);		

-    	    for (i = 0; i < 256; i++) {

-		hprint2(2 + POP2_Y + i / 16, 3 + POP2_X + (i % 16) * 3, spd_raw[i], 2);

-	    }

-	    flag = 0;

-    	    while(!flag) {

-		if (get_key()) flag++;

-	    }

-	    wait_keyup();

-	}

-    }

-    pop2down();

-}

-

-int get_ddr3_module_size(int sdram_capacity, int prim_bus_width, int sdram_width, int ranks)

-{

-	int module_size;

-	

-	switch(sdram_capacity)

-	{

-		case 0:

-			module_size = 256;

-			break;

-		case 1:

-			module_size = 512;

-			break;		

-		default:

-		case 2:

-			module_size = 1024;

-			break;		

-		case 3:

-			module_size = 2048;

-			break;

-		case 4:

-			module_size = 4096;

-			break;		

-		case 5:

-			module_size = 8192;

-			break;	

-		case 6:

-			module_size = 16384;		

-			break;		

-		}

-		

-		module_size /= 8;

-	

-	switch(prim_bus_width)

-	{

-		case 0:

-			module_size *= 8;

-			break;

-		case 1:

-			module_size *= 16;

-			break;		

-		case 2:

-			module_size *= 32;

-			break;		

-		case 3:

-			module_size *= 64;

-			break;		

-		}		

-	

-		switch(sdram_width)

-	{

-		case 0:

-			module_size /= 4;

-			break;

-		case 1:

-			module_size /= 8;

-			break;		

-		case 2:

-			module_size /= 16;

-			break;		

-		case 3:

-			module_size /= 32;

-			break;		

-

-		}	

-	

-	module_size *= (ranks + 1);

-	

-	return module_size;

-}

-

-

-int get_ddr2_module_size(int rank_density_byte, int rank_num_byte)

-{

-	int module_size;

-	

-	switch(rank_density_byte)

-	{

-		case 1:

-			module_size = 1024;

-			break;

-		case 2:

-			module_size = 2048;

-			break;		

-		case 4:

-			module_size = 4096;

-			break;		

-		case 8:

-			module_size = 8192;

-			break;		

-		case 16:

-			module_size = 16384;

-			break;

-		case 32:

-			module_size = 128;

-			break;		

-		case 64:

-			module_size = 256;

-			break;		

-		default:

-		case 128:

-			module_size = 512;

-			break;	

-		}	

-		

-	module_size *= (rank_num_byte & 7) + 1;

-	

-	return module_size;

-		

-}

-

-

-struct ascii_map {

-    unsigned hex_code;

-    char *name;

-};

-

-

-char* convert_hex_to_char(unsigned hex_org) {

-        static char buf[2] = " ";

-        if (hex_org >= 0x20 && hex_org < 0x80) {

-                buf[0] = hex_org;

-        } else {

-                //buf[0] = '\0';

-                buf[0] = ' ';

-        }

-

-        return buf;

+/*
+ * MemTest86+ V5 Specific code (GPL V2.0)
+ * By Samuel DEMEULEMEESTER, sdemeule@memtest.org
+ * http://www.canardpc.com - http://www.memtest.org
+ */
+
+
+#include "test.h"
+#include "io.h"
+#include "pci.h"
+#include "msr.h"
+#include "spd.h"
+#include "screen_buffer.h"
+#include "jedec_id.h"
+
+#define NULL 0
+
+#define SMBHSTSTS smbusbase
+#define SMBHSTCNT smbusbase + 2
+#define SMBHSTCMD smbusbase + 3
+#define SMBHSTADD smbusbase + 4
+#define SMBHSTDAT smbusbase + 5
+
+extern void wait_keyup();
+
+int smbdev, smbfun;
+unsigned short smbusbase;
+unsigned char spd_raw[256];
+char s[] = {'/', 0, '-', 0, '\\', 0, '|', 0};
+
+static void ich5_get_smb(void)
+{
+    unsigned long x;
+    int result;
+    result = pci_conf_read(0, smbdev, smbfun, 0x20, 2, &x);
+    if (result == 0) smbusbase = (unsigned short) x & 0xFFFE;
+}
+
+static void piix4_get_smb(void)
+{
+    unsigned long x;
+    int result;
+
+    result = pci_conf_read(0, smbdev, smbfun, 0x08, 1, &x);
+
+    if(x < 0x40){
+ 			// SB600/700
+ 			result = pci_conf_read(0, smbdev, smbfun, 0x90, 2, &x);
+  		if (result == 0) smbusbase = (unsigned short) x & 0xFFFE;
+  	} else {
+  		// SB800
+			sb800_get_smb();
+  	}
+}
+
+void sb800_get_smb(void)
+{
+	  int lbyte, hbyte;
+
+		__outb(AMD_SMBUS_BASE_REG + 1, AMD_INDEX_IO_PORT);
+		lbyte = __inb(AMD_DATA_IO_PORT);
+		__outb(AMD_SMBUS_BASE_REG, AMD_INDEX_IO_PORT);
+		hbyte = __inb(AMD_DATA_IO_PORT);
+
+		smbusbase = lbyte;
+		smbusbase <<= 8;
+		smbusbase += hbyte;
+		smbusbase &= 0xFFE0;
+
+		if (smbusbase == 0xFFE0)	{ smbusbase = 0; }
+}
+
+unsigned char ich5_smb_read_byte(unsigned char adr, unsigned char cmd)
+{
+    int l1, h1, l2, h2;
+    unsigned long long t;
+    __outb(0x1f, SMBHSTSTS);			// reset SMBus Controller
+    __outb(0xff, SMBHSTDAT);
+    while(__inb(SMBHSTSTS) & 0x01);		// wait until ready
+    __outb(cmd, SMBHSTCMD);
+    __outb((adr << 1) | 0x01, SMBHSTADD);
+    __outb(0x48, SMBHSTCNT);
+    rdtsc(l1, h1);
+    //cprint(POP2_Y, POP2_X + 16, s + cmd % 8);	// progress bar
+    while (!(__inb(SMBHSTSTS) & 0x02)) {	// wait til command finished
+			rdtsc(l2, h2);
+			t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;
+			if (t > 10) break;			// break after 10ms
+    }
+    return __inb(SMBHSTDAT);
+}
+
+static int ich5_read_spd(int dimmadr)
+{
+    int x;
+    spd_raw[0] = ich5_smb_read_byte(0x50 + dimmadr, 0);
+    if (spd_raw[0] == 0xff)	return -1;		// no spd here
+    for (x = 1; x < 256; x++) {
+			spd_raw[x] = ich5_smb_read_byte(0x50 + dimmadr, (unsigned char) x);
+    }
+    return 0;
+}
+
+static void us15w_get_smb(void)
+{
+    unsigned long x;
+    int result;
+    result = pci_conf_read(0, 0x1f, 0, 0x40, 2, &x);
+    if (result == 0) smbusbase = (unsigned short) x & 0xFFC0;
+}
+
+unsigned char us15w_smb_read_byte(unsigned char adr, unsigned char cmd)
+{
+    int l1, h1, l2, h2;
+    unsigned long long t;
+    //__outb(0x00, smbusbase + 1);			// reset SMBus Controller
+    //__outb(0x00, smbusbase + 6);
+    //while((__inb(smbusbase + 1) & 0x08) != 0);		// wait until ready
+    __outb(0x02, smbusbase + 0);    // Byte read
+    __outb(cmd, smbusbase + 5);     // Command
+    __outb(0x07, smbusbase + 1);    // Clear status
+    __outb((adr << 1) | 0x01, smbusbase + 4);   // DIMM address
+    __outb(0x12, smbusbase + 0);    // Start
+    //while (((__inb(smbusbase + 1) & 0x08) == 0)) {}	// wait til busy
+    rdtsc(l1, h1);
+    cprint(POP2_Y, POP2_X + 16, s + cmd % 8);	// progress bar
+    while (((__inb(smbusbase + 1) & 0x01) == 0) ||
+		((__inb(smbusbase + 1) & 0x08) != 0)) {	// wait til command finished
+	rdtsc(l2, h2);
+	t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / v->clks_msec;
+	if (t > 10) break;			// break after 10ms
+    }
+    return __inb(smbusbase + 6);
+}
+
+static int us15w_read_spd(int dimmadr)
+{
+    int x;
+    spd_raw[0] = us15w_smb_read_byte(0x50 + dimmadr, 0);
+    if (spd_raw[0] == 0xff)	return -1;		// no spd here
+    for (x = 1; x < 256; x++) {
+	spd_raw[x] = us15w_smb_read_byte(0x50 + dimmadr, (unsigned char) x);
+    }
+    return 0;
+}
+
+struct pci_smbus_controller {
+    unsigned vendor;
+    unsigned device;
+    char *name;
+    void (*get_adr)(void);
+    int (*read_spd)(int dimmadr);
+};
+
+static struct pci_smbus_controller smbcontrollers[] = {
+	// Intel SMBUS
+	{0x8086, 0x9C22, "Intel HSW-ULT",	ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x8C22, "Intel HSW", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x1E22, "Intel Z77", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x1C22, "Intel P67", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x3B30, "Intel P55", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x3A60, "Intel ICH10B", 	ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x3A30, "Intel ICH10R", 	ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x2930, "Intel ICH9", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x283E, "Intel ICH8", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x27DA, "Intel ICH7", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x266A, "Intel ICH6", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x24D3, "Intel ICH5", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x24C3, "Intel ICH4", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x25A4, "Intel 6300ESB", ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x269B, "Intel ESB2", 		ich5_get_smb, ich5_read_spd},
+	{0x8086, 0x8119, "Intel US15W", 	us15w_get_smb, us15w_read_spd},
+	{0x8086, 0x5032, "Intel EP80579", ich5_get_smb, ich5_read_spd},
+
+	// AMD SMBUS
+	{0x1002, 0x4385, "AMD SB600/700",	piix4_get_smb, ich5_read_spd},
+	{0x1022, 0x780B, "AMD SB800/900", sb800_get_smb, ich5_read_spd},
+	{0, 0, "", NULL, NULL}
+};
+
+
+int find_smb_controller(void)
+{
+    int i = 0;
+    unsigned long valuev, valued;
+
+    for (smbdev = 0; smbdev < 32; smbdev++) {
+			for (smbfun = 0; smbfun < 8; smbfun++) {
+		    pci_conf_read(0, smbdev, smbfun, 0, 2, &valuev);
+		    if (valuev != 0xFFFF) {					// if there is something look what's it..
+					for (i = 0; smbcontrollers[i].vendor > 0; i++) {	// check if this is a known smbus controller
+			    	if (valuev == smbcontrollers[i].vendor) {
+							pci_conf_read(0, smbdev, smbfun, 2, 2, &valued);	// read the device id
+							if (valued == smbcontrollers[i].device) {
+				    		return i;
+							}
+			    	}
+					}
+		    }
+			}
+    }
+    return -1;
+}
+
+
+
+void get_spd_spec(void)
+{
+	  int index;
+    int h, i, j, z;
+    int k = 0;
+    int module_size;
+    int curcol;
+    int temp_nbd;
+    int tck;
+
+    index = find_smb_controller();
+
+    if (index == -1)
+    {
+    	// Unknown SMBUS Controller, exit
+			return;
+    }
+
+    smbcontrollers[index].get_adr();
+		cprint(LINE_SPD-2, 0, "Memory SPD Informations");
+		cprint(LINE_SPD-1, 0, "--------------------------");
+
+    for (j = 0; j < 8; j++) {
+			if (smbcontrollers[index].read_spd(j) == 0) {
+				curcol = 1;
+				if(spd_raw[2] == 0x0b){
+				  // We are here if DDR3 present
+
+				  // First print slot#, module capacity
+					cprint(LINE_SPD+k, curcol, " - Slot   :");
+					dprint(LINE_SPD+k, curcol+8, k, 1, 0);
+
+					module_size = get_ddr3_module_size(spd_raw[4] & 0xF, spd_raw[8] & 0x7, spd_raw[7] & 0x7, spd_raw[7] >> 3);
+					temp_nbd = getnum(module_size); curcol += 12;
+					dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;
+					cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;
+
+					// If XMP is supported, check Tck in XMP reg
+					if(spd_raw[176] == 0x0C && spd_raw[177] == 0x4A && spd_raw[12])
+						{
+							tck = spd_raw[186];
+						} else {
+							tck = spd_raw[12];
+						}
+
+					// Then module jedec speed
+					switch(tck)
+					{
+						default:
+							cprint(LINE_SPD+k, curcol, "DDR3-????");
+							break;
+						case 20:
+							cprint(LINE_SPD+k, curcol, "DDR3-800");
+							curcol--;
+							break;
+						case 15:
+							cprint(LINE_SPD+k, curcol, "DDR3-1066");
+							break;
+						case 12:
+							cprint(LINE_SPD+k, curcol, "DDR3-1333");
+							break;
+						case 10:
+							cprint(LINE_SPD+k, curcol, "DDR3-1600");
+							break;
+						case 9:
+							cprint(LINE_SPD+k, curcol, "DDR3-1866");
+							break;
+						case 8:
+							cprint(LINE_SPD+k, curcol, "DDR3-2133");
+							break;
+						case 7:
+							cprint(LINE_SPD+k, curcol, "DDR3-2400");
+							break;
+						case 6:
+							cprint(LINE_SPD+k, curcol, "DDR3-2533");
+							break;
+						case 5:
+							cprint(LINE_SPD+k, curcol, "DDR3-2666");
+							break;
+						}
+
+					curcol += 10;
+
+					if((spd_raw[8] >> 3) == 1) { cprint(LINE_SPD+k, curcol, "ECC"); curcol += 4; }
+
+					// Then print module infos (manufacturer & part number)
+					spd_raw[117] &= 0x0F; // Parity odd or even
+					for (i = 0; jep106[i].cont_code < 9; i++) {
+			    	if (spd_raw[117] == jep106[i].cont_code && spd_raw[118] == jep106[i].hex_byte) {
+			    		// We are here if a Jedec manufacturer is detected
+							cprint(LINE_SPD+k, curcol, "-"); curcol += 2;
+							cprint(LINE_SPD+k, curcol, jep106[i].name);
+							for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }
+							curcol++;
+							// Display module serial number
+							for (h = 128; h < 146; h++) {
+								cprint(LINE_SPD+k, curcol, convert_hex_to_char(spd_raw[h]));
+								curcol++;
+							}
+
+							// Detect Week and Year of Manufacturing (Think to upgrade after 2015 !!!)
+							if(curcol <= 72 && spd_raw[120] > 3 && spd_raw[120] < 16 && spd_raw[121] < 55)
+							{
+								cprint(LINE_SPD+k, curcol, "(W");
+								dprint(LINE_SPD+k, curcol+2, spd_raw[121], 2, 0);
+								if(spd_raw[121] < 10) { cprint(LINE_SPD+k, curcol+2, "0"); }
+								cprint(LINE_SPD+k, curcol+4, "'");
+								dprint(LINE_SPD+k, curcol+5, spd_raw[120], 2, 0);
+								if(spd_raw[120] < 10) { cprint(LINE_SPD+k, curcol+5, "0"); }
+								cprint(LINE_SPD+k, curcol+7, ")");
+								curcol += 9;
+							}
+
+							// Detect XMP Memory
+							if(spd_raw[176] == 0x0C && spd_raw[177] == 0x4A)
+								{
+									cprint(LINE_SPD+k, curcol, "*XMP*");
+								}
+			    	}
+					}
+				}
+			// We enter this function if DDR2 is detected
+			if(spd_raw[2] == 0x08){
+					 // First print slot#, module capacity
+					cprint(LINE_SPD+k, curcol, " - Slot   :");
+					dprint(LINE_SPD+k, curcol+8, k, 1, 0);
+
+					module_size = get_ddr2_module_size(spd_raw[31], spd_raw[5]);
+					temp_nbd = getnum(module_size); curcol += 12;
+					dprint(LINE_SPD+k, curcol, module_size, temp_nbd, 0); curcol += temp_nbd;
+					cprint(LINE_SPD+k, curcol, " MB"); curcol += 4;
+
+					// Then module jedec speed
+					float ddr2_speed, byte1, byte2;
+
+					byte1 = (spd_raw[9] >> 4) * 10;
+					byte2 = spd_raw[9] & 0xF;
+
+					ddr2_speed = 1 / (byte1 + byte2) * 10000 * 2;
+
+					temp_nbd = getnum(ddr2_speed);
+					cprint(LINE_SPD+k, curcol, "DDR2-"); curcol += 5;
+					dprint(LINE_SPD+k, curcol, ddr2_speed, temp_nbd, 0); curcol += temp_nbd;
+
+					if((spd_raw[11] >> 1) == 1) { cprint(LINE_SPD+k, curcol+1, "ECC"); curcol += 4; }
+
+					// Then print module infos (manufacturer & part number)
+					int ccode = 0;
+
+					for(i = 64; i < 72; i++)
+					{
+						if(spd_raw[i] == 0x7F) { ccode++; }
+					}
+
+					curcol++;
+
+					for (i = 0; jep106[i].cont_code < 9; i++) {
+			    	if (ccode == jep106[i].cont_code && spd_raw[64+ccode] == jep106[i].hex_byte) {
+			    		// We are here if a Jedec manufacturer is detected
+							cprint(LINE_SPD+k, curcol, "-"); curcol += 2;
+							cprint(LINE_SPD+k, curcol, jep106[i].name);
+							for(z = 0; jep106[i].name[z] != '\0'; z++) { curcol++; }
+							curcol++;
+							// Display module serial number
+							for (h = 73; h < 91; h++) {
+								cprint(LINE_SPD+k, curcol, convert_hex_to_char(spd_raw[h]));
+								curcol++;
+							}
+
+			    	}
+					}
+
+				}
+			k++;
+			}
+    }
+}
+
+
+void show_spd(void)
+{
+    int index;
+    int i, j;
+    int flag = 0;
+    pop2up();
+    wait_keyup();
+    index = find_smb_controller();
+    if (index == -1) {
+	cprint(POP2_Y, POP2_X+1, "SMBus Controller not known");
+	while (!get_key());
+	wait_keyup();
+	pop2down();
+	return;
+    }
+    else cprint(POP2_Y, POP2_X+1, "SPD Data: Slot");
+    smbcontrollers[index].get_adr();
+    for (j = 0; j < 16; j++) {
+	if (smbcontrollers[index].read_spd(j) == 0) {
+	    dprint(POP2_Y, POP2_X + 15, j, 2, 0);
+    	    for (i = 0; i < 256; i++) {
+		hprint2(2 + POP2_Y + i / 16, 3 + POP2_X + (i % 16) * 3, spd_raw[i], 2);
+	    }
+	    flag = 0;
+    	    while(!flag) {
+		if (get_key()) flag++;
+	    }
+	    wait_keyup();
+	}
+    }
+    pop2down();
+}
+
+int get_ddr3_module_size(int sdram_capacity, int prim_bus_width, int sdram_width, int ranks)
+{
+	int module_size;
+
+	switch(sdram_capacity)
+	{
+		case 0:
+			module_size = 256;
+			break;
+		case 1:
+			module_size = 512;
+			break;
+		default:
+		case 2:
+			module_size = 1024;
+			break;
+		case 3:
+			module_size = 2048;
+			break;
+		case 4:
+			module_size = 4096;
+			break;
+		case 5:
+			module_size = 8192;
+			break;
+		case 6:
+			module_size = 16384;
+			break;
+		}
+
+		module_size /= 8;
+
+	switch(prim_bus_width)
+	{
+		case 0:
+			module_size *= 8;
+			break;
+		case 1:
+			module_size *= 16;
+			break;
+		case 2:
+			module_size *= 32;
+			break;
+		case 3:
+			module_size *= 64;
+			break;
+		}
+
+		switch(sdram_width)
+	{
+		case 0:
+			module_size /= 4;
+			break;
+		case 1:
+			module_size /= 8;
+			break;
+		case 2:
+			module_size /= 16;
+			break;
+		case 3:
+			module_size /= 32;
+			break;
+
+		}
+
+	module_size *= (ranks + 1);
+
+	return module_size;
+}
+
+
+int get_ddr2_module_size(int rank_density_byte, int rank_num_byte)
+{
+	int module_size;
+
+	switch(rank_density_byte)
+	{
+		case 1:
+			module_size = 1024;
+			break;
+		case 2:
+			module_size = 2048;
+			break;
+		case 4:
+			module_size = 4096;
+			break;
+		case 8:
+			module_size = 8192;
+			break;
+		case 16:
+			module_size = 16384;
+			break;
+		case 32:
+			module_size = 128;
+			break;
+		case 64:
+			module_size = 256;
+			break;
+		default:
+		case 128:
+			module_size = 512;
+			break;
+		}
+
+	module_size *= (rank_num_byte & 7) + 1;
+
+	return module_size;
+
+}
+
+
+struct ascii_map {
+    unsigned hex_code;
+    char *name;
+};
+
+
+char* convert_hex_to_char(unsigned hex_org) {
+        static char buf[2] = " ";
+        if (hex_org >= 0x20 && hex_org < 0x80) {
+                buf[0] = hex_org;
+        } else {
+                //buf[0] = '\0';
+                buf[0] = ' ';
+        }
+
+        return buf;
 }
\ No newline at end of file
diff --git a/spd.h b/spd.h
index 55f164f..f5c80a9 100644
--- a/spd.h
+++ b/spd.h
@@ -7,7 +7,7 @@
 #define AMD_INDEX_IO_PORT	0xCD6
 #define AMD_DATA_IO_PORT	0xCD7
 #define AMD_SMBUS_BASE_REG	0x2C
- 
+
 void get_spd_spec(void);
 int get_ddr2_module_size(int rank_density_byte, int rank_num_byte);
 int get_ddr3_module_size(int sdram_capacity, int prim_bus_width, int sdram_width, int ranks);
diff --git a/stdin.h b/stdin.h
index e3a08e1..6a8020e 100644
--- a/stdin.h
+++ b/stdin.h
@@ -3,7 +3,7 @@
 
 /* Exact integral types */
 typedef unsigned char      uint8_t;
-typedef signed char        int8_t; 
+typedef signed char        int8_t;
 
 typedef unsigned short     uint16_t;
 typedef signed short       int16_t;
@@ -16,7 +16,7 @@
 
 /* Small types */
 typedef unsigned char      uint_least8_t;
-typedef signed char        int_least8_t; 
+typedef signed char        int_least8_t;
 
 typedef unsigned short     uint_least16_t;
 typedef signed short       int_least16_t;
@@ -29,7 +29,7 @@
 
 /* Fast Types */
 typedef unsigned char      uint_fast8_t;
-typedef signed char        int_fast8_t; 
+typedef signed char        int_fast8_t;
 
 typedef unsigned int       uint_fast16_t;
 typedef signed int         int_fast16_t;
diff --git a/stdint.h b/stdint.h
index 1c136e0..1a0733e 100644
--- a/stdint.h
+++ b/stdint.h
@@ -3,7 +3,7 @@
 
 /* Exact integral types */
 typedef unsigned char      uint8_t;
-typedef signed char        int8_t; 
+typedef signed char        int8_t;
 
 typedef unsigned short     uint16_t;
 typedef signed short       int16_t;
@@ -16,7 +16,7 @@
 
 /* Small types */
 typedef unsigned char      uint_least8_t;
-typedef signed char        int_least8_t; 
+typedef signed char        int_least8_t;
 
 typedef unsigned short     uint_least16_t;
 typedef signed short       int_least16_t;
@@ -29,7 +29,7 @@
 
 /* Fast Types */
 typedef unsigned char      uint_fast8_t;
-typedef signed char        int_fast8_t; 
+typedef signed char        int_fast8_t;
 
 typedef unsigned int       uint_fast16_t;
 typedef signed int         int_fast16_t;
diff --git a/test.c b/test.c
index a56d293..d169c36 100644
--- a/test.c
+++ b/test.c
@@ -8,7 +8,7 @@
  * http://www.canardpc.com - http://www.memtest.org
  * Thanks to Passmark for calculate_chunk() and various comments !
  */
- 
+
 #include "test.h"
 #include "config.h"
 #include "stdint.h"
@@ -47,13 +47,13 @@
 	if (run_cpus == 1) {
 		*start = v->map[j].start;
 		*end = v->map[j].end;
-	} 
+	}
 	else{
 
 		// Divide the current segment by the number of CPUs
 		chunk = (ulong)v->map[j].end-(ulong)v->map[j].start;
 		chunk /= run_cpus;
-		
+
 		// Round down to the nearest desired bitlength multiple
 		chunk = (chunk + (makeMultipleOf-1)) &  ~(makeMultipleOf-1);
 
@@ -88,7 +88,7 @@
 		/* Set pattern in our lowest multiple of 0x20000 */
 		p = (ulong *)roundup((ulong)v->map[0].start, 0x1ffff);
 		*p = p1;
-	
+
 		/* Now write pattern compliment */
 		p1 = ~p1;
 		end = v->map[segs-1].end;
@@ -272,7 +272,7 @@
 				"cmpl %%edx,%%edi\n\t"
 				"jb L99\n\t"
 				"jmp L98\n\t"
-			
+
 				"L97:\n\t"
 				"pushl %%edx\n\t"
 				"pushl %%ecx\n\t"
@@ -394,7 +394,7 @@
 					break;
 				}
 /* Original C code replaced with hand tuned assembly code */
-				
+
 				/*for (; p <= pe; p++) {
 					num = rand(me);
 					if (i) {
@@ -412,7 +412,7 @@
 					xorVal = 0;
 				}
 				asm __volatile__ (
-					
+
                     "pushl %%ebp\n\t"
 
 					// Skip first increment
@@ -474,7 +474,7 @@
 					"popl %%eax\n\t"
 					"popl %%ecx\n\t"
 					"popl %%edx\n\t"
-					"jmp L25\n" 
+					"jmp L25\n"
 
 					"L24:\n\t"
                                         "popl %%ebp\n\t"
@@ -570,7 +570,7 @@
 					break;
 				}
 
-				// Original C code replaced with hand tuned assembly code 
+				// Original C code replaced with hand tuned assembly code
 				// seems broken
  				/*for (; p <= pe; p++) {
 					if ((bad=*p) != p1) {
@@ -632,7 +632,7 @@
 					done++;
 				}
 
-				/* Since we are using unsigned addresses a 
+				/* Since we are using unsigned addresses a
 				 * redundent check is required */
 				if (pe < start || pe > end) {
 					pe = start;
@@ -1169,7 +1169,7 @@
 }
 
 /*
- * Test memory using block moves 
+ * Test memory using block moves
  * Adapted from Robert Redelmeier's burnBX test
  */
 void block_move(int iter, int me)
@@ -1221,7 +1221,7 @@
 				"movl %%eax, %%edx\n\t"
 				"notl %%edx\n\t"
 
-				// Set a block of 64-bytes	// First loop DWORDS are 
+				// Set a block of 64-bytes	// First loop DWORDS are
 				"movl %%eax,0(%%edi)\n\t"	// 0x00000001
 				"movl %%eax,4(%%edi)\n\t"	// 0x00000001
 				"movl %%eax,8(%%edi)\n\t"	// 0x00000001
@@ -1239,11 +1239,11 @@
 				"movl %%edx,56(%%edi)\n\t"	// 0xfffffffe
 				"movl %%edx,60(%%edi)\n\t"	// 0xfffffffe
 
-				// rotate left with carry, 
+				// rotate left with carry,
 				// second loop eax is		 0x00000002
 				// second loop edx is (~eax) 0xfffffffd
-				"rcll $1, %%eax\n\t"		
-				
+				"rcll $1, %%eax\n\t"
+
 				// Move current position forward 64-bytes (to start of next block)
 				"leal 64(%%edi), %%edi\n\t"
 
@@ -1259,7 +1259,7 @@
 	}
 	s_barrier();
 
-	/* Now move the data around 
+	/* Now move the data around
 	 * First move the data up half of the segment size we are testing
 	 * Then move the data to the original location + 32 bytes
 	 */
@@ -1300,7 +1300,7 @@
 					"L110:\n\t"
 
 					//
-					// At the end of all this 
+					// At the end of all this
 					// - the second half equals the inital value of the first half
 					// - the first half is right shifted 32-bytes (with wrapping)
 					//
@@ -1337,7 +1337,7 @@
 	}
 	s_barrier();
 
-	/* Now check the data 
+	/* Now check the data
 	 * The error checking is rather crude.  We just check that the
 	 * adjacent words are the same.
 	 */
@@ -1524,7 +1524,7 @@
 			t = h * ((unsigned)0xffffffff / v->clks_msec) / 1000;
 			t += (l / v->clks_msec) / 1000;
 		}
-		
+
 		/* Is the time up? */
 		if (t >= n) {
 			break;
@@ -1547,7 +1547,7 @@
 
 void beep(unsigned int frequency)
 {
-	
+
 	unsigned int count = 1193180 / frequency;
 
 	// Switch on the speaker
diff --git a/test.h b/test.h
index a0275e5..ed35867 100644
--- a/test.h
+++ b/test.h
@@ -117,7 +117,7 @@
 int insertaddress(ulong);
 void printpatn(void);
 void printpatn(void);
-void itoa(char s[], int n); 
+void itoa(char s[], int n);
 void reverse(char *p);
 void serial_console_setup(char *param);
 void serial_echo_init(void);
@@ -165,7 +165,7 @@
 void block_move(int iter, int cpu);
 void find_ticks(void);
 void print_err(ulong *adr, ulong good, ulong bad, ulong xor);
-void print_ecc_err(ulong page, ulong offset, int corrected, 
+void print_ecc_err(ulong page, ulong offset, int corrected,
 	unsigned short syndrome, int channel);
 void mem_size(void);
 void adj_mem(void);
@@ -220,7 +220,7 @@
         asm(
 		"push %eax\n\t"
 		"movl %cr0,%eax\n\t"
-    "andl $0x9fffffff,%eax\n\t" /* Clear CD and NW */ 
+    "andl $0x9fffffff,%eax\n\t" /* Clear CD and NW */
     "movl %eax,%cr0\n\t"
 		"pop  %eax\n\t");
 }
diff --git a/vmem.c b/vmem.c
index 413d737..5adbe14 100644
--- a/vmem.c
+++ b/vmem.c
@@ -1,4 +1,4 @@
-/* vmem.c - MemTest-86 
+/* vmem.c - MemTest-86
  *
  * Virtual memory handling (PAE)
  *
@@ -149,6 +149,6 @@
 	cprint(LINE_SCROLL -2, 0, "page_of(        )->            ");
 	hprint(LINE_SCROLL -2, 8, ((unsigned long)addr));
 	hprint(LINE_SCROLL -2, 20, page);
-#endif	
+#endif
 	return page;
 }