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Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S
5 * Copyright (C) 2011, 2014 Stefan Tauner
6 *
7 * Based on nicinctel_spi.c and ichspi.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see http://www.gnu.org/licenses/.
20 */
21
22/*
23 * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet
24 * 3.3.1.4: General EEPROM Software Access
25 * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface)
26 * 7.4: Register Descriptions
27 */
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010028/*
29 * Datasheet: Intel Ethernet Controller I210: Datasheet
30 * 8.4.3: EEPROM-Mode Read Register
31 * 8.4.6: EEPROM-Mode Write Register
32 * Write process inspired on kernel e1000_i210.c
33 */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000034
35#include <stdlib.h>
36#include <unistd.h>
37#include "flash.h"
38#include "spi.h"
39#include "programmer.h"
40#include "hwaccess.h"
41
42#define PCI_VENDOR_ID_INTEL 0x8086
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010043#define MEMMAP_SIZE 0x1c /* Only EEC, EERD and EEWR are needed. */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000044
45#define EEC 0x10 /* EEPROM/Flash Control Register */
46#define EERD 0x14 /* EEPROM Read Register */
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010047#define EEWR 0x18 /* EEPROM Write Register */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000048
49/* EPROM/Flash Control Register bits */
50#define EE_SCK 0
51#define EE_CS 1
52#define EE_SI 2
53#define EE_SO 3
54#define EE_REQ 6
55#define EE_GNT 7
56#define EE_PRES 8
57#define EE_SIZE 11
58#define EE_SIZE_MASK 0xf
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010059#define EE_FLUPD 23
60#define EE_FLUDONE 26
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000061
62/* EEPROM Read Register bits */
63#define EERD_START 0
64#define EERD_DONE 1
65#define EERD_ADDR 2
66#define EERD_DATA 16
67
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010068/* EEPROM Write Register bits */
69#define EEWR_CMDV 0
70#define EEWR_DONE 1
71#define EEWR_ADDR 2
72#define EEWR_DATA 16
73
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000074#define BIT(x) (1<<x)
Stefan Tauner8d21ff12015-01-10 09:33:06 +000075#define EE_PAGE_MASK 0x3f
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000076
77static uint8_t *nicintel_eebar;
78static struct pci_dev *nicintel_pci;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010079static bool done_i20_write = false;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000080
81#define UNPROG_DEVICE 0x1509
82
Nico Hubera4b1d5b2017-10-10 17:38:07 +020083/*
84 * Warning: is_i210() below makes assumptions on these PCI ids.
85 * It may have to be updated when this list is extended.
86 */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000087const struct dev_entry nics_intel_ee[] = {
88 {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"},
89 {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"},
90 {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"},
91 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"},
92 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"},
93 {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"},
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010094 {PCI_VENDOR_ID_INTEL, 0x1531, NT, "Intel", "I210 Gigabit Network Connection Unprogrammed"},
95 {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"},
96 {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"},
97 {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"},
98 {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"},
99 {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"},
100 {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"},
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000101 {0},
102};
103
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100104static inline bool is_i210(uint16_t device_id)
105{
Nico Hubera4b1d5b2017-10-10 17:38:07 +0200106 return (device_id & 0xfff0) == 0x1530;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100107}
108
109static int nicintel_ee_probe_i210(struct flashctx *flash)
110{
111 /* Emulated eeprom has a fixed size of 4 KB */
112 flash->chip->total_size = 4;
113 flash->chip->page_size = flash->chip->total_size * 1024;
114 flash->chip->tested = TEST_OK_PREW;
115 flash->chip->gran = write_gran_1byte_implicit_erase;
116 flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size;
117 flash->chip->block_erasers->eraseblocks[0].count = 1;
118
119 return 1;
120}
121
122static int nicintel_ee_probe_82580(struct flashctx *flash)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000123{
124 if (nicintel_pci->device_id == UNPROG_DEVICE)
125 flash->chip->total_size = 16; /* Fall back to minimum supported size. */
126 else {
127 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
128 tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK);
129 switch (tmp) {
130 case 7:
131 flash->chip->total_size = 16;
132 break;
133 case 8:
134 flash->chip->total_size = 32;
135 break;
136 default:
137 msg_cerr("Unsupported chip size 0x%x\n", tmp);
138 return 0;
139 }
140 }
141
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000142 flash->chip->page_size = EE_PAGE_MASK + 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000143 flash->chip->tested = TEST_OK_PREW;
144 flash->chip->gran = write_gran_1byte_implicit_erase;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000145 flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1);
146 flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1);
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000147
148 return 1;
149}
150
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100151static int nicintel_ee_probe(struct flashctx *flash)
152{
153 if (is_i210(nicintel_pci->device_id))
154 return nicintel_ee_probe_i210(flash);
155
156 return nicintel_ee_probe_82580(flash);
157}
158
159#define MAX_ATTEMPTS 10000000
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000160static int nicintel_ee_read_word(unsigned int addr, uint16_t *data)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000161{
162 uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR);
163 pci_mmio_writel(tmp, nicintel_eebar + EERD);
164
165 /* Poll done flag. 10.000.000 cycles seem to be enough. */
166 uint32_t i;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100167 for (i = 0; i < MAX_ATTEMPTS; i++) {
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000168 tmp = pci_mmio_readl(nicintel_eebar + EERD);
169 if (tmp & BIT(EERD_DONE)) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000170 *data = (tmp >> EERD_DATA) & 0xffff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000171 return 0;
172 }
173 }
174
175 return -1;
176}
177
178static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len)
179{
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000180 uint16_t data;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000181
182 /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address
183 * explicitly at the start (and also at the end in the loop below). */
184 if (addr & 1) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000185 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000186 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000187 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000188 addr++;
189 len--;
190 }
191
192 while (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000193 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000194 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000195 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000196 addr++;
197 len--;
198 if (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000199 *buf++ = (data >> 8) & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000200 addr++;
201 len--;
202 }
203 }
204
205 return 0;
206}
207
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100208static int nicintel_ee_write_word_i210(unsigned int addr, uint16_t data)
209{
210 uint32_t eewr;
211
212 eewr = addr << EEWR_ADDR;
213 eewr |= data << EEWR_DATA;
214 eewr |= BIT(EEWR_CMDV);
215 pci_mmio_writel(eewr, nicintel_eebar + EEWR);
216
217 programmer_delay(5);
David Hendricks79d838d2017-09-27 09:25:34 -0700218 int i;
219 for (i = 0; i < MAX_ATTEMPTS; i++)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100220 if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE))
221 return 0;
222 return -1;
223}
224
Nico Hubera4b1d5b2017-10-10 17:38:07 +0200225static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf,
226 unsigned int addr, unsigned int len)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100227{
228 done_i20_write = true;
229
230 if (addr & 1) {
231 uint16_t data;
232
233 if (nicintel_ee_read_word(addr / 2, &data)) {
234 msg_perr("Timeout reading heading byte\n");
235 return -1;
236 }
237
238 data &= 0xff;
239 data |= (buf ? (buf[0]) : 0xff) << 8;
240
241 if (nicintel_ee_write_word_i210(addr / 2, data)) {
242 msg_perr("Timeout writing heading word\n");
243 return -1;
244 }
245
246 if (buf)
247 buf ++;
248 addr ++;
249 len --;
250 }
251
252 while (len > 0) {
253 uint16_t data;
254
255 if (len == 1) {
256 if (nicintel_ee_read_word(addr / 2, &data)) {
257 msg_perr("Timeout reading tail byte\n");
258 return -1;
259 }
260
261 data &= 0xff00;
262 data |= buf ? (buf[0]) : 0xff;
263 } else {
264 if (buf)
265 data = buf[0] | (buf[1] << 8);
266 else
267 data = 0xffff;
268 }
269
270 if (nicintel_ee_write_word_i210(addr / 2, data)) {
271 msg_perr("Timeout writing Shadow RAM\n");
272 return -1;
273 }
274
275 if (buf)
276 buf += 2;
277 if (len > 2)
278 len -= 2;
279 else
280 len = 0;
281 addr += 2;
282 }
283
284 return 0;
285}
286
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000287static int nicintel_ee_bitset(int reg, int bit, bool val)
288{
289 uint32_t tmp;
290
291 tmp = pci_mmio_readl(nicintel_eebar + reg);
292 if (val)
293 tmp |= BIT(bit);
294 else
295 tmp &= ~BIT(bit);
296 pci_mmio_writel(tmp, nicintel_eebar + reg);
297
298 return -1;
299}
300
301/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */
302static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso)
303{
304 uint8_t out = 0x0;
305
306 int i;
307 for (i = 7; i >= 0; i--) {
308 nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i));
309 nicintel_ee_bitset(EEC, EE_SCK, 1);
310 if (miso != NULL) {
311 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
312 if (tmp & BIT(EE_SO))
313 out |= BIT(i);
314 }
315 nicintel_ee_bitset(EEC, EE_SCK, 0);
316 }
317
318 if (miso != NULL)
319 *miso = out;
320
321 return 0;
322}
323
324/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */
325static int nicintel_ee_ready(void)
326{
327 unsigned int i;
328 for (i = 0; i < 1000; i++) {
329 nicintel_ee_bitset(EEC, EE_CS, 0);
330
331 nicintel_ee_bitbang(JEDEC_RDSR, NULL);
332 uint8_t rdsr;
333 nicintel_ee_bitbang(0x00, &rdsr);
334
335 nicintel_ee_bitset(EEC, EE_CS, 1);
336 programmer_delay(1);
337 if (!(rdsr & SPI_SR_WIP)) {
338 return 0;
339 }
340 }
341 return -1;
342}
343
344/* Requests direct access to the SPI pins. */
345static int nicintel_ee_req(void)
346{
347 uint32_t tmp;
348 nicintel_ee_bitset(EEC, EE_REQ, 1);
349
350 tmp = pci_mmio_readl(nicintel_eebar + EEC);
351 if (!(tmp & BIT(EE_GNT))) {
352 msg_perr("Enabling eeprom access failed.\n");
353 return 1;
354 }
355
356 nicintel_ee_bitset(EEC, EE_SCK, 0);
357 return 0;
358}
359
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100360static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000361{
362 if (nicintel_ee_req())
363 return -1;
364
365 int ret = -1;
366 if (nicintel_ee_ready())
367 goto out;
368
369 while (len > 0) {
370 /* WREN */
371 nicintel_ee_bitset(EEC, EE_CS, 0);
372 nicintel_ee_bitbang(JEDEC_WREN, NULL);
373 nicintel_ee_bitset(EEC, EE_CS, 1);
374 programmer_delay(1);
375
376 /* data */
377 nicintel_ee_bitset(EEC, EE_CS, 0);
378 nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL);
379 nicintel_ee_bitbang((addr >> 8) & 0xff, NULL);
380 nicintel_ee_bitbang(addr & 0xff, NULL);
381 while (len > 0) {
382 nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL);
383 len--;
384 addr++;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000385 if (!(addr & EE_PAGE_MASK))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000386 break;
387 }
388 nicintel_ee_bitset(EEC, EE_CS, 1);
389 programmer_delay(1);
390 if (nicintel_ee_ready())
391 goto out;
392 }
393 ret = 0;
394out:
395 nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */
396 return ret;
397}
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100398static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
399{
400 if (is_i210(nicintel_pci->device_id))
401 return nicintel_ee_write_i210(flash, buf, addr, len);
402
403 return nicintel_ee_write_82580(flash, buf, addr, len);
404}
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000405
406static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len)
407{
408 return nicintel_ee_write(flash, NULL, addr, len);
409}
410
411static const struct opaque_master opaque_master_nicintel_ee = {
412 .probe = nicintel_ee_probe,
413 .read = nicintel_ee_read,
414 .write = nicintel_ee_write,
415 .erase = nicintel_ee_erase,
416};
417
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100418static int nicintel_ee_shutdown_i210(void *arg)
419{
420 if (!done_i20_write)
421 return 0;
422
423 uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC);
424
425 flup |= BIT(EE_FLUPD);
426 pci_mmio_writel(flup, nicintel_eebar + EEC);
427
David Hendricks79d838d2017-09-27 09:25:34 -0700428 int i;
429 for (i = 0; i < MAX_ATTEMPTS; i++)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100430 if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE))
431 return 0;
432
433 msg_perr("Flash update failed\n");
434
435 return -1;
436}
437
Stefan Tauner5c316f92015-02-08 21:57:52 +0000438static int nicintel_ee_shutdown(void *eecp)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000439{
440 uint32_t old_eec = *(uint32_t *)eecp;
441 /* Request bitbanging and unselect the chip first to be safe. */
442 if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1))
443 return -1;
444
445 /* Try to restore individual bits we care about. */
446 int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK));
447 ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI));
448 ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS));
449 /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */
450 ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ));
451
452 free(eecp);
453 return ret;
454}
455
456int nicintel_ee_init(void)
457{
458 if (rget_io_perms())
459 return 1;
460
461 struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0);
462 if (!dev)
463 return 1;
464
465 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
466 if (!io_base_addr)
467 return 1;
468
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100469 nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM",
470 io_base_addr + (is_i210(dev->device_id) ? 0x12000 : 0), MEMMAP_SIZE);
471 if (!nicintel_eebar)
472 return 1;
473
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000474 nicintel_pci = dev;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100475 if ((dev->device_id != UNPROG_DEVICE) && ! is_i210(dev->device_id))
476 {
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000477 uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC);
478
479 /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition),
480 * and 3.3.1.7 for possible recovery. */
481 if (!(eec & BIT(EE_PRES))) {
482 msg_perr("Controller reports no EEPROM is present.\n");
483 return 1;
484 }
485
486 uint32_t *eecp = malloc(sizeof(uint32_t));
487 if (eecp == NULL)
488 return 1;
489 *eecp = eec;
490
Stefan Tauner5c316f92015-02-08 21:57:52 +0000491 if (register_shutdown(nicintel_ee_shutdown, eecp))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000492 return 1;
493 }
494
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100495 if (is_i210(dev->device_id))
496 if (register_shutdown(nicintel_ee_shutdown_i210, NULL))
497 return 1;
498
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000499 return register_opaque_master(&opaque_master_nicintel_ee);
500}