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Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00004 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Carl-Daniel Hailfinger
Stefan Reinauera9424d52008-06-27 16:28:34 +00005 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21/*
22 * Contains the generic SPI framework
23 */
24
Nico Huber1ca6bef2017-12-20 00:42:16 +010025#define _XOPEN_SOURCE 700 /* for ffs() */
26
Patrick Georgi97bc95c2011-03-08 07:17:44 +000027#include <strings.h>
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +000028#include <string.h>
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000029#include "flash.h"
Carl-Daniel Hailfinger08454642009-06-15 14:14:48 +000030#include "flashchips.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000031#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000032#include "programmer.h"
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000033#include "spi.h"
Carl-Daniel Hailfinger70539262007-10-15 21:45:29 +000034
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000035int spi_send_command(struct flashctx *flash, unsigned int writecnt,
36 unsigned int readcnt, const unsigned char *writearr,
37 unsigned char *readarr)
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000038{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000039 return flash->mst->spi.command(flash, writecnt, readcnt, writearr,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000040 readarr);
Carl-Daniel Hailfinger3d94a0e2007-10-16 21:09:06 +000041}
42
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000043int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds)
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +000044{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000045 return flash->mst->spi.multicommand(flash, cmds);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000046}
47
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000048int default_spi_send_command(struct flashctx *flash, unsigned int writecnt,
49 unsigned int readcnt,
50 const unsigned char *writearr,
51 unsigned char *readarr)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000052{
53 struct spi_command cmd[] = {
54 {
55 .writecnt = writecnt,
56 .readcnt = readcnt,
57 .writearr = writearr,
58 .readarr = readarr,
59 }, {
60 .writecnt = 0,
61 .writearr = NULL,
62 .readcnt = 0,
63 .readarr = NULL,
64 }};
65
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000066 return spi_send_multicommand(flash, cmd);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000067}
68
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000069int default_spi_send_multicommand(struct flashctx *flash,
70 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000071{
72 int result = 0;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +000073 for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000074 result = spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +000075 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +000076 }
77 return result;
Carl-Daniel Hailfingerd0478292009-07-10 21:08:55 +000078}
79
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000080int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
81 unsigned int len)
Michael Karcher62797512011-05-11 17:07:02 +000082{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000083 unsigned int max_data = flash->mst->spi.max_data_read;
Michael Karcher62797512011-05-11 17:07:02 +000084 if (max_data == MAX_DATA_UNSPECIFIED) {
85 msg_perr("%s called, but SPI read chunk size not defined "
86 "on this hardware. Please report a bug at "
87 "flashrom@flashrom.org\n", __func__);
88 return 1;
89 }
90 return spi_read_chunked(flash, buf, start, len, max_data);
91}
92
Mark Marshallf20b7be2014-05-09 21:16:21 +000093int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Michael Karcher62797512011-05-11 17:07:02 +000094{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000095 unsigned int max_data = flash->mst->spi.max_data_write;
Michael Karcher62797512011-05-11 17:07:02 +000096 if (max_data == MAX_DATA_UNSPECIFIED) {
97 msg_perr("%s called, but SPI write chunk size not defined "
98 "on this hardware. Please report a bug at "
99 "flashrom@flashrom.org\n", __func__);
100 return 1;
101 }
102 return spi_write_chunked(flash, buf, start, len, max_data);
103}
104
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000105int spi_chip_read(struct flashctx *flash, uint8_t *buf, unsigned int start,
106 unsigned int len)
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000107{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000108 unsigned int addrbase = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000109
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000110 /* Check if the chip fits between lowest valid and highest possible
111 * address. Highest possible address with the current SPI implementation
112 * means 0xffffff, the highest unsigned 24bit number.
113 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000114 addrbase = spi_get_valid_read_addr(flash);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000115 if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) {
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000116 msg_perr("Flash chip size exceeds the allowed access window. ");
117 msg_perr("Read will probably fail.\n");
118 /* Try to get the best alignment subject to constraints. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000119 addrbase = (1 << 24) - flash->chip->total_size * 1024;
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000120 }
121 /* Check if alignment is native (at least the largest power of two which
122 * is a factor of the mapped size of the chip).
123 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000124 if (ffs(flash->chip->total_size * 1024) > (ffs(addrbase) ? : 33)) {
Carl-Daniel Hailfingerec489e42010-09-15 00:13:02 +0000125 msg_perr("Flash chip is not aligned natively in the allowed "
126 "access window.\n");
127 msg_perr("Read will probably return garbage.\n");
128 }
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000129 return flash->mst->spi.read(flash, buf, addrbase + start, len);
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000130}
131
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000132/*
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000133 * Program chip using page (256 bytes) programming.
134 * Some SPI masters can't do this, they use single byte programming instead.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000135 * The redirect to single byte programming is achieved by setting
136 * .write_256 = spi_chip_write_1
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000137 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000138/* real chunksize is up to 256, logical chunksize is 256 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000139int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000140{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000141 return flash->mst->spi.write_256(flash, buf, start, len);
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000142}
143
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000144/*
145 * Get the lowest allowed address for read accesses. This often happens to
146 * be the lowest allowed address for all commands which take an address.
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000147 * This is a master limitation.
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000148 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000149uint32_t spi_get_valid_read_addr(struct flashctx *flash)
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000150{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000151 switch (flash->mst->spi.type) {
Carl-Daniel Hailfinger71127722010-05-31 15:27:27 +0000152#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000153#if defined(__i386__) || defined(__x86_64__)
154 case SPI_CONTROLLER_ICH7:
Stefan Taunereb582572012-09-21 12:52:50 +0000155 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000156 /* Return BBAR for ICH chipsets. */
157 return ichspi_bbar;
158#endif
159#endif
160 default:
161 return 0;
162 }
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000163}
Michael Karcherb9dbe482011-05-11 17:07:07 +0000164
Mark Marshallf20b7be2014-05-09 21:16:21 +0000165int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Nico Huber7bca1262012-06-15 22:28:12 +0000166{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000167 return flash->mst->spi.write_aai(flash, buf, start, len);
Nico Huber7bca1262012-06-15 22:28:12 +0000168}
169
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000170int register_spi_master(const struct spi_master *mst)
Michael Karcherb9dbe482011-05-11 17:07:07 +0000171{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000172 struct registered_master rmst;
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000173
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000174 if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command ||
175 !mst->multicommand ||
176 ((mst->command == default_spi_send_command) &&
177 (mst->multicommand == default_spi_send_multicommand))) {
178 msg_perr("%s called with incomplete master definition. "
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000179 "Please report a bug at flashrom@flashrom.org\n",
180 __func__);
181 return ERROR_FLASHROM_BUG;
182 }
183
184
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000185 rmst.buses_supported = BUS_SPI;
186 rmst.spi = *mst;
187 return register_master(&rmst);
Stefan Tauner93f70232011-07-26 14:33:46 +0000188}