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Andrew Morganc29c2e72010-06-07 22:37:54 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Andrew Morgan <ziltro@ziltro.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Andrew Morganc29c2e72010-06-07 22:37:54 +000015 */
16
17#if defined(__i386__) || defined(__x86_64__)
18
19#include <stdlib.h>
20#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000021#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000022#include "hwaccess.h"
Andrew Morganc29c2e72010-06-07 22:37:54 +000023
24#define PCI_VENDOR_ID_NATSEMI 0x100b
25
26#define BOOT_ROM_ADDR 0x50
27#define BOOT_ROM_DATA 0x54
28
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000029static uint32_t io_base_addr = 0;
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000030const struct dev_entry nics_natsemi[] = {
Andrew Morganc29c2e72010-06-07 22:37:54 +000031 {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
32 {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000033
34 {0},
Andrew Morganc29c2e72010-06-07 22:37:54 +000035};
36
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000037static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
38 chipaddr addr);
39static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
40 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000041static const struct par_master par_master_nicnatsemi = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000042 .chip_readb = nicnatsemi_chip_readb,
43 .chip_readw = fallback_chip_readw,
44 .chip_readl = fallback_chip_readl,
45 .chip_readn = fallback_chip_readn,
46 .chip_writeb = nicnatsemi_chip_writeb,
47 .chip_writew = fallback_chip_writew,
48 .chip_writel = fallback_chip_writel,
49 .chip_writen = fallback_chip_writen,
50};
51
Andrew Morganc29c2e72010-06-07 22:37:54 +000052int nicnatsemi_init(void)
53{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000054 struct pci_dev *dev = NULL;
55
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000056 if (rget_io_perms())
57 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000058
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000059 dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0);
60 if (!dev)
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000061 return 1;
Andrew Morganc29c2e72010-06-07 22:37:54 +000062
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000063 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000064 if (!io_base_addr)
65 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000066
Andrew Morgan74a828a2010-07-21 15:12:07 +000067 /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
68 * in another. My NIC has MA16 connected to A16 on the boot ROM socket
69 * so I'm assuming it is accessible. If not then next line wants to be
70 * max_rom_decode.parallel = 65536; and the mask in the read/write
71 * functions below wants to be 0x0000FFFF.
72 */
73 max_rom_decode.parallel = 131072;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +100074 register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, NULL);
Andrew Morgan74a828a2010-07-21 15:12:07 +000075
Andrew Morganc29c2e72010-06-07 22:37:54 +000076 return 0;
77}
78
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000079static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
80 chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +000081{
Andrew Morgan74a828a2010-07-21 15:12:07 +000082 OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +000083 /*
84 * The datasheet requires 32 bit accesses to this register, but it seems
85 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +000086 * Bits 8-31 of this register are apparently don't care, and if this
87 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +000088 * register seem to work fine. Due to that, we ignore the advice in the
89 * data sheet.
90 */
91 OUTB(val, io_base_addr + BOOT_ROM_DATA);
92}
93
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000094static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
95 const chipaddr addr)
Andrew Morganc29c2e72010-06-07 22:37:54 +000096{
Andrew Morgan74a828a2010-07-21 15:12:07 +000097 OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
Andrew Morganc29c2e72010-06-07 22:37:54 +000098 /*
99 * The datasheet requires 32 bit accesses to this register, but it seems
100 * that requirement might only apply if the register is memory mapped.
David Borg243ec632010-08-08 17:04:21 +0000101 * Bits 8-31 of this register are apparently don't care, and if this
102 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
Andrew Morganc29c2e72010-06-07 22:37:54 +0000103 * register seem to work fine. Due to that, we ignore the advice in the
104 * data sheet.
105 */
106 return INB(io_base_addr + BOOT_ROM_DATA);
107}
108
109#else
110#error PCI port I/O access is not supported on this architecture yet.
111#endif