blob: ef9da4b1ac07ff79a49dc94dc7bd0bc62af36947 [file] [log] [blame]
Jason Wanga3f04be2008-11-28 21:36:51 +00001/*
2 * This file is part of the flashrom project.
3 *
Jason Wang13f98ce2008-11-29 15:07:15 +00004 * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang@amd.com>
5 * Copyright (C) 2008 Joe Bao <Zheng.Bao@amd.com>
Uwe Hermann97e8f222009-04-13 21:35:49 +00006 * Copyright (C) 2008 Advanced Micro Devices, Inc.
Wei Hu31402ee2014-05-16 21:39:33 +00007 * Copyright (C) 2009, 2010, 2013 Carl-Daniel Hailfinger
8 * Copyright (C) 2013 Stefan Tauner
Jason Wanga3f04be2008-11-28 21:36:51 +00009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Jason Wanga3f04be2008-11-28 21:36:51 +000019 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Rudolf Marek70e14592013-07-25 22:58:56 +000023#include <string.h>
24#include <stdlib.h>
Jason Wanga3f04be2008-11-28 21:36:51 +000025#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000026#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000027#include "hwaccess.h"
Jason Wanga3f04be2008-11-28 21:36:51 +000028#include "spi.h"
29
Carl-Daniel Hailfinger2c7ba8c2009-06-23 00:47:26 +000030/* This struct is unused, but helps visualize the SB600 SPI BAR layout.
31 *struct sb600_spi_controller {
32 * unsigned int spi_cntrl0; / * 00h * /
33 * unsigned int restrictedcmd1; / * 04h * /
34 * unsigned int restrictedcmd2; / * 08h * /
35 * unsigned int spi_cntrl1; / * 0ch * /
36 * unsigned int spi_cmdvalue0; / * 10h * /
37 * unsigned int spi_cmdvalue1; / * 14h * /
38 * unsigned int spi_cmdvalue2; / * 18h * /
39 * unsigned int spi_fakeid; / * 1Ch * /
40 *};
41 */
Jason Wanga3f04be2008-11-28 21:36:51 +000042
Michael Karcherb05b9e12010-07-22 18:04:19 +000043static uint8_t *sb600_spibar = NULL;
Stefan Tauner463dd692013-08-08 12:00:19 +000044enum amd_chipset {
45 CHIPSET_AMD_UNKNOWN,
46 CHIPSET_SB6XX,
47 CHIPSET_SB7XX, /* SP5100 too */
48 CHIPSET_SB89XX, /* Hudson-1 too */
49 CHIPSET_HUDSON234,
Martin Roth82b6ec12014-07-15 13:50:58 +000050 CHIPSET_BOLTON,
Stefan Tauner463dd692013-08-08 12:00:19 +000051 CHIPSET_YANGTZE,
Edward O'Callaghan93737bc2019-10-29 18:30:01 +110052 CHIPSET_PROMONTORY,
Stefan Tauner463dd692013-08-08 12:00:19 +000053};
Stefan Tauner463dd692013-08-08 12:00:19 +000054
Stefan Taunerd5b2aef2014-05-16 21:39:28 +000055#define FIFO_SIZE_OLD 8
Wei Hu31402ee2014-05-16 21:39:33 +000056#define FIFO_SIZE_YANGTZE 71
Stefan Taunerd5b2aef2014-05-16 21:39:28 +000057
Edward O'Callaghan855d6b62020-07-31 12:21:02 +100058struct sb600spi_data {
59 struct flashctx *flash;
60};
61
Edward O'Callaghanc0a27e12019-10-29 17:05:39 +110062static int find_smbus_dev_rev(uint16_t vendor, uint16_t device)
63{
64 struct pci_dev *smbus_dev = pci_dev_find(vendor, device);
65 if (!smbus_dev) {
66 msg_pdbg("No SMBus device with ID %04X:%04X found.\n", vendor, device);
67 msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
68 return -1;
69 }
70 return pci_read_byte(smbus_dev, PCI_REVISION_ID);
71}
72
Edward O'Callaghan9355e6f2019-10-29 18:18:18 +110073/* Determine the chipset's version and identify the respective SMBUS device. */
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110074static enum amd_chipset determine_generation(struct pci_dev *dev)
Stefan Tauner463dd692013-08-08 12:00:19 +000075{
Stefan Tauner4442b812013-09-12 15:48:35 +000076 msg_pdbg2("Trying to determine the generation of the SPI interface... ");
77 if (dev->device_id == 0x438d) {
Stefan Tauner4442b812013-09-12 15:48:35 +000078 msg_pdbg("SB6xx detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110079 return CHIPSET_SB6XX;
Stefan Tauner4442b812013-09-12 15:48:35 +000080 } else if (dev->device_id == 0x439d) {
Edward O'Callaghanc0a27e12019-10-29 17:05:39 +110081 int rev = find_smbus_dev_rev(0x1002, 0x4385);
82 if (rev < 0)
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110083 return CHIPSET_AMD_UNKNOWN;
Stefan Tauner4442b812013-09-12 15:48:35 +000084 if (rev >= 0x39 && rev <= 0x3D) {
Stefan Tauner4442b812013-09-12 15:48:35 +000085 msg_pdbg("SB7xx/SP5100 detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110086 return CHIPSET_SB7XX;
Stefan Tauner4442b812013-09-12 15:48:35 +000087 } else if (rev >= 0x40 && rev <= 0x42) {
Stefan Tauner4442b812013-09-12 15:48:35 +000088 msg_pdbg("SB8xx/SB9xx/Hudson-1 detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110089 return CHIPSET_SB89XX;
Stefan Tauner4442b812013-09-12 15:48:35 +000090 } else {
91 msg_pwarn("SB device found but SMBus revision 0x%02x does not match known values.\n"
92 "Assuming SB8xx/SB9xx/Hudson-1. Please send a log to flashrom@flashrom.org\n",
93 rev);
Edward O'Callaghan0386aa12019-10-30 00:38:16 +110094 return CHIPSET_SB89XX;
Stefan Tauner4442b812013-09-12 15:48:35 +000095 }
96 } else if (dev->device_id == 0x780e) {
Stefan Tauner463dd692013-08-08 12:00:19 +000097 /* The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash)
98 * although they use different SPI interfaces. */
Edward O'Callaghanc0a27e12019-10-29 17:05:39 +110099 int rev = find_smbus_dev_rev(0x1022, 0x780B);
100 if (rev < 0)
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100101 return CHIPSET_AMD_UNKNOWN;
Stefan Tauner463dd692013-08-08 12:00:19 +0000102 if (rev >= 0x11 && rev <= 0x15) {
Stefan Tauner463dd692013-08-08 12:00:19 +0000103 msg_pdbg("Hudson-2/3/4 detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100104 return CHIPSET_HUDSON234;
Martin Roth82b6ec12014-07-15 13:50:58 +0000105 } else if (rev == 0x16) {
Martin Roth82b6ec12014-07-15 13:50:58 +0000106 msg_pdbg("Bolton detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100107 return CHIPSET_BOLTON;
Stefan Tauner5c316f92015-02-08 21:57:52 +0000108 } else if ((rev >= 0x39 && rev <= 0x3A) || rev == 0x42) {
Stefan Tauner463dd692013-08-08 12:00:19 +0000109 msg_pdbg("Yangtze detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100110 return CHIPSET_YANGTZE;
Stefan Tauner463dd692013-08-08 12:00:19 +0000111 } else {
112 msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
113 "Please report this to flashrom@flashrom.org and include this log and\n"
114 "the output of lspci -nnvx, thanks!.\n", rev);
115 }
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100116 } else if (dev->device_id == 0x790e) {
Edward O'Callaghanc0a27e12019-10-29 17:05:39 +1100117 int rev = find_smbus_dev_rev(0x1022, 0x790B);
118 if (rev < 0)
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100119 return CHIPSET_AMD_UNKNOWN;
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100120 if (rev == 0x4a) {
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100121 msg_pdbg("Yangtze detected.\n");
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100122 return CHIPSET_YANGTZE;
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000123 /**
124 * FCH chipsets called 'Promontory' are one's with the
125 * so-called SPI100 ip core that uses memory mapping and
126 * not a ring buffer for transactions. Typically this is
127 * found on both Stoney Ridge and Zen platforms.
128 *
129 * The revisions I have found by searching various lspci
130 * outputs are as follows: 0x4b, 0x59 & 0x61.
131 */
Edward O'Callaghan55583c02020-12-21 12:29:44 +1100132 } else if (rev == 0x4b || rev == 0x51 || rev == 0x59 || rev == 0x61) {
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000133 msg_pdbg("Promontory (rev 0x%02x) detected.\n", rev);
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100134 return CHIPSET_PROMONTORY;
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100135 } else {
136 msg_pwarn("FCH device found but SMBus revision 0x%02x does not match known values.\n"
137 "Please report this to flashrom@flashrom.org and include this log and\n"
138 "the output of lspci -nnvx, thanks!.\n", rev);
139 }
140
141
Stefan Tauner4442b812013-09-12 15:48:35 +0000142 } else
143 msg_pwarn("%s: Unknown LPC device %" PRIx16 ":%" PRIx16 ".\n"
144 "Please report this to flashrom@flashrom.org and include this log and\n"
145 "the output of lspci -nnvx, thanks!\n",
146 __func__, dev->vendor_id, dev->device_id);
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100147
148 msg_perr("Could not determine chipset generation.");
149 return CHIPSET_AMD_UNKNOWN;
Stefan Tauner463dd692013-08-08 12:00:19 +0000150}
Jason Wanga3f04be2008-11-28 21:36:51 +0000151
Carl-Daniel Hailfinger2c7ba8c2009-06-23 00:47:26 +0000152static void reset_internal_fifo_pointer(void)
Jason Wanga3f04be2008-11-28 21:36:51 +0000153{
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000154 mmio_writeb(mmio_readb(sb600_spibar + 2) | 0x10, sb600_spibar + 2);
Jason Wanga3f04be2008-11-28 21:36:51 +0000155
Rudolf Marek70e14592013-07-25 22:58:56 +0000156 /* FIXME: This loop needs a timeout and a clearer message. */
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000157 while (mmio_readb(sb600_spibar + 0xD) & 0x7)
Carl-Daniel Hailfinger643415b2010-01-10 01:59:50 +0000158 msg_pspew("reset\n");
Jason Wanga3f04be2008-11-28 21:36:51 +0000159}
160
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000161static int compare_internal_fifo_pointer(uint8_t want)
162{
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000163 uint8_t have = mmio_readb(sb600_spibar + 0xd) & 0x07;
164 want %= FIFO_SIZE_OLD;
165 if (have != want) {
166 msg_perr("AMD SPI FIFO pointer corruption! Pointer is %d, wanted %d\n", have, want);
167 msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
168 "Please stop all applications and drivers and IPMI which access the flash chip.\n");
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000169 return 1;
170 } else {
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000171 msg_pspew("AMD SPI FIFO pointer is %d, wanted %d\n", have, want);
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000172 return 0;
173 }
174}
175
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000176/* Check the number of bytes to be transmitted and extract opcode. */
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000177static int check_readwritecnt(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt)
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000178{
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000179 unsigned int maxwritecnt = flash->mst->spi.max_data_write + 3;
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000180 if (writecnt > maxwritecnt) {
181 msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n",
182 __func__, writecnt, maxwritecnt);
183 return SPI_INVALID_LENGTH;
184 }
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000185
Stefan Tauner6697f712014-08-06 15:09:15 +0000186 unsigned int maxreadcnt = flash->mst->spi.max_data_read;
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000187 if (readcnt > maxreadcnt) {
188 msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n",
189 __func__, readcnt, maxreadcnt);
190 return SPI_INVALID_LENGTH;
191 }
192 return 0;
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000193}
194
Carl-Daniel Hailfinger2c7ba8c2009-06-23 00:47:26 +0000195static void execute_command(void)
Jason Wanga3f04be2008-11-28 21:36:51 +0000196{
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000197 msg_pspew("Executing... ");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000198 mmio_writeb(mmio_readb(sb600_spibar + 2) | 1, sb600_spibar + 2);
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000199 while (mmio_readb(sb600_spibar + 2) & 1)
Jason Wanga3f04be2008-11-28 21:36:51 +0000200 ;
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000201 msg_pspew("done\n");
Jason Wanga3f04be2008-11-28 21:36:51 +0000202}
203
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000204static int sb600_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000205 unsigned int readcnt,
206 const unsigned char *writearr,
207 unsigned char *readarr)
Jason Wanga3f04be2008-11-28 21:36:51 +0000208{
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000209 /* First byte is cmd which can not be sent through the FIFO. */
Jason Wanga3f04be2008-11-28 21:36:51 +0000210 unsigned char cmd = *writearr++;
Jason Wanga3f04be2008-11-28 21:36:51 +0000211 writecnt--;
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000212 msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
213 mmio_writeb(cmd, sb600_spibar + 0);
Jason Wanga3f04be2008-11-28 21:36:51 +0000214
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000215 int ret = check_readwritecnt(flash, writecnt, readcnt);
216 if (ret != 0)
217 return ret;
Jason Wanga3f04be2008-11-28 21:36:51 +0000218
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000219 /* This is a workaround for a bug in SPI controller. If we only send
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000220 * an opcode and no additional data/address, the SPI controller will
221 * read one byte too few from the chip. Basically, the last byte of
222 * the chip response is discarded and will not end up in the FIFO.
223 * It is unclear if the CS# line is set high too early as well.
224 */
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000225 unsigned int readoffby1 = (writecnt > 0) ? 0 : 1;
226 uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt);
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000227 mmio_writeb(readwrite, sb600_spibar + 1);
Jason Wanga3f04be2008-11-28 21:36:51 +0000228
Jason Wanga3f04be2008-11-28 21:36:51 +0000229 reset_internal_fifo_pointer();
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000230 msg_pspew("Filling FIFO: ");
Nico Huber519be662018-12-23 20:03:35 +0100231 unsigned int count;
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000232 for (count = 0; count < writecnt; count++) {
233 msg_pspew("[%02x]", writearr[count]);
234 mmio_writeb(writearr[count], sb600_spibar + 0xC);
Jason Wanga3f04be2008-11-28 21:36:51 +0000235 }
Carl-Daniel Hailfinger643415b2010-01-10 01:59:50 +0000236 msg_pspew("\n");
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000237 if (compare_internal_fifo_pointer(writecnt))
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000238 return SPI_PROGRAMMER_ERROR;
Jason Wanga3f04be2008-11-28 21:36:51 +0000239
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000240 /*
241 * We should send the data in sequence, which means we need to reset
242 * the FIFO pointer to the first byte we want to send.
243 */
244 reset_internal_fifo_pointer();
Jason Wanga3f04be2008-11-28 21:36:51 +0000245 execute_command();
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000246 if (compare_internal_fifo_pointer(writecnt + readcnt))
247 return SPI_PROGRAMMER_ERROR;
Jason Wanga3f04be2008-11-28 21:36:51 +0000248
249 /*
250 * After the command executed, we should find out the index of the
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000251 * received byte. Here we just reset the FIFO pointer and skip the
252 * writecnt.
253 * It would be possible to increase the FIFO pointer by one instead
254 * of reading and discarding one byte from the FIFO.
255 * The FIFO is implemented on top of an 8 byte ring buffer and the
256 * buffer is never cleared. For every byte that is shifted out after
257 * the opcode, the FIFO already stores the response from the chip.
258 * Usually, the chip will respond with 0x00 or 0xff.
Jason Wanga3f04be2008-11-28 21:36:51 +0000259 */
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000260 reset_internal_fifo_pointer();
Jason Wanga3f04be2008-11-28 21:36:51 +0000261
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000262 /* Skip the bytes we sent. */
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000263 msg_pspew("Skipping: ");
Jason Wanga3f04be2008-11-28 21:36:51 +0000264 for (count = 0; count < writecnt; count++) {
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000265 msg_pspew("[%02x]", mmio_readb(sb600_spibar + 0xC));
Jason Wanga3f04be2008-11-28 21:36:51 +0000266 }
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000267 msg_pspew("\n");
268 if (compare_internal_fifo_pointer(writecnt))
269 return SPI_PROGRAMMER_ERROR;
Jason Wanga3f04be2008-11-28 21:36:51 +0000270
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000271 msg_pspew("Reading FIFO: ");
272 for (count = 0; count < readcnt; count++) {
273 readarr[count] = mmio_readb(sb600_spibar + 0xC);
274 msg_pspew("[%02x]", readarr[count]);
Jason Wanga3f04be2008-11-28 21:36:51 +0000275 }
Carl-Daniel Hailfinger643415b2010-01-10 01:59:50 +0000276 msg_pspew("\n");
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000277 if (compare_internal_fifo_pointer(writecnt+readcnt))
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000278 return SPI_PROGRAMMER_ERROR;
279
280 if (mmio_readb(sb600_spibar + 1) != readwrite) {
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000281 msg_perr("Unexpected change in AMD SPI read/write count!\n");
282 msg_perr("Something else is accessing the flash chip and causes random corruption.\n"
283 "Please stop all applications and drivers and IPMI which access the flash chip.\n");
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000284 return SPI_PROGRAMMER_ERROR;
285 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000286
287 return 0;
288}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000289
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000290static int spi100_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Wei Hu31402ee2014-05-16 21:39:33 +0000291 unsigned int readcnt,
292 const unsigned char *writearr,
293 unsigned char *readarr)
294{
295 /* First byte is cmd which can not be sent through the buffer. */
296 unsigned char cmd = *writearr++;
297 writecnt--;
298 msg_pspew("%s, cmd=0x%02x, writecnt=%d, readcnt=%d\n", __func__, cmd, writecnt, readcnt);
299 mmio_writeb(cmd, sb600_spibar + 0);
300
301 int ret = check_readwritecnt(flash, writecnt, readcnt);
302 if (ret != 0)
303 return ret;
304
305 /* Use the extended TxByteCount and RxByteCount registers. */
306 mmio_writeb(writecnt, sb600_spibar + 0x48);
307 mmio_writeb(readcnt, sb600_spibar + 0x4b);
308
309 msg_pspew("Filling buffer: ");
Nico Huber519be662018-12-23 20:03:35 +0100310 unsigned int count;
Wei Hu31402ee2014-05-16 21:39:33 +0000311 for (count = 0; count < writecnt; count++) {
312 msg_pspew("[%02x]", writearr[count]);
313 mmio_writeb(writearr[count], sb600_spibar + 0x80 + count);
314 }
315 msg_pspew("\n");
316
317 execute_command();
318
319 msg_pspew("Reading buffer: ");
320 for (count = 0; count < readcnt; count++) {
321 readarr[count] = mmio_readb(sb600_spibar + 0x80 + (writecnt + count) % FIFO_SIZE_YANGTZE);
322 msg_pspew("[%02x]", readarr[count]);
323 }
324 msg_pspew("\n");
325
326 return 0;
327}
328
Stefan Taunera6a0d202013-09-15 14:17:39 +0000329struct spispeed {
330 const char *const name;
331 const uint8_t speed;
332};
333
Rob Barnes703de982020-01-21 09:10:51 -0700334static const char* spispeeds[] = {
335 "66 MHz",
336 "33 MHz",
337 "22 MHz",
338 "16.5 MHz",
339 "100 MHz",
340 "Reserved",
341 "Reserved",
342 "800 kHz",
Stefan Taunera6a0d202013-09-15 14:17:39 +0000343};
344
Rob Barnes703de982020-01-21 09:10:51 -0700345static const char* spireadmodes[] = {
346 "Normal (up to 33 MHz)",
347 "Reserved",
348 "Dual IO (1-1-2)",
349 "Quad IO (1-1-4)",
350 "Dual IO (1-2-2)",
351 "Quad IO (1-4-4)",
352 "Normal (up to 66 MHz)",
353 "Fast Read",
354};
355
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100356static int set_speed(struct pci_dev *dev, enum amd_chipset amd_gen, uint8_t speed)
Stefan Taunera6a0d202013-09-15 14:17:39 +0000357{
358 bool success = false;
Stefan Taunera6a0d202013-09-15 14:17:39 +0000359
Rob Barnes703de982020-01-21 09:10:51 -0700360 msg_pdbg("Setting SPI clock to %s (%i)... ", spispeeds[speed], speed);
Wei Hu31402ee2014-05-16 21:39:33 +0000361 if (amd_gen >= CHIPSET_YANGTZE) {
362 rmmio_writew((speed << 12) | (speed << 8) | (speed << 4) | speed, sb600_spibar + 0x22);
363 uint16_t tmp = mmio_readw(sb600_spibar + 0x22);
364 success = (((tmp >> 12) & 0xf) == speed && ((tmp >> 8) & 0xf) == speed &&
365 ((tmp >> 4) & 0xf) == speed && ((tmp >> 0) & 0xf) == speed);
366 } else {
Stefan Taunera6a0d202013-09-15 14:17:39 +0000367 rmmio_writeb((mmio_readb(sb600_spibar + 0xd) & ~(0x3 << 4)) | (speed << 4), sb600_spibar + 0xd);
368 success = (speed == ((mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3));
369 }
370
371 if (!success) {
Rob Barnes703de982020-01-21 09:10:51 -0700372 msg_perr("FAILED!\n");
Stefan Taunera6a0d202013-09-15 14:17:39 +0000373 return 1;
374 }
Rob Barnes703de982020-01-21 09:10:51 -0700375 msg_pdbg("succeeded.\n");
Stefan Taunera6a0d202013-09-15 14:17:39 +0000376 return 0;
377}
378
Rob Barnes703de982020-01-21 09:10:51 -0700379static int set_mode(struct pci_dev *dev, uint8_t mode)
Wei Hu31402ee2014-05-16 21:39:33 +0000380{
Rob Barnes703de982020-01-21 09:10:51 -0700381 msg_pdbg("Setting SPI read mode to %s (%i)... ", spireadmodes[mode], mode);
Wei Hu31402ee2014-05-16 21:39:33 +0000382 uint32_t tmp = mmio_readl(sb600_spibar + 0x00);
383 tmp &= ~(0x6 << 28 | 0x1 << 18); /* Clear mode bits */
Rob Barnes703de982020-01-21 09:10:51 -0700384 tmp |= ((mode & 0x6) << 28) | ((mode & 0x1) << 18);
Wei Hu31402ee2014-05-16 21:39:33 +0000385 rmmio_writel(tmp, sb600_spibar + 0x00);
Rob Barnes703de982020-01-21 09:10:51 -0700386 if (tmp != mmio_readl(sb600_spibar + 0x00)) {
387 msg_perr("FAILED!\n");
Wei Hu31402ee2014-05-16 21:39:33 +0000388 return 1;
Rob Barnes703de982020-01-21 09:10:51 -0700389 }
390 msg_pdbg("succeeded.\n");
Wei Hu31402ee2014-05-16 21:39:33 +0000391 return 0;
392}
393
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100394static int handle_speed(struct pci_dev *dev, enum amd_chipset amd_gen)
Stefan Taunera6a0d202013-09-15 14:17:39 +0000395{
396 uint32_t tmp;
Rob Barnes703de982020-01-21 09:10:51 -0700397 int16_t spispeed_idx = -1;
398 int16_t spireadmode_idx = -1;
399 char *spispeed;
400 char *spireadmode;
Stefan Taunera6a0d202013-09-15 14:17:39 +0000401
Rob Barnes703de982020-01-21 09:10:51 -0700402 spispeed = extract_programmer_param("spispeed");
Stefan Tauner21071b02014-05-16 21:39:48 +0000403 if (spispeed != NULL) {
Carl-Daniel Hailfinger57cdd6b2016-03-12 19:49:14 +0000404 unsigned int i;
405 for (i = 0; i < ARRAY_SIZE(spispeeds); i++) {
Rob Barnes703de982020-01-21 09:10:51 -0700406 if (strcasecmp(spispeeds[i], spispeed) == 0) {
Carl-Daniel Hailfinger57cdd6b2016-03-12 19:49:14 +0000407 spispeed_idx = i;
408 break;
Stefan Tauner21071b02014-05-16 21:39:48 +0000409 }
Stefan Tauner21071b02014-05-16 21:39:48 +0000410 }
Carl-Daniel Hailfinger57cdd6b2016-03-12 19:49:14 +0000411 /* "reserved" is not a valid speed.
412 * Error out on speeds not present in the spispeeds array.
413 * Only Yangtze supports the second half of indices.
414 * No 66 MHz before SB8xx. */
415 if ((strcasecmp(spispeed, "reserved") == 0) ||
416 (i == ARRAY_SIZE(spispeeds)) ||
417 (amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) ||
418 (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0)) {
Stefan Tauner21071b02014-05-16 21:39:48 +0000419 msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed);
420 free(spispeed);
421 return 1;
422 }
423 free(spispeed);
424 }
425
Rob Barnes703de982020-01-21 09:10:51 -0700426 spireadmode = extract_programmer_param("spireadmode");
427 if (spireadmode != NULL) {
428 unsigned int i;
429 for (i = 0; i < ARRAY_SIZE(spireadmodes); i++) {
430 if (strcasecmp(spireadmodes[i], spireadmode) == 0) {
431 spireadmode_idx = i;
432 break;
433 }
434 }
435 if ((strcasecmp(spireadmode, "reserved") == 0) ||
436 (i == ARRAY_SIZE(spireadmodes))) {
437 msg_perr("Error: Invalid spireadmode value: '%s'.\n", spireadmode);
438 free(spireadmode);
439 return 1;
440 }
441 if (amd_gen < CHIPSET_BOLTON) {
442 msg_perr("Warning: spireadmode not supported for this chipset.");
443 }
444 free(spireadmode);
445 }
446
Stefan Taunera6a0d202013-09-15 14:17:39 +0000447 /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used.
Martin Roth82b6ec12014-07-15 13:50:58 +0000448 * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 bolton/yangtze
Stefan Taunera6a0d202013-09-15 14:17:39 +0000449 * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0]
450 * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]
451 */
Martin Roth82b6ec12014-07-15 13:50:58 +0000452 if (amd_gen >= CHIPSET_BOLTON) {
Rob Barnes703de982020-01-21 09:10:51 -0700453
Wei Hu31402ee2014-05-16 21:39:33 +0000454 tmp = mmio_readl(sb600_spibar + 0x00);
455 uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1);
Rob Barnes703de982020-01-21 09:10:51 -0700456 msg_pdbg("SPI read mode is %s (%i)\n",
457 spireadmodes[read_mode], read_mode);
458 if (spireadmode_idx < 0) {
459 msg_perr("Warning: spireadmode not set, "
460 "leaving spireadmode unchanged.");
461 }
462 else if (set_mode(dev, spireadmode_idx) != 0) {
463 return 1;
Wei Hu31402ee2014-05-16 21:39:33 +0000464 }
465
Martin Roth82b6ec12014-07-15 13:50:58 +0000466 if (amd_gen >= CHIPSET_YANGTZE) {
467 tmp = mmio_readb(sb600_spibar + 0x20);
468 msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis");
469 if ((tmp & 0x1) == 0) {
470 rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20);
471 tmp = mmio_readb(sb600_spibar + 0x20) & 0x1;
472 if (tmp == 0) {
473 msg_perr("Enabling Spi100 failed.\n");
474 return 1;
475 }
476 msg_pdbg("Enabling Spi100 succeeded.\n");
477 }
478
479 tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */
Rob Barnes703de982020-01-21 09:10:51 -0700480 msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf]);
481 msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf]);
482 msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf]);
483 msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf]);
Martin Roth82b6ec12014-07-15 13:50:58 +0000484 }
Wei Hu31402ee2014-05-16 21:39:33 +0000485 } else {
Stefan Taunera6a0d202013-09-15 14:17:39 +0000486 if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) {
487 bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;
488 msg_pdbg("Fast Reads are %sabled\n", fast_read ? "en" : "dis");
489 if (fast_read) {
490 msg_pdbg("Disabling them temporarily.\n");
491 rmmio_writel(mmio_readl(sb600_spibar + 0x00) & ~(0x1 << 18),
492 sb600_spibar + 0x00);
493 }
494 }
495 tmp = (mmio_readb(sb600_spibar + 0xd) >> 4) & 0x3;
Rob Barnes703de982020-01-21 09:10:51 -0700496 msg_pdbg("NormSpeed is %s\n", spispeeds[tmp]);
497 if (spispeed_idx < 0) {
498 spispeed_idx = 3; /* Default to 16.5 MHz */
499 }
Stefan Taunera6a0d202013-09-15 14:17:39 +0000500 }
Rob Barnes703de982020-01-21 09:10:51 -0700501 if (spispeed_idx < 0) {
502 msg_perr("Warning: spispeed not set, leaving spispeed unchanged.");
503 return 0;
504 }
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100505 return set_speed(dev, amd_gen, spispeed_idx);
Stefan Taunera6a0d202013-09-15 14:17:39 +0000506}
507
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100508static int handle_imc(struct pci_dev *dev, enum amd_chipset amd_gen)
Rudolf Marek70e14592013-07-25 22:58:56 +0000509{
510 /* Handle IMC everywhere but sb600 which does not have one. */
Stefan Tauner4442b812013-09-12 15:48:35 +0000511 if (amd_gen == CHIPSET_SB6XX)
Rudolf Marek70e14592013-07-25 22:58:56 +0000512 return 0;
513
Stefan Taunerd5b2aef2014-05-16 21:39:28 +0000514 bool amd_imc_force = false;
515 char *arg = extract_programmer_param("amd_imc_force");
516 if (arg && !strcmp(arg, "yes")) {
517 amd_imc_force = true;
518 msg_pspew("amd_imc_force enabled.\n");
519 } else if (arg && !strlen(arg)) {
520 msg_perr("Missing argument for amd_imc_force.\n");
521 free(arg);
522 return 1;
523 } else if (arg) {
524 msg_perr("Unknown argument for amd_imc_force: \"%s\" (not \"yes\").\n", arg);
525 free(arg);
526 return 1;
527 }
528 free(arg);
529
Rudolf Marek70e14592013-07-25 22:58:56 +0000530 /* TODO: we should not only look at IntegratedImcPresent (LPC Dev 20, Func 3, 40h) but also at
Stefan Tauner5c316f92015-02-08 21:57:52 +0000531 * IMCEnable(Strap) and Override EcEnable(Strap) (sb8xx, sb9xx?, a50, Bolton: Misc_Reg: 80h-87h;
Rudolf Marek70e14592013-07-25 22:58:56 +0000532 * sb7xx, sp5100: PM_Reg: B0h-B1h) etc. */
533 uint8_t reg = pci_read_byte(dev, 0x40);
534 if ((reg & (1 << 7)) == 0) {
535 msg_pdbg("IMC is not active.\n");
536 return 0;
537 }
538
539 if (!amd_imc_force)
540 programmer_may_write = 0;
Stefan Tauner463dd692013-08-08 12:00:19 +0000541 msg_pinfo("Writes have been disabled for safety reasons because the presence of the IMC\n"
542 "was detected and it could interfere with accessing flash memory. Flashrom will\n"
543 "try to disable it temporarily but even then this might not be safe:\n"
Stefan Tauner0be072c2016-03-13 15:16:30 +0000544 "when it is re-enabled and after a reboot it expects to find working code\n"
Rudolf Marek70e14592013-07-25 22:58:56 +0000545 "in the flash and it is unpredictable what happens if there is none.\n"
546 "\n"
547 "To be safe make sure that there is a working IMC firmware at the right\n"
548 "location in the image you intend to write and do not attempt to erase.\n"
549 "\n"
550 "You can enforce write support with the amd_imc_force programmer option.\n");
551 if (amd_imc_force)
552 msg_pinfo("Continuing with write support because the user forced us to!\n");
553
554 return amd_imc_shutdown(dev);
555}
556
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000557static int promontory_read_memmapped(struct flashctx *flash, uint8_t *buf,
558 unsigned int start, unsigned int len)
559{
560 struct sb600spi_data * data = (struct sb600spi_data *)flash->mst->spi.data;
561 if (!data->flash) {
562 map_flash(flash);
563 data->flash = flash; /* keep a copy of flashctx for unmap() on tear-down. */
564 }
565 mmio_readn((void *)(flash->virtual_memory + start), buf, len);
566 return 0;
567}
568
Edward O'Callaghan97dcc972020-11-17 19:27:13 +1100569static struct spi_master spi_master_sb600 = {
570 .max_data_read = FIFO_SIZE_OLD,
571 .max_data_write = FIFO_SIZE_OLD - 3,
572 .command = sb600_spi_send_command,
573 .multicommand = default_spi_send_multicommand,
574 .read = default_spi_read,
575 .write_256 = default_spi_write_256,
576 .write_aai = default_spi_write_aai,
577};
578
579static struct spi_master spi_master_yangtze = {
580 .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */
581 .max_data_write = FIFO_SIZE_YANGTZE - 3,
582 .command = spi100_spi_send_command,
583 .multicommand = default_spi_send_multicommand,
584 .read = default_spi_read,
585 .write_256 = default_spi_write_256,
586 .write_aai = default_spi_write_aai,
587};
588
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000589static struct spi_master spi_master_promontory = {
590 .max_data_read = MAX_DATA_READ_UNLIMITED,
591 .max_data_write = FIFO_SIZE_YANGTZE - 3,
592 .command = spi100_spi_send_command,
593 .multicommand = default_spi_send_multicommand,
594 .read = promontory_read_memmapped,
595 .write_256 = default_spi_write_256,
596 .write_aai = default_spi_write_aai,
597};
598
599static int sb600spi_shutdown(void *data)
600{
601 struct flashctx *flash = ((struct sb600spi_data *)data)->flash;
602 if (flash)
603 finalize_flash_access(flash);
604 free(data);
605 return 0;
606}
607
Michael Karcherb05b9e12010-07-22 18:04:19 +0000608int sb600_probe_spi(struct pci_dev *dev)
609{
610 struct pci_dev *smbus_dev;
611 uint32_t tmp;
612 uint8_t reg;
Rudolf Marek70e14592013-07-25 22:58:56 +0000613
Michael Karcherb05b9e12010-07-22 18:04:19 +0000614 /* Read SPI_BaseAddr */
615 tmp = pci_read_long(dev, 0xa0);
616 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
617 msg_pdbg("SPI base address is at 0x%x\n", tmp);
618
619 /* If the BAR has address 0, it is unlikely SPI is used. */
620 if (!tmp)
621 return 0;
622
623 /* Physical memory has to be mapped at page (4k) boundaries. */
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000624 sb600_spibar = rphysmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000);
625 if (sb600_spibar == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000626 return ERROR_FATAL;
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000627
Michael Karcherb05b9e12010-07-22 18:04:19 +0000628 /* The low bits of the SPI base address are used as offset into
629 * the mapped page.
630 */
631 sb600_spibar += tmp & 0xfff;
632
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100633 enum amd_chipset amd_gen = determine_generation(dev);
634 if (amd_gen == CHIPSET_AMD_UNKNOWN)
Stefan Tauner4442b812013-09-12 15:48:35 +0000635 return ERROR_NONFATAL;
Stefan Tauner463dd692013-08-08 12:00:19 +0000636
Stefan Tauner4442b812013-09-12 15:48:35 +0000637 /* How to read the following table and similar ones in this file:
638 * "?" means we have no datasheet for this chipset generation or it doesn't have any relevant info.
639 * "<-" means the bit/register meaning is identical to the next non-"?" chipset to the left. "<-" thus
640 * never refers to another "?".
641 * If a "?" chipset is between two chipsets with identical meaning, we assume the meaning didn't change
642 * twice in between, i.e. the meaning is unchanged for the "?" chipset. Usually we assume that
643 * succeeding hardware supports the same functionality as its predecessor unless proven different by
644 * tests or documentation, hence "?" will often be implemented equally to "<-".
645 *
646 * Chipset support matrix for SPI Base_Addr (LPC PCI reg 0xa0)
647 * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze
648 * 3 rsvd <- <- ? <- ? RouteTpm2Spi
649 * 2 rsvd AbortEnable rsvd ? <- ? <-
650 * 1 rsvd SpiRomEnable <- ? <- ? <-
651 * 0 rsvd AltSpiCSEnable rsvd ? <- ? <-
652 */
653 if (amd_gen >= CHIPSET_SB7XX) {
654 tmp = pci_read_long(dev, 0xa0);
655 msg_pdbg("SpiRomEnable=%i", (tmp >> 1) & 0x1);
656 if (amd_gen == CHIPSET_SB7XX)
657 msg_pdbg(", AltSpiCSEnable=%i, AbortEnable=%i", tmp & 0x1, (tmp >> 2) & 0x1);
Edward O'Callaghan93737bc2019-10-29 18:30:01 +1100658 else if (amd_gen >= CHIPSET_YANGTZE)
Wei Hu31402ee2014-05-16 21:39:33 +0000659 msg_pdbg(", RouteTpm2Sp=%i", (tmp >> 3) & 0x1);
Michael Karcherb05b9e12010-07-22 18:04:19 +0000660
Stefan Tauner4442b812013-09-12 15:48:35 +0000661 tmp = pci_read_byte(dev, 0xba);
662 msg_pdbg(", PrefetchEnSPIFromIMC=%i", (tmp & 0x4) >> 2);
663
664 tmp = pci_read_byte(dev, 0xbb);
665 /* FIXME: Set bit 3,6,7 if not already set.
666 * Set bit 5, otherwise SPI accesses are pointless in LPC mode.
667 * See doc 42413 AMD SB700/710/750 RPR.
668 */
669 if (amd_gen == CHIPSET_SB7XX)
670 msg_pdbg(", SpiOpEnInLpcMode=%i", (tmp >> 5) & 0x1);
671 msg_pdbg(", PrefetchEnSPIFromHost=%i\n", tmp & 0x1);
672 }
673
674 /* Chipset support matrix for SPI_Cntrl0 (spibar + 0x0)
675 * See the chipset support matrix for SPI Base_Addr above for an explanation of the symbols used.
676 * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson2+ yangtze
677 * 17 rsvd <- <- ? <- ? <-
Stefan Taunera6a0d202013-09-15 14:17:39 +0000678 * 18 rsvd <- fastReadEnable<1> ? <- ? SpiReadMode[0]<1>
Stefan Tauner4442b812013-09-12 15:48:35 +0000679 * 19 SpiArbEnable <- <- ? <- ? <-
680 * 20 (FifoPtrClr) <- <- ? <- ? <-
681 * 21 (FifoPtrInc) <- <- ? <- ? IllegalAccess
682 * 22 SpiAccessMacRomEn <- <- ? <- ? <-
683 * 23 SpiHostAccessRomEn <- <- ? <- ? <-
684 * 24:26 ArbWaitCount <- <- ? <- ? <-
685 * 27 SpiBridgeDisable <- <- ? <- ? rsvd
686 * 28 rsvd DropOneClkOnRd = SPIClkGate ? <- ? <-
Stefan Taunera6a0d202013-09-15 14:17:39 +0000687 * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1]<1>
Stefan Tauner4442b812013-09-12 15:48:35 +0000688 * 31 rsvd <- SpiBusy ? <- ? <-
Stefan Taunera6a0d202013-09-15 14:17:39 +0000689 *
690 * <1> see handle_speed
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000691 */
Stefan Tauner4442b812013-09-12 15:48:35 +0000692 tmp = mmio_readl(sb600_spibar + 0x00);
693 msg_pdbg("(0x%08" PRIx32 ") SpiArbEnable=%i", tmp, (tmp >> 19) & 0x1);
Edward O'Callaghan93737bc2019-10-29 18:30:01 +1100694 if (amd_gen >= CHIPSET_YANGTZE)
Wei Hu31402ee2014-05-16 21:39:33 +0000695 msg_pdbg(", IllegalAccess=%i", (tmp >> 21) & 0x1);
Stefan Tauner4442b812013-09-12 15:48:35 +0000696
697 msg_pdbg(", SpiAccessMacRomEn=%i, SpiHostAccessRomEn=%i, ArbWaitCount=%i",
698 (tmp >> 22) & 0x1, (tmp >> 23) & 0x1, (tmp >> 24) & 0x7);
699
Edward O'Callaghan93737bc2019-10-29 18:30:01 +1100700 if (amd_gen < CHIPSET_YANGTZE)
Stefan Tauner4442b812013-09-12 15:48:35 +0000701 msg_pdbg(", SpiBridgeDisable=%i", (tmp >> 27) & 0x1);
702
703 switch (amd_gen) {
704 case CHIPSET_SB7XX:
705 msg_pdbg(", DropOneClkOnRd/SpiClkGate=%i", (tmp >> 28) & 0x1);
Richard Hughesdb7482b2018-12-19 12:04:30 +0000706 /* Fall through. */
Stefan Tauner4442b812013-09-12 15:48:35 +0000707 case CHIPSET_SB89XX:
708 case CHIPSET_HUDSON234:
Wei Hu31402ee2014-05-16 21:39:33 +0000709 case CHIPSET_YANGTZE:
Edward O'Callaghan93737bc2019-10-29 18:30:01 +1100710 case CHIPSET_PROMONTORY:
Stefan Tauner4442b812013-09-12 15:48:35 +0000711 msg_pdbg(", SpiBusy=%i", (tmp >> 31) & 0x1);
712 default: break;
713 }
714 msg_pdbg("\n");
715
716 if (((tmp >> 22) & 0x1) == 0 || ((tmp >> 23) & 0x1) == 0) {
717 msg_perr("ERROR: State of SpiAccessMacRomEn or SpiHostAccessRomEn prohibits full access.\n");
718 return ERROR_NONFATAL;
719 }
720
Stefan Tauner4442b812013-09-12 15:48:35 +0000721 if (amd_gen >= CHIPSET_SB89XX) {
722 tmp = mmio_readb(sb600_spibar + 0x1D);
723 msg_pdbg("Using SPI_CS%d\n", tmp & 0x3);
Wei Hu31402ee2014-05-16 21:39:33 +0000724 /* FIXME: Handle SpiProtect* configuration on Yangtze. */
Stefan Tauner4442b812013-09-12 15:48:35 +0000725 }
726
Michael Karcherb05b9e12010-07-22 18:04:19 +0000727 /* Look for the SMBus device. */
728 smbus_dev = pci_dev_find(0x1002, 0x4385);
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100729 if (!smbus_dev)
Stefan Tauner463dd692013-08-08 12:00:19 +0000730 smbus_dev = pci_dev_find(0x1022, 0x780b); /* AMD FCH */
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +0100731 if (!smbus_dev)
732 smbus_dev = pci_dev_find(0x1022, 0x790b); /* AMD FP4 */
733 if (!smbus_dev) {
734 msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
735 return ERROR_NONFATAL;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000736 }
737
738 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
739 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
740 reg = pci_read_byte(smbus_dev, 0xAB);
741 reg &= 0xC0;
742 msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
743 msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
744 if (reg != 0x00) {
745 msg_pdbg("Not enabling SPI");
746 return 0;
747 }
748 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
749 reg = pci_read_byte(smbus_dev, 0x83);
750 reg &= 0xC0;
751 msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
752 msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
753 /* SPI_HOLD is not used on all boards, filter it out. */
754 if ((reg & 0x80) != 0x00) {
755 msg_pdbg("Not enabling SPI");
756 return 0;
757 }
758 /* GPIO47/SPI_CLK status */
759 reg = pci_read_byte(smbus_dev, 0xA7);
760 reg &= 0x40;
761 msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
762 if (reg != 0x00) {
763 msg_pdbg("Not enabling SPI");
764 return 0;
765 }
766
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100767 if (handle_speed(dev, amd_gen) != 0)
Stefan Taunera6a0d202013-09-15 14:17:39 +0000768 return ERROR_FATAL;
769
Edward O'Callaghan0386aa12019-10-30 00:38:16 +1100770 if (handle_imc(dev, amd_gen) != 0)
Rudolf Marek70e14592013-07-25 22:58:56 +0000771 return ERROR_FATAL;
Carl-Daniel Hailfinger39446e32010-09-15 12:02:07 +0000772
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000773 struct sb600spi_data *data = calloc(1, sizeof(struct sb600spi_data));
774 if (!data) {
775 msg_perr("Unable to allocate space for extra SPI master data.\n");
776 return SPI_GENERIC_ERROR;
777 }
778
779 data->flash = NULL;
780
781 register_shutdown(sb600spi_shutdown, data);
782 spi_master_sb600.data = data;
783 spi_master_yangtze.data = data;
784 spi_master_promontory.data = data;
785
786
Wei Hu31402ee2014-05-16 21:39:33 +0000787 /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */
Edward O'Callaghan93737bc2019-10-29 18:30:01 +1100788 if (amd_gen < CHIPSET_YANGTZE)
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000789 register_spi_master(&spi_master_sb600);
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000790 else if (amd_gen == CHIPSET_YANGTZE)
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000791 register_spi_master(&spi_master_yangtze);
Edward O'Callaghan855d6b62020-07-31 12:21:02 +1000792 else
793 register_spi_master(&spi_master_promontory);
794
Michael Karcherb05b9e12010-07-22 18:04:19 +0000795 return 0;
796}
797
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000798#endif