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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Nico Huber93c30692017-03-20 14:25:09 +010010 * Copyright (C) 2017 secunet Security Networks AG
11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
Ollie Lho184a4042005-11-26 21:55:36 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
Uwe Hermannd1107642007-08-29 17:52:32 +000021 */
22
23/*
24 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000025 */
26
Lane Brooksd54958a2007-11-13 16:45:22 +000027#define _LARGEFILE64_SOURCE
28
Ollie Lhocbbf1252004-03-17 22:22:08 +000029#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000030#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000031#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000032#include <inttypes.h>
33#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000034#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000035#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000036#include "hwaccess.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000040#if defined(__i386__) || defined(__x86_64__)
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000052 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000053
54 return 0;
55}
56
Rudolf Marek23907d82012-02-07 21:29:48 +000057static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 /* enable ROMCS for writes */
62 tmp = pci_read_byte(dev, 0x43);
63 tmp |= 0x80;
64 pci_write_byte(dev, 0x43, tmp);
65
66 /* read the bootstrapping register */
67 tmp = pci_read_byte(dev, 0x40) & 0x3;
68 switch (tmp) {
69 case 3:
Nico Huber2e50cdc2018-09-23 20:20:26 +020070 internal_buses_supported &= BUS_FWH;
Rudolf Marek23907d82012-02-07 21:29:48 +000071 break;
72 case 2:
Nico Huber2e50cdc2018-09-23 20:20:26 +020073 internal_buses_supported &= BUS_LPC;
Rudolf Marek23907d82012-02-07 21:29:48 +000074 break;
75 default:
Nico Huber2e50cdc2018-09-23 20:20:26 +020076 internal_buses_supported &= BUS_PARALLEL;
Rudolf Marek23907d82012-02-07 21:29:48 +000077 break;
78 }
79
80 return 0;
81}
82
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000083static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
84{
85 uint8_t tmp;
86
87 tmp = pci_read_byte(dev, 0xd0);
88 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000089 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000090
91 return 0;
92}
93
94static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
95{
Stefan Taunere34e3e82013-01-01 00:06:51 +000096 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000097 uint8_t new, newer;
98
99 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
100 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000101 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000102 new &= (~0x04); /* No idea why we clear bit 2. */
103 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000104 rpci_write_byte(dev, SIS_MAPREG, new);
105 newer = pci_read_byte(dev, SIS_MAPREG);
106 if (newer != new) { /* FIXME: share this with other code? */
107 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
108 SIS_MAPREG, new, name);
109 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000110 return -1;
111 }
112 return 0;
113}
114
115static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
116{
117 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000118
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000119 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
120 if (!sbdev)
121 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
122 if (!sbdev)
123 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
124 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000125 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000126 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000127 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000128 sbdev->vendor_id, sbdev->device_id,
129 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000130 return sbdev;
131}
132
133static int enable_flash_sis501(struct pci_dev *dev, const char *name)
134{
135 uint8_t tmp;
136 int ret = 0;
137 struct pci_dev *sbdev;
138
139 sbdev = find_southbridge(dev->vendor_id, name);
140 if (!sbdev)
141 return -1;
142
143 ret = enable_flash_sis_mapping(sbdev, name);
144
145 tmp = sio_read(0x22, 0x80);
146 tmp &= (~0x20);
147 tmp |= 0x4;
148 sio_write(0x22, 0x80, tmp);
149
150 tmp = sio_read(0x22, 0x70);
151 tmp &= (~0x20);
152 tmp |= 0x4;
153 sio_write(0x22, 0x70, tmp);
Elyes HAOUAS2f1d0072018-10-04 10:42:42 +0200154
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000155 return ret;
156}
157
158static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
159{
160 uint8_t tmp;
161 int ret = 0;
162 struct pci_dev *sbdev;
163
164 sbdev = find_southbridge(dev->vendor_id, name);
165 if (!sbdev)
166 return -1;
167
168 ret = enable_flash_sis_mapping(sbdev, name);
169
170 tmp = sio_read(0x22, 0x50);
171 tmp &= (~0x20);
172 tmp |= 0x4;
173 sio_write(0x22, 0x50, tmp);
174
175 return ret;
176}
177
Stefan Taunere34e3e82013-01-01 00:06:51 +0000178static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000179{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000180 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000181 uint8_t new, newer;
182 int ret = 0;
183 struct pci_dev *sbdev;
184
185 sbdev = find_southbridge(dev->vendor_id, name);
186 if (!sbdev)
187 return -1;
188
189 ret = enable_flash_sis_mapping(sbdev, name);
190
Stefan Taunere34e3e82013-01-01 00:06:51 +0000191 new = pci_read_byte(sbdev, SIS_REG);
192 new &= (~dis_mask);
193 new |= en_mask;
194 rpci_write_byte(sbdev, SIS_REG, new);
195 newer = pci_read_byte(sbdev, SIS_REG);
196 if (newer != new) { /* FIXME: share this with other code? */
197 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
198 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000199 ret = -1;
200 }
201
202 return ret;
203}
204
Stefan Taunere34e3e82013-01-01 00:06:51 +0000205static int enable_flash_sis530(struct pci_dev *dev, const char *name)
206{
207 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
208}
209
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000210static int enable_flash_sis540(struct pci_dev *dev, const char *name)
211{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000212 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000213}
214
Uwe Hermann987942d2006-11-07 11:16:21 +0000215/* Datasheet:
216 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
217 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
218 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
219 * - Order Number: 290562-001
220 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000221static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000222{
223 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000224 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000225
Nico Huber2e50cdc2018-09-23 20:20:26 +0200226 internal_buses_supported &= BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000227
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000228 old = pci_read_word(dev, xbcs);
229
230 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000231 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000232 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 * Set bit 7: Extended BIOS Enable (PCI master accesses to
234 * FFF80000-FFFDFFFF are forwarded to ISA).
235 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
236 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
237 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
238 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
239 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
240 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
241 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000242 if (dev->device_id == 0x122e || dev->device_id == 0x7000
243 || dev->device_id == 0x1234)
244 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000245 else
246 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000247
248 if (new == old)
249 return 0;
250
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000251 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000252
Stefan Taunere34e3e82013-01-01 00:06:51 +0000253 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
254 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000255 return -1;
256 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000257
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000258 return 0;
259}
260
Duncan Laurie4095ed72014-08-20 15:39:32 +0000261/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
262 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
263 *
264 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000265 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000266static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
267 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000268{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000269 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000270
Stefan Tauner92d6a862013-10-25 00:33:37 +0000271 switch (ich_generation) {
272 case CHIPSET_ICH_UNKNOWN:
273 return ERROR_FATAL;
274 /* Non-SPI-capable */
275 case CHIPSET_ICH:
276 case CHIPSET_ICH2345:
277 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000278 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
279 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000280 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
281 * mentions that the prefetching and caching does only happen for direct memory reads.
282 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
283 * programmed access only and not memory mapping. */
284 case CHIPSET_TUNNEL_CREEK:
285 case CHIPSET_POULSBO:
286 case CHIPSET_CENTERTON:
287 old = pci_read_byte(dev, bios_cntl + 1);
288 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
289 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000290 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000291 case CHIPSET_ICH7:
292 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000293 if (ich_generation == CHIPSET_BAYTRAIL)
294 old = (mmio_readl(addr) >> 2) & 0x3;
295 else
296 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000297 msg_pdbg("SPI Read Configuration: ");
298 if (old == 3)
299 msg_pdbg("invalid prefetching/caching settings, ");
300 else
301 msg_pdbg("prefetching %sabled, caching %sabled, ",
302 (old & 0x2) ? "en" : "dis",
303 (old & 0x1) ? "dis" : "en");
304 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000305
Duncan Laurie4095ed72014-08-20 15:39:32 +0000306 if (ich_generation == CHIPSET_BAYTRAIL)
307 wanted = old = mmio_readl(addr);
308 else
309 wanted = old = pci_read_byte(dev, bios_cntl);
310
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000311 /*
312 * Quote from the 6 Series datasheet (Document Number: 324645-004):
313 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
314 * 1 = BIOS region SMM protection is enabled.
315 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000316 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000317 *
318 * Try to unset it in any case.
319 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000320 *
321 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
322 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000323 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000324 int smm_bwp_bit;
325 if (ich_generation == CHIPSET_CENTERTON)
326 smm_bwp_bit = 7;
327 else
328 smm_bwp_bit = 5;
329 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000330
Stefan Tauner92d6a862013-10-25 00:33:37 +0000331 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
332 if (ich_generation == CHIPSET_TUNNEL_CREEK)
333 wanted |= (1 << 2);
334
335 wanted |= (1 << 0); /* Set BIOS Write Enable */
336 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000337
338 /* Only write the register if it's necessary */
339 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000340 if (ich_generation == CHIPSET_BAYTRAIL) {
341 rmmio_writel(wanted, addr);
342 new = mmio_readl(addr);
343 } else {
344 rpci_write_byte(dev, bios_cntl, wanted);
345 new = pci_read_byte(dev, bios_cntl);
346 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000347 } else
348 new = old;
349
350 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
351 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
352 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000353 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000354 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000355
Stefan Reinauer62218c32012-08-26 02:35:13 +0000356 if (new != wanted)
Angel Pons84bfddc2020-04-29 15:23:59 +0200357 msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n"
Stefan Tauner92d6a862013-10-25 00:33:37 +0000358 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000359
Stefan Tauner92d6a862013-10-25 00:33:37 +0000360 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000361 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000362 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000363
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000364 return 0;
365}
366
Duncan Laurie4095ed72014-08-20 15:39:32 +0000367static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
368 uint8_t bios_cntl)
369{
370 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
371}
372
373static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
374{
375 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
376}
377
Stefan Tauner92d6a862013-10-25 00:33:37 +0000378static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000379{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000380 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
381 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000382 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000383 switch (ich_generation) {
384 case CHIPSET_ICH:
385 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
386 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
387 break;
388 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000389 fwh_sel1 = 0xe8;
390 fwh_sel2 = 0xee;
391 fwh_dec_en_lo = 0xf0;
392 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000393 implemented = 1;
394 break;
395 case CHIPSET_POULSBO:
396 case CHIPSET_TUNNEL_CREEK:
397 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
398 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
399 break;
400 case CHIPSET_CENTERTON:
401 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
402 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000403 case CHIPSET_BAYTRAIL: {
404 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
405 if (ilb_base == 0) {
406 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
407 return ERROR_FATAL;
408 }
409 ilb = rphysmap("BYT IBASE", ilb_base, 512);
410 fwh_sel1 = 0x18;
411 fwh_dec_en_lo = 0xd8;
412 fwh_dec_en_hi = 0xd9;
413 implemented = 1;
414 break;
415 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000416 case CHIPSET_ICH6:
417 case CHIPSET_ICH7:
418 default: /* Future version might behave the same */
419 fwh_sel1 = 0xd0;
420 fwh_sel2 = 0xd4;
421 fwh_dec_en_lo = 0xd8;
422 fwh_dec_en_hi = 0xd9;
423 implemented = 1;
424 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000425 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000426
Stefan Tauner92d6a862013-10-25 00:33:37 +0000427 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000428 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000429 if (!implemented) {
430 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
431 goto idsel_garbage_out;
432 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000433 errno = 0;
434 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000435 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000436 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000437 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000438 goto idsel_garbage_out;
439 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000440 uint64_t fwh_mask = 0xffffffff;
441 if (fwh_sel2 > 0)
442 fwh_mask |= (0xffffULL << 32);
443 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000444 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000445 goto idsel_garbage_out;
446 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000447 uint64_t fwh_idsel_old;
448 if (ich_generation == CHIPSET_BAYTRAIL) {
449 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
450 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
451 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000452 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000453 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
454 if (fwh_sel2 > 0) {
455 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
456 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
457 }
458 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000459 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000460 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000461 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000462 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000463 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000464idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000465 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000466 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000467 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000468 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000469
Stefan Tauner92d6a862013-10-25 00:33:37 +0000470 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000471 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000472 return 0;
473 }
474
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000475 /* Ignore all legacy ranges below 1 MB.
476 * We currently only support flashing the chip which responds to
477 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
478 * have to be adjusted.
479 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000480 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
481 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000482 uint32_t fwh_conf;
483 if (ich_generation == CHIPSET_BAYTRAIL)
484 fwh_conf = mmio_readl(ilb + fwh_sel1);
485 else
486 fwh_conf = pci_read_long(dev, fwh_sel1);
487
Stefan Tauner92d6a862013-10-25 00:33:37 +0000488 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000489 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000490 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000491 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000492 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000493 (0x1ff8 + i) * 0x80000,
494 (0x1ff0 + i) * 0x80000,
495 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000496 if ((tmp == 0) && contiguous) {
497 max_decode_fwh_idsel = (8 - i) * 0x80000;
498 } else {
499 contiguous = 0;
500 }
501 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000502 if (fwh_sel2 > 0) {
503 /* FWH_SEL2 */
504 fwh_conf = pci_read_word(dev, fwh_sel2);
505 for (i = 3; i >= 0; i--) {
506 int tmp = (fwh_conf >> (i * 4)) & 0xf;
507 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
508 (0xff4 + i) * 0x100000,
509 (0xff0 + i) * 0x100000,
510 tmp);
511 if ((tmp == 0) && contiguous) {
512 max_decode_fwh_idsel = (8 - i) * 0x100000;
513 } else {
514 contiguous = 0;
515 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000516 }
517 }
518 contiguous = 1;
519 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000520 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
521 fwh_conf <<= 8;
522 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000523 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000524 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000525 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000526 (0x1ff8 + i) * 0x80000,
527 (0x1ff0 + i) * 0x80000,
528 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000529 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000530 max_decode_fwh_decode = (8 - i) * 0x80000;
531 } else {
532 contiguous = 0;
533 }
534 }
535 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000536 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000537 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000538 (0xff4 + i) * 0x100000,
539 (0xff0 + i) * 0x100000,
540 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000541 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000542 max_decode_fwh_decode = (8 - i) * 0x100000;
543 } else {
544 contiguous = 0;
545 }
546 }
547 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000548 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000549
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000550 return 0;
551}
552
Stefan Tauner92d6a862013-10-25 00:33:37 +0000553static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000554{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000555 int err;
556
557 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000558 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000559 return err;
560
Nico Huber2e50cdc2018-09-23 20:20:26 +0200561 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000562 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000563}
564
Stefan Tauner92d6a862013-10-25 00:33:37 +0000565static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000566{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000567 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000568}
569
Stefan Tauner92d6a862013-10-25 00:33:37 +0000570static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000571{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000572 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000573}
574
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000575static int enable_flash_ich6(struct pci_dev *dev, const char *name)
576{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000577 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000578}
579
Adam Jurkowskie4984102009-12-21 15:30:46 +0000580static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
581{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000582 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000583}
584
Nico Huber2e50cdc2018-09-23 20:20:26 +0200585static enum chipbustype enable_flash_ich_report_gcs(
586 struct pci_dev *const dev, const enum ich_chipset ich_generation, const uint8_t *const rcrb)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000587{
Nico Huber0ea99f52017-03-17 17:22:53 +0100588 uint32_t gcs;
Nico Huber93c30692017-03-20 14:25:09 +0100589 const char *reg_name;
590 bool bild, top_swap;
Nico Huber0ea99f52017-03-17 17:22:53 +0100591
592 switch (ich_generation) {
593 case CHIPSET_BAYTRAIL:
Nico Huber93c30692017-03-20 14:25:09 +0100594 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100595 gcs = mmio_readl(rcrb + 0);
Nico Huber93c30692017-03-20 14:25:09 +0100596 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100597 top_swap = (gcs & 2) >> 1;
598 break;
Nico Huber93c30692017-03-20 14:25:09 +0100599 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700600 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100601 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500602 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huber37509862019-01-18 14:23:02 +0100603 case CHIPSET_APOLLO_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100604 reg_name = "BIOS_SPI_BC";
605 gcs = pci_read_long(dev, 0xdc);
606 bild = (gcs >> 7) & 1;
607 top_swap = (gcs >> 4) & 1;
608 break;
Nico Huber0ea99f52017-03-17 17:22:53 +0100609 default:
Nico Huber93c30692017-03-20 14:25:09 +0100610 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100611 gcs = mmio_readl(rcrb + 0x3410);
Nico Huber93c30692017-03-20 14:25:09 +0100612 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100613 top_swap = mmio_readb(rcrb + 0x3414) & 1;
614 break;
615 }
616
Nico Huber93c30692017-03-20 14:25:09 +0100617 msg_pdbg("%s = 0x%x: ", reg_name, gcs);
618 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
Duncan Laurie4095ed72014-08-20 15:39:32 +0000619
Nico Huber2e50cdc2018-09-23 20:20:26 +0200620 struct boot_straps {
621 const char *name;
622 enum chipbustype bus;
623 };
624 static const struct boot_straps boot_straps_EP80579[] =
625 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200626 { "reserved", BUS_NONE },
627 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200628 { "LPC", BUS_LPC | BUS_FWH } };
629 static const struct boot_straps boot_straps_ich7_nm10[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200630 { { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200631 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200632 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200633 { "LPC", BUS_LPC | BUS_FWH } };
634 static const struct boot_straps boot_straps_tunnel_creek[] =
635 { { "SPI", BUS_SPI },
636 { "LPC", BUS_LPC | BUS_FWH } };
637 static const struct boot_straps boot_straps_ich8910[] =
638 { { "SPI", BUS_SPI },
639 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200640 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200641 { "LPC", BUS_LPC | BUS_FWH } };
642 static const struct boot_straps boot_straps_pch567[] =
643 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200644 { "reserved", BUS_NONE },
645 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200646 { "SPI", BUS_SPI } };
647 static const struct boot_straps boot_straps_pch89_baytrail[] =
648 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200649 { "reserved", BUS_NONE },
650 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200651 { "SPI", BUS_SPI } };
652 static const struct boot_straps boot_straps_pch8_lp[] =
653 { { "SPI", BUS_SPI },
654 { "LPC", BUS_LPC | BUS_FWH } };
Nico Huber37509862019-01-18 14:23:02 +0100655 static const struct boot_straps boot_straps_apl[] =
656 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200657 { "reserved", BUS_NONE } };
Nico Huber2e50cdc2018-09-23 20:20:26 +0200658 static const struct boot_straps boot_straps_unknown[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200659 { { "unknown", BUS_NONE },
660 { "unknown", BUS_NONE },
661 { "unknown", BUS_NONE },
662 { "unknown", BUS_NONE } };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000663
Nico Huber2e50cdc2018-09-23 20:20:26 +0200664 const struct boot_straps *boot_straps;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000665 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000666 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000667 /* EP80579 may need further changes, but this is the least
668 * intrusive way to get correct BOOT Strap printing without
669 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000670 if (dev->device_id == 0x5031)
Nico Huber2e50cdc2018-09-23 20:20:26 +0200671 boot_straps = boot_straps_EP80579;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000672 else
Nico Huber2e50cdc2018-09-23 20:20:26 +0200673 boot_straps = boot_straps_ich7_nm10;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000674 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000675 case CHIPSET_ICH8:
676 case CHIPSET_ICH9:
677 case CHIPSET_ICH10:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200678 boot_straps = boot_straps_ich8910;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000679 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000680 case CHIPSET_TUNNEL_CREEK:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200681 boot_straps = boot_straps_tunnel_creek;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000682 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000683 case CHIPSET_5_SERIES_IBEX_PEAK:
684 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000685 case CHIPSET_7_SERIES_PANTHER_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200686 boot_straps = boot_straps_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000687 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000688 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000689 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000690 case CHIPSET_BAYTRAIL:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200691 boot_straps = boot_straps_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000692 break;
693 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100694 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huber93c30692017-03-20 14:25:09 +0100695 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700696 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100697 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500698 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200699 boot_straps = boot_straps_pch8_lp;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000700 break;
Nico Huber37509862019-01-18 14:23:02 +0100701 case CHIPSET_APOLLO_LAKE:
702 boot_straps = boot_straps_apl;
703 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000704 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000705 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Nico Huber2e50cdc2018-09-23 20:20:26 +0200706 boot_straps = boot_straps_unknown;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000707 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000708 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000709 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Nico Huber2e50cdc2018-09-23 20:20:26 +0200710 boot_straps = boot_straps_unknown;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000711 break;
712 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000713
Duncan Laurie4095ed72014-08-20 15:39:32 +0000714 uint8_t bbs;
715 switch (ich_generation) {
716 case CHIPSET_TUNNEL_CREEK:
717 bbs = (gcs >> 1) & 0x1;
718 break;
719 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100720 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
721 /* LP PCHs use a single bit for BBS */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000722 bbs = (gcs >> 10) & 0x1;
723 break;
Nico Huber93c30692017-03-20 14:25:09 +0100724 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700725 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100726 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500727 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huber37509862019-01-18 14:23:02 +0100728 case CHIPSET_APOLLO_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100729 bbs = (gcs >> 6) & 0x1;
730 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000731 default:
732 /* Other chipsets use two bits for BBS */
733 bbs = (gcs >> 10) & 0x3;
734 break;
735 }
Nico Huber2e50cdc2018-09-23 20:20:26 +0200736 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, boot_straps[bbs].name);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000737
738 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
739 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
740 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
Nico Huber2e50cdc2018-09-23 20:20:26 +0200741
742 return boot_straps[bbs].bus;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000743}
744
745static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
746{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000747 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000748 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
749 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000750
751 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000752 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000753 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000754 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000755
Nico Huber2e50cdc2018-09-23 20:20:26 +0200756 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000757
Stefan Tauner92d6a862013-10-25 00:33:37 +0000758 /* Handle FWH-related parameters and initialization */
759 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
760 if (ret_fwh == ERROR_FATAL)
761 return ret_fwh;
762
Angel Ponsaa4aa162020-04-15 12:59:42 +0200763 /*
764 * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted
765 * from LPC, the SCIP bit will never clear, which causes long delays and many error messages.
766 * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC.
767 */
768 if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC))
769 return 0;
770
Stefan Tauner92d6a862013-10-25 00:33:37 +0000771 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
772 uint16_t spibar_offset;
773 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000774 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000775 case CHIPSET_ICH_UNKNOWN:
776 return ERROR_FATAL;
777 case CHIPSET_ICH7:
778 case CHIPSET_ICH8:
779 case CHIPSET_TUNNEL_CREEK:
780 case CHIPSET_CENTERTON:
781 spibar_offset = 0x3020;
782 break;
783 case CHIPSET_ICH9:
784 default: /* Future version might behave the same */
785 spibar_offset = 0x3800;
786 break;
787 }
788 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
789 void *spibar = rcrb + spibar_offset;
790
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000791 /* This adds BUS_SPI */
Nico Huber560111e2017-04-26 12:27:17 +0200792 int ret_spi = ich_init_spi(spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000793 if (ret_spi == ERROR_FATAL)
794 return ret_spi;
Elyes HAOUAS0cacb112019-02-04 12:16:38 +0100795
Nico Huber2e50cdc2018-09-23 20:20:26 +0200796 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Stefan Tauner92d6a862013-10-25 00:33:37 +0000797 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000798
Nico Huber2e50cdc2018-09-23 20:20:26 +0200799 /* Suppress unknown laptop warning if we booted from SPI. */
800 if (boot_buses & BUS_SPI)
801 laptop_ok = 1;
802
Stefan Tauner92d6a862013-10-25 00:33:37 +0000803 return 0;
804}
805
806static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
807{
808 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
809}
810
811static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
812{
813 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000814}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000815
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000816static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000817{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000818 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000819}
820
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000821static int enable_flash_ich8(struct pci_dev *dev, const char *name)
822{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000823 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000824}
825
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000826static int enable_flash_ich9(struct pci_dev *dev, const char *name)
827{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000828 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000829}
830
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000831static int enable_flash_ich10(struct pci_dev *dev, const char *name)
832{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000833 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000834}
835
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000836/* Ibex Peak aka. 5 series & 3400 series */
837static int enable_flash_pch5(struct pci_dev *dev, const char *name)
838{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000839 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000840}
841
842/* Cougar Point aka. 6 series & c200 series */
843static int enable_flash_pch6(struct pci_dev *dev, const char *name)
844{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000845 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000846}
847
Stefan Tauner2abab942012-04-27 20:41:23 +0000848/* Panther Point aka. 7 series */
849static int enable_flash_pch7(struct pci_dev *dev, const char *name)
850{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000851 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000852}
853
854/* Lynx Point aka. 8 series */
855static int enable_flash_pch8(struct pci_dev *dev, const char *name)
856{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000857 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000858}
859
Stefan Tauner92d6a862013-10-25 00:33:37 +0000860/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000861static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
862{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000863 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000864}
865
866/* Wellsburg (for Haswell-EP Xeons) */
867static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
868{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000869 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000870}
871
Duncan Laurie823096e2014-08-20 15:39:38 +0000872/* Wildcat Point */
873static int enable_flash_pch9(struct pci_dev *dev, const char *name)
874{
875 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
876}
877
Nico Huber51205912017-03-17 17:59:54 +0100878/* Wildcat Point LP */
879static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
880{
881 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
882}
883
Nico Huber93c30692017-03-20 14:25:09 +0100884/* Sunrise Point */
885static int enable_flash_pch100_shutdown(void *const pci_acc)
886{
887 pci_cleanup(pci_acc);
888 return 0;
889}
890
Nico Huber37509862019-01-18 14:23:02 +0100891static int enable_flash_pch100_or_c620(
892 struct pci_dev *const dev, const char *const name,
893 const int slot, const int func, const enum ich_chipset pch_generation)
Nico Huber93c30692017-03-20 14:25:09 +0100894{
Nico Huber93c30692017-03-20 14:25:09 +0100895 int ret = ERROR_FATAL;
896
897 /*
898 * The SPI PCI device is usually hidden (by hiding PCI vendor
899 * and device IDs). So we need a PCI access method that works
900 * even when the OS doesn't know the PCI device. We can't use
901 * this method globally since it would bring along other con-
902 * straints (e.g. on PCI domains, extended PCIe config space).
903 */
904 struct pci_access *const pci_acc = pci_alloc();
Youness Alaouia54ceb12017-07-26 18:03:36 -0400905 struct pci_access *const saved_pacc = pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100906 if (!pci_acc) {
907 msg_perr("Can't allocate PCI accessor.\n");
908 return ret;
909 }
910 pci_acc->method = PCI_ACCESS_I386_TYPE1;
911 pci_init(pci_acc);
912 register_shutdown(enable_flash_pch100_shutdown, pci_acc);
913
Nico Huber37509862019-01-18 14:23:02 +0100914 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
Nico Huber93c30692017-03-20 14:25:09 +0100915 if (!spi_dev) {
916 msg_perr("Can't allocate PCI device.\n");
917 return ret;
918 }
919
Youness Alaouia54ceb12017-07-26 18:03:36 -0400920 /* Modify pacc so the rpci_write can register the undo callback with a
921 * device using the correct pci_access */
922 pacc = pci_acc;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200923 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
Nico Huber93c30692017-03-20 14:25:09 +0100924
925 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
926 if (ret_bc == ERROR_FATAL)
927 goto _freepci_ret;
928
929 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
930 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
931 if (spibar == ERROR_PTR)
932 goto _freepci_ret;
933 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
934
935 /* This adds BUS_SPI */
936 const int ret_spi = ich_init_spi(spibar, pch_generation);
937 if (ret_spi != ERROR_FATAL) {
938 if (ret_bc || ret_spi)
939 ret = ERROR_NONFATAL;
940 else
941 ret = 0;
942 }
943
Nico Huber2e50cdc2018-09-23 20:20:26 +0200944 /* Suppress unknown laptop warning if we booted from SPI. */
945 if (!ret && (boot_buses & BUS_SPI))
946 laptop_ok = 1;
947
Nico Huber93c30692017-03-20 14:25:09 +0100948_freepci_ret:
949 pci_free_dev(spi_dev);
Youness Alaouia54ceb12017-07-26 18:03:36 -0400950 pacc = saved_pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100951 return ret;
952}
953
David Hendricksa5216362017-08-08 20:02:22 -0700954static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
955{
Nico Huber37509862019-01-18 14:23:02 +0100956 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
David Hendricksa5216362017-08-08 20:02:22 -0700957}
958
959static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
960{
Nico Huber37509862019-01-18 14:23:02 +0100961 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
962}
963
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100964static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
965{
966 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
967}
968
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500969static int enable_flash_pch400(struct pci_dev *const dev, const char *const name)
970{
971 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT);
972}
973
Nico Huber37509862019-01-18 14:23:02 +0100974static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
975{
976 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
David Hendricksa5216362017-08-08 20:02:22 -0700977}
978
Duncan Laurie4095ed72014-08-20 15:39:32 +0000979/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
980 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
981 *
982 * Differences include:
983 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
984 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
985 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
986 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
987 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
988 */
989static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
990{
991 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
992
993 /* Get physical address of Root Complex Register Block */
994 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
995 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
996
997 /* Handle GCS (in RCRB) */
998 void *rcrb = physmap("BYT RCRB", rcba, 4);
Edward O'Callaghan705212d2020-12-02 13:17:46 +1100999 if (rcrb == ERROR_PTR)
1000 return ERROR_FATAL;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001001 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001002 physunmap(rcrb, 4);
1003
1004 /* Handle fwh_idsel parameter */
1005 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
1006 if (ret_fwh == ERROR_FATAL)
1007 return ret_fwh;
1008
Nico Huber2e50cdc2018-09-23 20:20:26 +02001009 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001010
1011 /* Get physical address of SPI Base Address and map it */
1012 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
1013 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
1014 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
Edward O'Callaghanda0825f2020-10-15 19:19:05 +11001015 if (spibar == ERROR_PTR)
1016 return ERROR_FATAL;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001017
1018 /* Enable Flash Writes.
1019 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
1020 */
1021 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
1022
Nico Huber560111e2017-04-26 12:27:17 +02001023 int ret_spi = ich_init_spi(spibar, ich_generation);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001024 if (ret_spi == ERROR_FATAL)
1025 return ret_spi;
1026
Nico Huber2e50cdc2018-09-23 20:20:26 +02001027 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Duncan Laurie4095ed72014-08-20 15:39:32 +00001028 return ERROR_NONFATAL;
1029
Nico Huber2e50cdc2018-09-23 20:20:26 +02001030 /* Suppress unknown laptop warning if we booted from SPI. */
1031 if (boot_buses & BUS_SPI)
1032 laptop_ok = 1;
1033
Duncan Laurie4095ed72014-08-20 15:39:32 +00001034 return 0;
1035}
1036
Michael Karcher89bed6d2010-06-13 10:16:12 +00001037static int via_no_byte_merge(struct pci_dev *dev, const char *name)
1038{
1039 uint8_t val;
1040
1041 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001042 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +00001043 msg_pdbg("Disabling byte merging\n");
1044 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001045 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001046 }
1047 return NOT_DONE_YET; /* need to find south bridge, too */
1048}
1049
Uwe Hermann372eeb52007-12-04 21:49:06 +00001050static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001051{
Ollie Lho184a4042005-11-26 21:55:36 +00001052 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001053
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001054 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001055 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +00001056
Uwe Hermannffec5f32007-08-23 16:08:21 +00001057 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001058 val = pci_read_byte(dev, 0x40);
1059 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001060 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001061
1062 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001063 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001064 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001065 }
Luc Verhaegen6382b442007-03-02 22:16:38 +00001066
Helge Wagnerdd73d832012-08-24 23:03:46 +00001067 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001068 /* All memory cycles, not just ROM ones, go to LPC. */
1069 val = pci_read_byte(dev, 0x59);
1070 val &= ~0x80;
1071 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +00001072 }
1073
Uwe Hermanna7e05482007-05-09 10:17:44 +00001074 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001075}
1076
Helge Wagnerdd73d832012-08-24 23:03:46 +00001077static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
1078{
1079 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
1080 if (south_north == NULL) {
1081 msg_perr("Could not find South-North Module Interface Control device!\n");
1082 return ERROR_FATAL;
1083 }
1084
1085 msg_pdbg("Strapped to ");
1086 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
1087 msg_pdbg("LPC.\n");
1088 return enable_flash_vt823x(dev, name);
1089 }
1090 msg_pdbg("SPI.\n");
1091
1092 uint32_t mmio_base;
1093 void *mmio_base_physmapped;
1094 uint32_t spi_cntl;
1095 #define SPI_CNTL_LEN 0x08
1096 uint32_t spi0_mm_base = 0;
1097 switch(dev->device_id) {
1098 case 0x8353: /* VX800/VX820 */
1099 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001100 if (spi0_mm_base == 0x0) {
1101 msg_pdbg ("MMIO not enabled!\n");
1102 return ERROR_FATAL;
1103 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001104 break;
1105 case 0x8409: /* VX855/VX875 */
1106 case 0x8410: /* VX900 */
1107 mmio_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001108 if (mmio_base == 0x0) {
1109 msg_pdbg ("MMIO not enabled!\n");
1110 return ERROR_FATAL;
1111 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001112 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001113 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +00001114 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001115
1116 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
1117 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
1118 if ((spi_cntl & 0x01) == 0) {
1119 msg_pdbg ("SPI Bus0 disabled!\n");
1120 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1121 return ERROR_FATAL;
1122 }
1123 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
1124 spi0_mm_base = spi_cntl & 0xFFFFFF00;
1125
1126 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
1127 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
1128 if ((spi_cntl & 0x01) == 1)
1129 msg_pdbg2("SPI Bus1 is enabled too.\n");
1130
1131 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1132 break;
1133 default:
1134 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
1135 return ERROR_FATAL;
1136 }
1137
Nico Huber560111e2017-04-26 12:27:17 +02001138 return via_init_spi(spi0_mm_base);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001139}
1140
1141static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
1142{
Nico Huber560111e2017-04-26 12:27:17 +02001143 return via_init_spi(pci_read_long(dev, 0xbc) << 8);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001144}
1145
Uwe Hermann372eeb52007-12-04 21:49:06 +00001146static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001147{
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001148 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001149
Uwe Hermann394131e2008-10-18 21:14:13 +00001150#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
1151#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001152#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
1153#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001154
Uwe Hermann394131e2008-10-18 21:14:13 +00001155#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
1156#define ROM_WRITE_ENABLE (1 << 1)
1157#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
1158#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001159#define CS5530_ISA_MASTER (1 << 7)
1160#define CS5530_ENABLE_SA2320 (1 << 2)
1161#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001162
Nico Huber2e50cdc2018-09-23 20:20:26 +02001163 internal_buses_supported &= BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001164 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
1165 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001166 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
1167 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001168 * Make the configured ROM areas writable.
1169 */
1170 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
1171 reg8 |= LOWER_ROM_ADDRESS_RANGE;
1172 reg8 |= UPPER_ROM_ADDRESS_RANGE;
1173 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001174 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001175
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001176 /* Set positive decode on ROM. */
1177 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
1178 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001179 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001180
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001181 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
1182 if (reg8 & CS5530_ISA_MASTER) {
1183 /* We have A0-A23 available. */
1184 max_rom_decode.parallel = 16 * 1024 * 1024;
1185 } else {
1186 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
1187 if (reg8 & CS5530_ENABLE_SA2320) {
1188 /* We have A0-19, A20-A23 available. */
1189 max_rom_decode.parallel = 16 * 1024 * 1024;
1190 } else if (reg8 & CS5530_ENABLE_SA20) {
1191 /* We have A0-19, A20 available. */
1192 max_rom_decode.parallel = 2 * 1024 * 1024;
1193 } else {
1194 /* A20 and above are not active. */
1195 max_rom_decode.parallel = 1024 * 1024;
1196 }
1197 }
1198
Ollie Lhocbbf1252004-03-17 22:22:08 +00001199 return 0;
1200}
1201
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001202/*
Mart Raudseppe1344da2008-02-08 10:10:57 +00001203 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001204 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +00001205 *
1206 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
1207 * To enable write to NOR Boot flash for the benefit of systems that have such
1208 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001209 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001210static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001211{
Uwe Hermann394131e2008-10-18 21:14:13 +00001212#define MSR_RCONF_DEFAULT 0x1808
1213#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001214
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001215 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001216
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001217 /* Geode only has a single core */
1218 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001219 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001220
1221 msr = rdmsr(MSR_RCONF_DEFAULT);
1222 if ((msr.hi >> 24) != 0x22) {
1223 msr.hi &= 0xfbffffff;
1224 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001225 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001226
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001227 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001228 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001229 msr.lo |= 0x08;
1230 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001231
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001232 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001233
Uwe Hermann394131e2008-10-18 21:14:13 +00001234#undef MSR_RCONF_DEFAULT
1235#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001236 return 0;
1237}
1238
Uwe Hermann372eeb52007-12-04 21:49:06 +00001239static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001240{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001241 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001242 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001243
Stefan Taunere34e3e82013-01-01 00:06:51 +00001244 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001245
Stefan Taunere34e3e82013-01-01 00:06:51 +00001246 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001247
Stefan Taunere34e3e82013-01-01 00:06:51 +00001248 if (new != 0xee) { /* FIXME: share this with other code? */
1249 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001250 return -1;
1251 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001252
Ollie Lhocbbf1252004-03-17 22:22:08 +00001253 return 0;
1254}
1255
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001256/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1257 *
1258 * ROM decode control register matrix
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001259 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001260 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1261 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1262 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1263 */
1264static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001265{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001266 #define AMD_MAPREG 0x43
1267 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001268 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001269
Stefan Taunere34e3e82013-01-01 00:06:51 +00001270 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001271 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001272 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001273 rpci_write_byte(dev, AMD_MAPREG, new);
1274 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001275 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001276 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001277 } else
1278 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001279 }
1280
Uwe Hermann190f8492008-10-25 18:03:50 +00001281 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001282 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001283 new = old | 0x01;
1284 if (new == old)
1285 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001286 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001287
Stefan Taunere34e3e82013-01-01 00:06:51 +00001288 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001289 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001290 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001291 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001292 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001293 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001294
Ollie Lhocbbf1252004-03-17 22:22:08 +00001295 return 0;
1296}
1297
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001298static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1299{
1300 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1301 max_rom_decode.lpc = 5 * 1024 * 1024;
1302 return enable_flash_amd_via(dev, name, 0xC0);
1303}
1304
1305static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1306{
1307 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1308 max_rom_decode.parallel = 512 * 1024;
1309 return enable_flash_amd_via(dev, name, 0xC0);
1310}
1311
1312/* Works for VT82C686A/B too. */
1313static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1314{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001315 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001316 max_rom_decode.parallel = 1024 * 1024;
1317 return enable_flash_amd_via(dev, name, 0xE0);
1318}
1319
Marc Jones3af487d2008-10-15 17:50:29 +00001320static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1321{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001322 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001323 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001324 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001325
Jason Wanga3f04be2008-11-28 21:36:51 +00001326 /* Clear ROM protect 0-3. */
1327 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001328 prot = pci_read_long(dev, reg);
1329 /* No protection flags for this region?*/
1330 if ((prot & 0x3) == 0)
1331 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001332 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001333 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001334 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001335 (prot & 0xfffff800),
1336 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001337 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001338 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001339 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001340 if ((prot & 0x3) != 0) {
1341 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001342 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001343 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001344 (prot & 0xfffff800),
1345 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001346 continue;
1347 }
1348 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001349 }
1350
Nico Huber2e50cdc2018-09-23 20:20:26 +02001351 internal_buses_supported &= BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001352
1353 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001354
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001355 /* Read ROM strap override register. */
1356 OUTB(0x8f, 0xcd6);
1357 reg = INB(0xcd7);
1358 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001359 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001360 if (reg & 0x02) {
1361 switch ((reg & 0x0c) >> 2) {
1362 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001363 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001364 break;
1365 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001366 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001367 break;
1368 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001369 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001370 break;
1371 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001372 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001373 break;
1374 }
1375 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001376 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001377
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001378 /* Force enable SPI ROM in SB600 PM register.
1379 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001380 * But how can we know which ROM we are going to handle? So we have
1381 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001382 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1383 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001384 */
1385 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001386 OUTB(0x8f, 0xcd6);
1387 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001388 */
Marc Jones3af487d2008-10-15 17:50:29 +00001389
Michael Karcherb05b9e12010-07-22 18:04:19 +00001390 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001391}
1392
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001393/* sets bit 0 in 0x6d */
1394static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1395{
1396 uint8_t old, new;
1397
1398 old = pci_read_byte(dev, 0x6d);
1399 new = old | 0x01;
1400 if (new == old)
1401 return 0;
1402
1403 rpci_write_byte(dev, 0x6d, new);
1404 if (pci_read_byte(dev, 0x6d) != new) {
1405 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1406 return 1;
1407 }
1408 return 0;
1409}
1410
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001411static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1412{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001413 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001414 if (enable_flash_nvidia_common(dev, name))
1415 return ERROR_NONFATAL;
1416 else
1417 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001418}
1419
Uwe Hermann372eeb52007-12-04 21:49:06 +00001420static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001421{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001422 uint32_t segctrl;
1423 uint8_t reg, old, new;
1424 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001425
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001426 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1427 reg = 0x8A;
1428 segctrl = pci_read_byte(dev, reg);
1429 if ((segctrl & 0x3) != 0x0) {
1430 if ((segctrl & 0xC) != 0x0) {
1431 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1432 err++;
1433 } else {
1434 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1435 rpci_write_byte(dev, reg, segctrl & 0xF0);
1436
1437 segctrl = pci_read_byte(dev, reg);
1438 if ((segctrl & 0x3) != 0x0) {
1439 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1440 reg, segctrl);
1441 err++;
1442 } else
1443 msg_pdbg("OK\n");
1444 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001445 }
1446
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001447 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1448 segctrl = pci_read_long(dev, reg);
1449 if ((segctrl & 0x33333333) == 0x00000000) {
1450 /* reads and writes are unlocked */
1451 continue;
1452 }
1453 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1454 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1455 err++;
1456 continue;
1457 }
1458 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1459 rpci_write_long(dev, reg, 0x00000000);
1460
1461 segctrl = pci_read_long(dev, reg);
1462 if ((segctrl & 0x33333333) != 0x00000000) {
1463 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1464 reg, segctrl);
1465 err++;
1466 } else
1467 msg_pdbg("OK\n");
1468 }
1469
1470 if (err > 0) {
1471 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
1472 programmer_may_write = 0;
1473 }
1474
1475 reg = 0x88;
1476 old = pci_read_byte(dev, reg);
1477 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001478 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001479 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001480 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1481 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001482 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001483 }
1484 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001485
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001486 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001487 err++;
1488
1489 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001490 return ERROR_NONFATAL;
1491 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001492 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001493}
1494
Joshua Roys85835d82010-09-15 14:47:56 +00001495static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1496{
1497 uint8_t tmp;
1498
Nico Huber2e50cdc2018-09-23 20:20:26 +02001499 internal_buses_supported &= BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001500
1501 tmp = INB(0xc06);
1502 tmp |= 0x1;
1503 OUTB(tmp, 0xc06);
1504
1505 tmp = INB(0xc6f);
1506 tmp |= 0x40;
1507 OUTB(tmp, 0xc6f);
1508
1509 return 0;
1510}
1511
Uwe Hermann372eeb52007-12-04 21:49:06 +00001512/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1513static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001514{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001515 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001516 struct pci_dev *smbusdev;
1517
Uwe Hermann372eeb52007-12-04 21:49:06 +00001518 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001519 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001520
Uwe Hermanna7e05482007-05-09 10:17:44 +00001521 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001522 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001523 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001524 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001525
Uwe Hermann372eeb52007-12-04 21:49:06 +00001526 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001527 tmp = pci_read_byte(smbusdev, 0x79);
1528 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001529 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001530
Uwe Hermann372eeb52007-12-04 21:49:06 +00001531 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001532 tmp = pci_read_byte(dev, 0x48);
1533 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001534 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001535
Uwe Hermann372eeb52007-12-04 21:49:06 +00001536 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001537 tmp = INB(0xc6f);
1538 OUTB(tmp, 0xeb);
1539 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001540 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001541 OUTB(tmp, 0xc6f);
1542 OUTB(tmp, 0xeb);
1543 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001544
1545 return 0;
1546}
1547
Uwe Hermann372eeb52007-12-04 21:49:06 +00001548static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001549{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001550 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001551 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001552
Uwe Hermann372eeb52007-12-04 21:49:06 +00001553 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001554 val = pci_read_byte(dev, 0x88);
1555 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001556 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001557 val = pci_read_byte(dev, 0x8c);
1558 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001559 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001560 wordval = pci_read_word(dev, 0x90);
1561 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001562 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001563
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001564 if (enable_flash_nvidia_common(dev, name))
1565 return ERROR_NONFATAL;
1566 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001567 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001568}
1569
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001570/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001571 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1572 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1573 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001574 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001575static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001576{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001577 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001578 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001579
1580 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001581 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001582 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001583 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001584
Michael Karchercfa674f2010-02-25 11:38:23 +00001585 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001586 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001587 ret = enable_flash_mcp55(dev, name);
Nico Huber2e50cdc2018-09-23 20:20:26 +02001588 internal_buses_supported &= BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001589 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001590 break;
1591 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001592 want_spi = 1;
1593 /* SPI is added in mcp6x_spi_init if it works.
1594 * Do we really want to disable LPC in this case?
1595 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001596 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001597 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001598 break;
1599 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001600 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001601 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001602 msg_pwarn("Flash bus type is unknown (none)\n");
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001603 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n"
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001604 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1605 "help us finish support for your chipset. Thanks.\n");
1606 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001607 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001608
1609 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001610#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001611 val |= (1 << 6);
1612 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001613 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001614#endif
1615
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001616 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001617 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001618
Nico Huber2e50cdc2018-09-23 20:20:26 +02001619 /* Suppress unknown laptop warning if we booted from SPI. */
1620 if (!ret && want_spi)
1621 laptop_ok = 1;
1622
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001623 return ret;
1624}
1625
Uwe Hermann372eeb52007-12-04 21:49:06 +00001626static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001627{
Michael Karchercfa674f2010-02-25 11:38:23 +00001628 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001629
Uwe Hermanne823ee02007-06-05 15:02:18 +00001630 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001631 val = pci_read_byte(dev, 0x41);
1632 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001633 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001634
Michael Karchercfa674f2010-02-25 11:38:23 +00001635 val = pci_read_byte(dev, 0x43);
1636 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001637 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001638
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001639 return 0;
1640}
1641
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001642/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001643 * Usually on the x86 architectures (and on other PC-like platforms like some
1644 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1645 * Elan SC520 only a small piece of the system flash is mapped there, but the
1646 * complete flash is mapped somewhere below 1G. The position can be determined
1647 * by the BOOTCS PAR register.
1648 */
1649static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1650{
1651 int i, bootcs_found = 0;
1652 uint32_t parx = 0;
1653 void *mmcr;
1654
1655 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001656 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001657 if (mmcr == ERROR_PTR)
1658 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001659
1660 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1661 * BOOTCS region (PARx[31:29] = 100b)e
1662 */
1663 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001664 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001665 if ((parx >> 29) == 4) {
1666 bootcs_found = 1;
1667 break; /* BOOTCS found */
1668 }
1669 }
1670
1671 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1672 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1673 */
1674 if (bootcs_found) {
1675 if (parx & (1 << 25)) {
1676 parx &= (1 << 14) - 1; /* Mask [13:0] */
1677 flashbase = parx << 16;
1678 } else {
1679 parx &= (1 << 18) - 1; /* Mask [17:0] */
1680 flashbase = parx << 12;
1681 }
1682 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001683 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001684 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001685 }
1686
1687 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001688 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001689 return 0;
1690}
1691
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001692#endif
1693
Nico Huber2e50cdc2018-09-23 20:20:26 +02001694#define B_P (BUS_PARALLEL)
1695#define B_PFL (BUS_NONSPI)
1696#define B_PFLS (BUS_NONSPI | BUS_SPI)
1697#define B_FL (BUS_FWH | BUS_LPC)
1698#define B_FLS (BUS_FWH | BUS_LPC | BUS_SPI)
1699#define B_FS (BUS_FWH | BUS_SPI)
1700#define B_L (BUS_LPC)
1701#define B_LS (BUS_LPC | BUS_SPI)
1702#define B_S (BUS_SPI)
1703
Idwer Vollering326a0602011-06-18 18:45:41 +00001704/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001705const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001706#if defined(__i386__) || defined(__x86_64__)
Nico Huber2e50cdc2018-09-23 20:20:26 +02001707 {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400},
1708 {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600},
1709 {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1710 {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100},
1711 {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1712 {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1713 {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1714 {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1715 {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1716 {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600},
1717 {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600},
1718 {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1719 {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1720 {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530},
1721 {0x1039, 0x0540, B_PFL, NT, "SiS", "540", enable_flash_sis540},
1722 {0x1039, 0x0620, B_PFL, NT, "SiS", "620", enable_flash_sis530},
1723 {0x1039, 0x0630, B_PFL, OK, "SiS", "630", enable_flash_sis540},
1724 {0x1039, 0x0635, B_PFL, NT, "SiS", "635", enable_flash_sis540},
1725 {0x1039, 0x0640, B_PFL, NT, "SiS", "640", enable_flash_sis540},
1726 {0x1039, 0x0645, B_PFL, NT, "SiS", "645", enable_flash_sis540},
1727 {0x1039, 0x0646, B_PFL, OK, "SiS", "645DX", enable_flash_sis540},
1728 {0x1039, 0x0648, B_PFL, OK, "SiS", "648", enable_flash_sis540},
1729 {0x1039, 0x0650, B_PFL, OK, "SiS", "650", enable_flash_sis540},
1730 {0x1039, 0x0651, B_PFL, OK, "SiS", "651", enable_flash_sis540},
1731 {0x1039, 0x0655, B_PFL, NT, "SiS", "655", enable_flash_sis540},
1732 {0x1039, 0x0661, B_PFL, OK, "SiS", "661", enable_flash_sis540},
1733 {0x1039, 0x0730, B_PFL, OK, "SiS", "730", enable_flash_sis540},
1734 {0x1039, 0x0733, B_PFL, NT, "SiS", "733", enable_flash_sis540},
1735 {0x1039, 0x0735, B_PFL, OK, "SiS", "735", enable_flash_sis540},
1736 {0x1039, 0x0740, B_PFL, NT, "SiS", "740", enable_flash_sis540},
1737 {0x1039, 0x0741, B_PFL, OK, "SiS", "741", enable_flash_sis540},
1738 {0x1039, 0x0745, B_PFL, OK, "SiS", "745", enable_flash_sis540},
1739 {0x1039, 0x0746, B_PFL, NT, "SiS", "746", enable_flash_sis540},
1740 {0x1039, 0x0748, B_PFL, NT, "SiS", "748", enable_flash_sis540},
1741 {0x1039, 0x0755, B_PFL, OK, "SiS", "755", enable_flash_sis540},
1742 {0x1039, 0x5511, B_PFL, NT, "SiS", "5511", enable_flash_sis5511},
1743 {0x1039, 0x5571, B_PFL, NT, "SiS", "5571", enable_flash_sis530},
1744 {0x1039, 0x5591, B_PFL, NT, "SiS", "5591/5592", enable_flash_sis530},
1745 {0x1039, 0x5596, B_PFL, NT, "SiS", "5596", enable_flash_sis5511},
1746 {0x1039, 0x5597, B_PFL, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1747 {0x1039, 0x5600, B_PFL, NT, "SiS", "600", enable_flash_sis530},
1748 {0x1078, 0x0100, B_P, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1749 {0x10b9, 0x1533, B_PFL, OK, "ALi", "M1533", enable_flash_ali_m1533},
1750 {0x10de, 0x0030, B_PFL, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1751 {0x10de, 0x0050, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1752 {0x10de, 0x0051, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1753 {0x10de, 0x0060, B_PFL, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1754 {0x10de, 0x00e0, B_PFL, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001755 /* Slave, should not be here, to fix known bug for A01. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001756 {0x10de, 0x00d3, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804},
1757 {0x10de, 0x0260, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1758 {0x10de, 0x0261, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1759 {0x10de, 0x0262, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1760 {0x10de, 0x0263, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1761 {0x10de, 0x0360, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001762 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1763 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1764 * Until we have PCI device class matching or some fallback mechanism,
1765 * this is needed to get flashrom working on Tyan S2915 and maybe other
1766 * dual-MCP55 boards.
1767 */
1768#if 0
Nico Huber2e50cdc2018-09-23 20:20:26 +02001769 {0x10de, 0x0361, B_L, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001770#endif
Nico Huber2e50cdc2018-09-23 20:20:26 +02001771 {0x10de, 0x0362, B_L, OK, "NVIDIA", "MCP55"