blob: 3a9ca578089345ff469a745cd63dc87cdf3a961b [file] [log] [blame]
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000015 */
16
Stefan Taunerb0eee9b2015-01-10 09:32:50 +000017#include "platform.h"
Peter Lemenkov62829662012-12-29 19:26:55 +000018
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000019#include <stdint.h>
20#include <string.h>
21#include <stdlib.h>
Carl-Daniel Hailfinger11990da2013-07-13 23:21:05 +000022#include <errno.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000023#include <sys/types.h>
Patrick Georgia9095a92010-09-30 17:03:32 +000024#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__)
Carl-Daniel Hailfinger11990da2013-07-13 23:21:05 +000025/* No file access needed/possible to get hardware access permissions. */
Carl-Daniel Hailfinger831e8f42010-05-30 22:24:40 +000026#include <unistd.h>
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000027#include <fcntl.h>
Patrick Georgia9095a92010-09-30 17:03:32 +000028#endif
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000029#include "flash.h"
Jacob Garber6c683632019-06-21 15:33:09 -060030#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000031#include "hwaccess.h"
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000032
Stefan Tauner8e656542016-03-06 22:32:16 +000033#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun) || defined(__gnu_hurd__))
Stefan Taunerb0eee9b2015-01-10 09:32:50 +000034#error "Unknown operating system"
35#endif
36
Patrick Georgid2a03b32017-03-13 13:48:03 +010037#if IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__)
38#define USE_IOPL 1
39#else
40#define USE_IOPL 0
41#endif
42#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
43#define USE_DEV_IO 1
44#else
45#define USE_DEV_IO 0
46#endif
47#if defined(__gnu_hurd__)
48#define USE_IOPERM 1
49#else
50#define USE_IOPERM 0
51#endif
Stefan Tauner8e656542016-03-06 22:32:16 +000052
53#if USE_IOPERM
54#include <sys/io.h>
55#endif
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000056
57#if IS_X86 && USE_DEV_IO
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +000058int io_fd;
59#endif
60
Peter Lemenkov62829662012-12-29 19:26:55 +000061/* Prevent reordering and/or merging of reads/writes to hardware.
62 * Such reordering and/or merging would break device accesses which depend on the exact access order.
63 */
64static inline void sync_primitive(void)
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000065{
Stefan Taunerfb2d77c2015-02-10 08:03:10 +000066/* This is not needed for...
67 * - x86: uses uncached accesses which have a strongly ordered memory model.
68 * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model.
69 * - ARM: uses a strongly ordered memory model for device memories.
70 *
71 * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/memory-barriers.txt
Peter Lemenkov62829662012-12-29 19:26:55 +000072 */
Stefan Taunerb0eee9b2015-01-10 09:32:50 +000073#if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h
Peter Lemenkov62829662012-12-29 19:26:55 +000074 asm("eieio" : : : "memory");
Stefan Taunerfb2d77c2015-02-10 08:03:10 +000075#elif IS_SPARC
76#if defined(__sparc_v9__) || defined(__sparcv9)
77 /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like
78 * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we
79 * use the strongest hardware memory barriers that exist on Sparc V9. */
80 asm volatile ("membar #Sync" ::: "memory");
81#elif defined(__sparc_v8__) || defined(__sparcv8)
82 /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run
83 * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable
84 * operation in the V8 instruction set anyway. If you know better then please tell us. */
85 asm volatile ("stbar");
86#else
87 #error Unknown and/or unsupported SPARC instruction set version detected.
88#endif
Peter Lemenkov62829662012-12-29 19:26:55 +000089#endif
90}
91
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000092#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
Peter Lemenkov62829662012-12-29 19:26:55 +000093static int release_io_perms(void *p)
94{
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +000095#if defined (__sun)
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000096 sysi86(SI86V86, V86SC_IOPL, 0);
Stefan Tauner95b4b6d2013-07-13 20:55:33 +000097#elif USE_DEV_IO
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000098 close(io_fd);
Stefan Tauner8e656542016-03-06 22:32:16 +000099#elif USE_IOPERM
100 ioperm(0, 65536, 0);
Stefan Tauner95b4b6d2013-07-13 20:55:33 +0000101#elif USE_IOPL
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000102 iopl(0);
103#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000104 return 0;
105}
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +0000106#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000107
108/* Get I/O permissions with automatic permission release on shutdown. */
109int rget_io_perms(void)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000110{
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +0000111#if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__))
112#if defined (__sun)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000113 if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) {
Stefan Tauner95b4b6d2013-07-13 20:55:33 +0000114#elif USE_DEV_IO
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000115 if ((io_fd = open("/dev/io", O_RDWR)) < 0) {
Stefan Tauner8e656542016-03-06 22:32:16 +0000116#elif USE_IOPERM
117 if (ioperm(0, 65536, 1) != 0) {
Stefan Tauner95b4b6d2013-07-13 20:55:33 +0000118#elif USE_IOPL
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000119 if (iopl(3) != 0) {
120#endif
Stefan Tauner95b4b6d2013-07-13 20:55:33 +0000121 msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno));
122 msg_perr("You need to be root.\n");
Carl-Daniel Hailfingerb63b0672010-07-02 17:12:50 +0000123#if defined (__OpenBSD__)
Stefan Tauner95b4b6d2013-07-13 20:55:33 +0000124 msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and\n"
125 "reboot, or reboot into single user mode.\n");
126#elif defined(__NetBSD__)
127 msg_perr("If you are root already please reboot into single user mode or make sure\n"
128 "that your kernel configuration has the option INSECURE enabled.\n");
Carl-Daniel Hailfingerb63b0672010-07-02 17:12:50 +0000129#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000130 return 1;
131 } else {
132 register_shutdown(release_io_perms, NULL);
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000133 }
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000134#else
Carl-Daniel Hailfinger82258682013-01-08 22:49:12 +0000135 /* DJGPP and libpayload environments have full PCI port I/O permissions by default. */
136 /* PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000137#endif
Peter Lemenkov62829662012-12-29 19:26:55 +0000138 return 0;
139}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000140
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000141void mmio_writeb(uint8_t val, void *addr)
142{
143 *(volatile uint8_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000144 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000145}
146
147void mmio_writew(uint16_t val, void *addr)
148{
149 *(volatile uint16_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000150 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000151}
152
153void mmio_writel(uint32_t val, void *addr)
154{
155 *(volatile uint32_t *) addr = val;
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000156 sync_primitive();
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000157}
158
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100159uint8_t mmio_readb(const void *addr)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000160{
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100161 return *(volatile const uint8_t *) addr;
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000162}
163
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100164uint16_t mmio_readw(const void *addr)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000165{
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100166 return *(volatile const uint16_t *) addr;
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000167}
168
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100169uint32_t mmio_readl(const void *addr)
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000170{
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100171 return *(volatile const uint32_t *) addr;
Carl-Daniel Hailfingerfb0828f2010-02-12 19:35:25 +0000172}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000173
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100174void mmio_readn(const void *addr, uint8_t *buf, size_t len)
Carl-Daniel Hailfingerccd71c22012-03-01 22:38:27 +0000175{
176 memcpy(buf, addr, len);
177 return;
178}
179
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000180void mmio_le_writeb(uint8_t val, void *addr)
181{
182 mmio_writeb(cpu_to_le8(val), addr);
183}
184
185void mmio_le_writew(uint16_t val, void *addr)
186{
187 mmio_writew(cpu_to_le16(val), addr);
188}
189
190void mmio_le_writel(uint32_t val, void *addr)
191{
192 mmio_writel(cpu_to_le32(val), addr);
193}
194
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100195uint8_t mmio_le_readb(const void *addr)
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000196{
197 return le_to_cpu8(mmio_readb(addr));
198}
199
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100200uint16_t mmio_le_readw(const void *addr)
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000201{
202 return le_to_cpu16(mmio_readw(addr));
203}
204
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100205uint32_t mmio_le_readl(const void *addr)
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000206{
207 return le_to_cpu32(mmio_readl(addr));
208}
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000209
210enum mmio_write_type {
211 mmio_write_type_b,
212 mmio_write_type_w,
213 mmio_write_type_l,
214};
215
216struct undo_mmio_write_data {
217 void *addr;
218 int reg;
219 enum mmio_write_type type;
220 union {
221 uint8_t bdata;
222 uint16_t wdata;
223 uint32_t ldata;
224 };
225};
226
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600227static int undo_mmio_write(void *p)
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000228{
229 struct undo_mmio_write_data *data = p;
230 msg_pdbg("Restoring MMIO space at %p\n", data->addr);
231 switch (data->type) {
232 case mmio_write_type_b:
233 mmio_writeb(data->bdata, data->addr);
234 break;
235 case mmio_write_type_w:
236 mmio_writew(data->wdata, data->addr);
237 break;
238 case mmio_write_type_l:
239 mmio_writel(data->ldata, data->addr);
240 break;
241 }
242 /* p was allocated in register_undo_mmio_write. */
243 free(p);
David Hendricks8bb20212011-06-14 01:35:36 +0000244 return 0;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000245}
246
247#define register_undo_mmio_write(a, c) \
248{ \
249 struct undo_mmio_write_data *undo_mmio_write_data; \
Angel Pons3bd47522021-06-07 12:33:53 +0200250 undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \
Stefan Tauner269de352011-07-12 22:35:21 +0000251 if (!undo_mmio_write_data) { \
252 msg_gerr("Out of memory!\n"); \
253 exit(1); \
254 } \
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000255 undo_mmio_write_data->addr = a; \
256 undo_mmio_write_data->type = mmio_write_type_##c; \
257 undo_mmio_write_data->c##data = mmio_read##c(a); \
258 register_shutdown(undo_mmio_write, undo_mmio_write_data); \
259}
260
261#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b)
262#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w)
263#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l)
264
265void rmmio_writeb(uint8_t val, void *addr)
266{
267 register_undo_mmio_writeb(addr);
268 mmio_writeb(val, addr);
269}
270
271void rmmio_writew(uint16_t val, void *addr)
272{
273 register_undo_mmio_writew(addr);
274 mmio_writew(val, addr);
275}
276
277void rmmio_writel(uint32_t val, void *addr)
278{
279 register_undo_mmio_writel(addr);
280 mmio_writel(val, addr);
281}
282
283void rmmio_le_writeb(uint8_t val, void *addr)
284{
285 register_undo_mmio_writeb(addr);
286 mmio_le_writeb(val, addr);
287}
288
289void rmmio_le_writew(uint16_t val, void *addr)
290{
291 register_undo_mmio_writew(addr);
292 mmio_le_writew(val, addr);
293}
294
295void rmmio_le_writel(uint32_t val, void *addr)
296{
297 register_undo_mmio_writel(addr);
298 mmio_le_writel(val, addr);
299}
300
301void rmmio_valb(void *addr)
302{
303 register_undo_mmio_writeb(addr);
304}
305
306void rmmio_valw(void *addr)
307{
308 register_undo_mmio_writew(addr);
309}
310
311void rmmio_vall(void *addr)
312{
313 register_undo_mmio_writel(addr);
314}