blob: 2f4fd1011ee6554aa82eab71b92dfca87128601e [file] [log] [blame]
Idwer Vollering004f4b72010-09-03 18:21:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Carl-Daniel Hailfinger
5 * Copyright (C) 2010 Idwer Vollering
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Idwer Vollering004f4b72010-09-03 18:21:21 +000015 */
16
17/*
Bill Paulbf8ea492014-03-17 22:07:29 +000018 * Datasheets:
Idwer Vollering004f4b72010-09-03 18:21:21 +000019 * PCI/PCI-X Family of Gigabit Ethernet Controllers Software Developer's Manual
20 * 82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and 82547xx
Bill Paulbf8ea492014-03-17 22:07:29 +000021 * http://www.intel.com/content/www/us/en/ethernet-controllers/pci-pci-x-family-gbe-controllers-software-dev-manual.html
22 *
23 * PCIe GbE Controllers Open Source Software Developer's Manual
24 * http://www.intel.com/content/www/us/en/ethernet-controllers/pcie-gbe-controllers-open-source-manual.html
25 *
26 * Intel 82574 Gigabit Ethernet Controller Family Datasheet
27 * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-controller-datasheet.html
Ed Swierk33180df2014-12-05 22:56:13 +000028 *
29 * Intel 82599 10 GbE Controller Datasheet (331520)
30 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf
Idwer Vollering004f4b72010-09-03 18:21:21 +000031 */
32
33#include <stdlib.h>
Stefan Tauner6745d6f2012-08-26 21:50:36 +000034#include <unistd.h>
Idwer Vollering004f4b72010-09-03 18:21:21 +000035#include "flash.h"
36#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000037#include "hwaccess.h"
Idwer Vollering004f4b72010-09-03 18:21:21 +000038
39#define PCI_VENDOR_ID_INTEL 0x8086
Stefan Tauner6745d6f2012-08-26 21:50:36 +000040#define MEMMAP_SIZE getpagesize()
Idwer Vollering004f4b72010-09-03 18:21:21 +000041
Stefan Tauner8ee180d2012-02-27 19:44:16 +000042/* EEPROM/Flash Control & Data Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000043#define EECD 0x10
Stefan Tauner8ee180d2012-02-27 19:44:16 +000044/* Flash Access Register */
Idwer Vollering004f4b72010-09-03 18:21:21 +000045#define FLA 0x1c
46
47/*
48 * Register bits of EECD.
Stefan Tauner8ee180d2012-02-27 19:44:16 +000049 * Table 13-6
50 *
Idwer Vollering004f4b72010-09-03 18:21:21 +000051 * Bit 04, 05: FWE (Flash Write Enable Control)
Ed Swierk33180df2014-12-05 22:56:13 +000052 * 00b = not allowed (on some cards this sends an erase command if bit 31 (FL_ER) of FLA is set)
Idwer Vollering004f4b72010-09-03 18:21:21 +000053 * 01b = flash writes disabled
54 * 10b = flash writes enabled
55 * 11b = not allowed
56 */
57#define FLASH_WRITES_DISABLED 0x10 /* FWE: 10000b */
58#define FLASH_WRITES_ENABLED 0x20 /* FWE: 100000b */
59
Stefan Tauner8ee180d2012-02-27 19:44:16 +000060/* Flash Access register bits
61 * Table 13-9
62 */
Idwer Vollering004f4b72010-09-03 18:21:21 +000063#define FL_SCK 0
64#define FL_CS 1
65#define FL_SI 2
66#define FL_SO 3
67#define FL_REQ 4
68#define FL_GNT 5
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +010069#define FL_LOCKED 6
70#define FL_ABORT 7
71#define FL_CLR_ERR 8
Idwer Vollering004f4b72010-09-03 18:21:21 +000072/* Currently unused */
73// #define FL_BUSY 30
74// #define FL_ER 31
75
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +010076#define BIT(x) (1<<(x))
77
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +100078struct nicintel_spi_data {
79 uint8_t *spibar;
80};
Idwer Vollering004f4b72010-09-03 18:21:21 +000081
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020082static const struct dev_entry nics_intel_spi[] = {
Idwer Volleringbdc48272010-10-05 11:16:14 +000083 {PCI_VENDOR_ID_INTEL, 0x105e, OK, "Intel", "82571EB Gigabit Ethernet Controller"},
Stefan Tauner4b90e6b2011-05-18 01:31:24 +000084 {PCI_VENDOR_ID_INTEL, 0x1076, OK, "Intel", "82541GI Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000085 {PCI_VENDOR_ID_INTEL, 0x107c, OK, "Intel", "82541PI Gigabit Ethernet Controller"},
Idwer Volleringbdc48272010-10-05 11:16:14 +000086 {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"},
Bill Paulbf8ea492014-03-17 22:07:29 +000087 {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"},
Idwer Vollering004f4b72010-09-03 18:21:21 +000088
Ed Swierk33180df2014-12-05 22:56:13 +000089 {PCI_VENDOR_ID_INTEL, 0x10d8, NT, "Intel", "82599 10 Gigabit Unprogrammed Network Controller"},
90 {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "82599 10 Gigabit KX4 Dual Port Network Controller"},
91 {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller"},
92 {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit CX4 Dual Port Network Controller"},
93 {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599 10-Gigabit SFI/SFP+ Network Controller"},
94 {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit XAUI/BX4 Dual Port Network Controller"},
95 {PCI_VENDOR_ID_INTEL, 0x1517, NT, "Intel", "82599 10 Gigabit KR Network Controller"},
96 {PCI_VENDOR_ID_INTEL, 0x151c, NT, "Intel", "82599 10 Gigabit TN Network Controller"},
97 {PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"},
98 {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"},
99 {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"},
100
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100101 {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"},
102 {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"},
103 {PCI_VENDOR_ID_INTEL, 0x1533, NT, "Intel", "I210 Gigabit Network Connection"},
104 {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"},
105 {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"},
106 {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"},
107 {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"},
108
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000109 {0},
Idwer Vollering004f4b72010-09-03 18:21:21 +0000110};
111
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000112static void nicintel_request_spibus(void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000113{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000114 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000115 uint32_t tmp;
116
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000117 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100118 tmp |= BIT(FL_REQ);
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000119 pci_mmio_writel(tmp, data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000120
121 /* Wait until we are allowed to use the SPI bus. */
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000122 while (!(pci_mmio_readl(data->spibar + FLA) & BIT(FL_GNT))) ;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000123}
124
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000125static void nicintel_release_spibus(void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000126{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000127 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000128 uint32_t tmp;
129
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000130 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100131 tmp &= ~BIT(FL_REQ);
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000132 pci_mmio_writel(tmp, data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000133}
134
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000135static void nicintel_bitbang_set_cs(int val, void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000136{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000137 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000138 uint32_t tmp;
139
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000140 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100141 tmp &= ~BIT(FL_CS);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000142 tmp |= (val << FL_CS);
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000143 pci_mmio_writel(tmp, data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000144}
145
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000146static void nicintel_bitbang_set_sck(int val, void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000147{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000148 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000149 uint32_t tmp;
150
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000151 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100152 tmp &= ~BIT(FL_SCK);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000153 tmp |= (val << FL_SCK);
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000154 pci_mmio_writel(tmp, data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000155}
156
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000157static void nicintel_bitbang_set_mosi(int val, void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000158{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000159 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000160 uint32_t tmp;
161
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000162 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100163 tmp &= ~BIT(FL_SI);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000164 tmp |= (val << FL_SI);
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000165 pci_mmio_writel(tmp, data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000166}
167
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000168static int nicintel_bitbang_get_miso(void *spi_data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000169{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000170 struct nicintel_spi_data *data = spi_data;
Idwer Vollering004f4b72010-09-03 18:21:21 +0000171 uint32_t tmp;
172
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000173 tmp = pci_mmio_readl(data->spibar + FLA);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000174 tmp = (tmp >> FL_SO) & 0x1;
175 return tmp;
176}
177
178static const struct bitbang_spi_master bitbang_spi_master_nicintel = {
Idwer Vollering004f4b72010-09-03 18:21:21 +0000179 .set_cs = nicintel_bitbang_set_cs,
180 .set_sck = nicintel_bitbang_set_sck,
181 .set_mosi = nicintel_bitbang_set_mosi,
182 .get_miso = nicintel_bitbang_get_miso,
Carl-Daniel Hailfinger28228882010-09-15 00:17:37 +0000183 .request_bus = nicintel_request_spibus,
184 .release_bus = nicintel_release_spibus,
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000185 .half_period = 1,
Idwer Vollering004f4b72010-09-03 18:21:21 +0000186};
187
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000188static int nicintel_spi_shutdown(void *spi_data)
David Hendricks8bb20212011-06-14 01:35:36 +0000189{
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000190 struct nicintel_spi_data *data = spi_data;
David Hendricks8bb20212011-06-14 01:35:36 +0000191 uint32_t tmp;
192
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000193 /* Disable writes manually. See the comment about EECD in nicintel_spi_init() for details. */
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000194 tmp = pci_mmio_readl(data->spibar + EECD);
David Hendricks8bb20212011-06-14 01:35:36 +0000195 tmp &= ~FLASH_WRITES_ENABLED;
196 tmp |= FLASH_WRITES_DISABLED;
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000197 pci_mmio_writel(tmp, data->spibar + EECD);
David Hendricks8bb20212011-06-14 01:35:36 +0000198
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000199 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000200 return 0;
201}
202
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000203static int nicintel_spi_82599_enable_flash(struct nicintel_spi_data *data)
Idwer Vollering004f4b72010-09-03 18:21:21 +0000204{
205 uint32_t tmp;
206
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000207 /* Automatic restore of EECD on shutdown is not possible because EECD
208 * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED,
209 * but other bits with side effects as well. Those other bits must be
210 * left untouched.
211 */
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000212 tmp = pci_mmio_readl(data->spibar + EECD);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000213 tmp &= ~FLASH_WRITES_DISABLED;
214 tmp |= FLASH_WRITES_ENABLED;
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000215 pci_mmio_writel(tmp, data->spibar + EECD);
Idwer Vollering004f4b72010-09-03 18:21:21 +0000216
Stefan Tauner8ee180d2012-02-27 19:44:16 +0000217 /* test if FWE is really set to allow writes */
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000218 tmp = pci_mmio_readl(data->spibar + EECD);
Stefan Tauner8ee180d2012-02-27 19:44:16 +0000219 if ( (tmp & FLASH_WRITES_DISABLED) || !(tmp & FLASH_WRITES_ENABLED) ) {
220 msg_perr("Enabling flash write access failed.\n");
221 return 1;
222 }
223
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000224 if (register_shutdown(nicintel_spi_shutdown, data))
David Hendricks8bb20212011-06-14 01:35:36 +0000225 return 1;
226
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100227 return 0;
228}
229
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000230static int nicintel_spi_i210_shutdown(void *data)
231{
232 free(data);
233 return 0;
234}
235
236static int nicintel_spi_i210_enable_flash(struct nicintel_spi_data *data)
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100237{
238 uint32_t tmp;
239
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000240 tmp = pci_mmio_readl(data->spibar + FLA);
Ricardo Ribalda Delgado75a2a792017-03-23 23:38:04 +0100241 if (tmp & BIT(FL_LOCKED)) {
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100242 msg_perr("Flash is in Secure Mode. Abort.\n");
243 return 1;
244 }
245
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000246 if (tmp & BIT(FL_ABORT)) {
247 tmp |= BIT(FL_CLR_ERR);
248 pci_mmio_writel(tmp, data->spibar + FLA);
249 tmp = pci_mmio_readl(data->spibar + FLA);
250 if (!(tmp & BIT(FL_ABORT))) {
251 msg_perr("Unable to clear Flash Access Error. Abort\n");
252 return 1;
253 }
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100254 }
255
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000256 if (register_shutdown(nicintel_spi_i210_shutdown, data))
257 return 1;
258
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100259 return 0;
260}
261
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200262static int nicintel_spi_init(void)
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100263{
264 struct pci_dev *dev = NULL;
265
266 if (rget_io_perms())
267 return 1;
268
269 dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0);
270 if (!dev)
271 return 1;
272
273 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
274 if (!io_base_addr)
275 return 1;
276
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000277 struct nicintel_spi_data *data = calloc(1, sizeof(*data));
278 if (!data) {
279 msg_perr("Unable to allocate space for SPI master data\n");
280 return 1;
Ricardo Ribalda Delgado26d33d22017-03-22 14:30:52 +0100281 }
282
Anastasia Klimchuk0d149d92021-05-27 08:23:24 +1000283 if ((dev->device_id & 0xfff0) == 0x1530) {
284 data->spibar = rphysmap("Intel I210 Gigabit w/ SPI flash", io_base_addr + 0x12000,
285 MEMMAP_SIZE);
286 if (!data->spibar || nicintel_spi_i210_enable_flash(data)) {
287 free(data);
288 return 1;
289 }
290 } else if (dev->device_id < 0x10d8) {
291 data->spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr,
292 MEMMAP_SIZE);
293 if (!data->spibar || nicintel_spi_82599_enable_flash(data)) {
294 free(data);
295 return 1;
296 }
297 } else {
298 data->spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000,
299 MEMMAP_SIZE);
300 if (!data->spibar || nicintel_spi_82599_enable_flash(data)) {
301 free(data);
302 return 1;
303 }
304 }
305
306 if (register_spi_bitbang_master(&bitbang_spi_master_nicintel, data))
307 return 1; /* shutdown function does cleanup */
Idwer Vollering004f4b72010-09-03 18:21:21 +0000308
Idwer Vollering004f4b72010-09-03 18:21:21 +0000309 return 0;
310}
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200311
312const struct programmer_entry programmer_nicintel_spi = {
313 .name = "nicintel_spi",
314 .type = PCI,
315 .devs.dev = nics_intel_spi,
316 .init = nicintel_spi_init,
317 .map_flash_region = fallback_map,
318 .unmap_flash_region = fallback_unmap,
319 .delay = internal_delay,
320};