blob: 213273f2153490e19b6449cc881da32806fae366 [file] [log] [blame]
Sean Nelson14ba6682010-02-26 05:48:29 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00004 * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger
Sean Nelson14ba6682010-02-26 05:48:29 +00005 * Copyright (C) 2008 coresystems GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Sean Nelson14ba6682010-02-26 05:48:29 +000015 */
16
17/*
18 * Contains the common SPI chip driver functions
19 */
20
Nico Hubera3140d02017-10-15 11:20:58 +020021#include <stddef.h>
Sean Nelson14ba6682010-02-26 05:48:29 +000022#include <string.h>
Nico Hubera1672f82017-10-14 18:00:20 +020023#include <stdbool.h>
Sean Nelson14ba6682010-02-26 05:48:29 +000024#include "flash.h"
25#include "flashchips.h"
26#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000028#include "spi.h"
29
Edward O'Callaghan3b129452020-05-14 15:19:42 +100030enum id_type {
31 RDID,
32 RDID4,
33 REMS,
34 RES2,
35 RES3,
36 NUM_ID_TYPES,
37};
38
39static struct {
40 int is_cached;
41 unsigned char bytes[4]; /* enough to hold largest ID type */
42} id_cache[NUM_ID_TYPES];
43
44void clear_spi_id_cache(void)
45{
46 memset(id_cache, 0, sizeof(id_cache));
47 return;
48}
49
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000050static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000051{
Mathias Krausea60faab2011-01-17 07:50:42 +000052 static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
Sean Nelson14ba6682010-02-26 05:48:29 +000053 int ret;
54 int i;
55
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000056 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000057 if (ret)
58 return ret;
Sean Nelsoned479d22010-03-24 23:14:32 +000059 msg_cspew("RDID returned");
Sean Nelson14ba6682010-02-26 05:48:29 +000060 for (i = 0; i < bytes; i++)
Sean Nelsoned479d22010-03-24 23:14:32 +000061 msg_cspew(" 0x%02x", readarr[i]);
62 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000063 return 0;
64}
65
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000066static int spi_rems(struct flashctx *flash, unsigned char *readarr)
Sean Nelson14ba6682010-02-26 05:48:29 +000067{
Nico Hubered098d62017-04-21 23:47:08 +020068 static const unsigned char cmd[JEDEC_REMS_OUTSIZE] = { JEDEC_REMS, };
Sean Nelson14ba6682010-02-26 05:48:29 +000069 int ret;
70
Nico Hubered098d62017-04-21 23:47:08 +020071 ret = spi_send_command(flash, sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000072 if (ret)
73 return ret;
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +000074 msg_cspew("REMS returned 0x%02x 0x%02x. ", readarr[0], readarr[1]);
Sean Nelson14ba6682010-02-26 05:48:29 +000075 return 0;
76}
77
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000078static int spi_res(struct flashctx *flash, unsigned char *readarr, int bytes)
Sean Nelson14ba6682010-02-26 05:48:29 +000079{
Nico Hubered098d62017-04-21 23:47:08 +020080 static const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, };
Sean Nelson14ba6682010-02-26 05:48:29 +000081 int ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000082 int i;
Sean Nelson14ba6682010-02-26 05:48:29 +000083
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000084 ret = spi_send_command(flash, sizeof(cmd), bytes, cmd, readarr);
Sean Nelson14ba6682010-02-26 05:48:29 +000085 if (ret)
86 return ret;
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +000087 msg_cspew("RES returned");
88 for (i = 0; i < bytes; i++)
89 msg_cspew(" 0x%02x", readarr[i]);
90 msg_cspew(". ");
Sean Nelson14ba6682010-02-26 05:48:29 +000091 return 0;
92}
93
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000094int spi_write_enable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +000095{
Mathias Krausea60faab2011-01-17 07:50:42 +000096 static const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
Sean Nelson14ba6682010-02-26 05:48:29 +000097 int result;
98
99 /* Send WREN (Write Enable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000100 result = spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000101
102 if (result)
Sean Nelsoned479d22010-03-24 23:14:32 +0000103 msg_cerr("%s failed\n", __func__);
Sean Nelson14ba6682010-02-26 05:48:29 +0000104
105 return result;
106}
107
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000108int spi_write_disable(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000109{
Mathias Krausea60faab2011-01-17 07:50:42 +0000110 static const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
Sean Nelson14ba6682010-02-26 05:48:29 +0000111
112 /* Send WRDI (Write Disable) */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000113 return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL);
Sean Nelson14ba6682010-02-26 05:48:29 +0000114}
115
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000116static void rdid_get_ids(unsigned char *readarr, int bytes,
117 uint32_t *id1, uint32_t *id2)
Sean Nelson14ba6682010-02-26 05:48:29 +0000118{
Sean Nelson14ba6682010-02-26 05:48:29 +0000119 if (!oddparity(readarr[0]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000120 msg_cdbg("RDID byte 0 parity violation. ");
Sean Nelson14ba6682010-02-26 05:48:29 +0000121
Carl-Daniel Hailfinger8ae500e2010-06-20 10:39:33 +0000122 /* Check if this is a continuation vendor ID.
123 * FIXME: Handle continuation device IDs.
124 */
Sean Nelson14ba6682010-02-26 05:48:29 +0000125 if (readarr[0] == 0x7f) {
126 if (!oddparity(readarr[1]))
Sean Nelsoned479d22010-03-24 23:14:32 +0000127 msg_cdbg("RDID byte 1 parity violation. ");
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000128 *id1 = (readarr[0] << 8) | readarr[1];
129 *id2 = readarr[2];
Sean Nelson14ba6682010-02-26 05:48:29 +0000130 if (bytes > 3) {
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000131 *id2 <<= 8;
132 *id2 |= readarr[3];
Sean Nelson14ba6682010-02-26 05:48:29 +0000133 }
134 } else {
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000135 *id1 = readarr[0];
136 *id2 = (readarr[1] << 8) | readarr[2];
Sean Nelson14ba6682010-02-26 05:48:29 +0000137 }
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000138}
Sean Nelson14ba6682010-02-26 05:48:29 +0000139
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000140static int compare_id(const struct flashctx *flash, uint32_t id1, uint32_t id2)
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000141{
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000142 const struct flashchip *chip = flash->chip;
Sean Nelson14ba6682010-02-26 05:48:29 +0000143
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000144 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
Stefan Tauner6ee37e22012-12-29 15:03:51 +0000145 if (id1 == chip->manufacture_id && id2 == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000146 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000147
148 /* Test if this is a pure vendor match. */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000149 if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000150 return 1;
151
152 /* Test if there is any vendor ID. */
Urja Rannikko0a5f6e42015-06-22 23:59:15 +0000153 if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00)
Sean Nelson14ba6682010-02-26 05:48:29 +0000154 return 1;
155
156 return 0;
157}
158
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000159static int probe_spi_rdid_generic(struct flashctx *flash, int bytes)
160{
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000161 uint32_t id1, id2;
162 enum id_type idty = bytes == 3 ? RDID : RDID4;
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000163
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000164 if (!id_cache[idty].is_cached) {
165 const int ret = spi_rdid(flash, id_cache[idty].bytes, bytes);
166 if (ret == SPI_INVALID_LENGTH)
167 msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes);
168 if (ret)
169 return 0;
170 id_cache[idty].is_cached = 1;
171 }
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000172
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000173 rdid_get_ids(id_cache[idty].bytes, bytes, &id1, &id2);
174 return compare_id(flash, id1, id2);
Edward O'Callaghana2dc4f72020-05-14 15:13:22 +1000175}
176
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000177int probe_spi_rdid(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000178{
179 return probe_spi_rdid_generic(flash, 3);
180}
181
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000182int probe_spi_rdid4(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000183{
Nico Huber959aafa2017-04-22 00:13:15 +0200184 return probe_spi_rdid_generic(flash, 4);
Sean Nelson14ba6682010-02-26 05:48:29 +0000185}
186
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000187int probe_spi_rems(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000188{
Sean Nelson14ba6682010-02-26 05:48:29 +0000189 uint32_t id1, id2;
190
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000191 if (!id_cache[REMS].is_cached) {
192 if (spi_rems(flash, id_cache[REMS].bytes))
193 return 0;
194 id_cache[REMS].is_cached = 1;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000195 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000196
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000197 id1 = id_cache[REMS].bytes[0];
198 id2 = id_cache[REMS].bytes[1];
199 return compare_id(flash, id1, id2);
Sean Nelson14ba6682010-02-26 05:48:29 +0000200}
201
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000202int probe_spi_res1(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000203{
Mathias Krausea60faab2011-01-17 07:50:42 +0000204 static const unsigned char allff[] = {0xff, 0xff, 0xff};
205 static const unsigned char all00[] = {0x00, 0x00, 0x00};
Sean Nelson14ba6682010-02-26 05:48:29 +0000206 unsigned char readarr[3];
207 uint32_t id2;
Sean Nelson14ba6682010-02-26 05:48:29 +0000208
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000209 /* We only want one-byte RES if RDID and REMS are unusable. */
210
Sean Nelson14ba6682010-02-26 05:48:29 +0000211 /* Check if RDID is usable and does not return 0xff 0xff 0xff or
212 * 0x00 0x00 0x00. In that case, RES is pointless.
213 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000214 if (!spi_rdid(flash, readarr, 3) && memcmp(readarr, allff, 3) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000215 memcmp(readarr, all00, 3)) {
216 msg_cdbg("Ignoring RES in favour of RDID.\n");
217 return 0;
218 }
219 /* Check if REMS is usable and does not return 0xff 0xff or
220 * 0x00 0x00. In that case, RES is pointless.
221 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000222 if (!spi_rems(flash, readarr) &&
223 memcmp(readarr, allff, JEDEC_REMS_INSIZE) &&
Sean Nelson14ba6682010-02-26 05:48:29 +0000224 memcmp(readarr, all00, JEDEC_REMS_INSIZE)) {
225 msg_cdbg("Ignoring RES in favour of REMS.\n");
226 return 0;
227 }
228
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000229 if (spi_res(flash, readarr, 1)) {
Sean Nelson14ba6682010-02-26 05:48:29 +0000230 return 0;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000231 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000232
Sean Nelson14ba6682010-02-26 05:48:29 +0000233 id2 = readarr[0];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000234
Sean Nelsoned479d22010-03-24 23:14:32 +0000235 msg_cdbg("%s: id 0x%x\n", __func__, id2);
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000236
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000237 if (id2 != flash->chip->model_id)
Sean Nelson14ba6682010-02-26 05:48:29 +0000238 return 0;
239
Sean Nelson14ba6682010-02-26 05:48:29 +0000240 return 1;
241}
242
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000243int probe_spi_res2(struct flashctx *flash)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000244{
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000245 uint32_t id1, id2;
246
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000247 if (!id_cache[RES2].is_cached) {
248 if (spi_res(flash, id_cache[RES2].bytes, 2))
249 return 0;
250 id_cache[RES2].is_cached = 1;
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000251 }
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000252
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000253 id1 = id_cache[RES2].bytes[0];
254 id2 = id_cache[RES2].bytes[1];
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000255 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
256
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000257 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000258 return 0;
259
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +0000260 return 1;
261}
262
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000263int probe_spi_res3(struct flashctx *flash)
264{
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000265 uint32_t id1, id2;
266
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000267 if (!id_cache[RES3].is_cached) {
268 if (spi_res(flash, id_cache[RES3].bytes, 3))
269 return 0;
270 id_cache[RES3].is_cached = 1;
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000271 }
272
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000273 id1 = (id_cache[RES3].bytes[0] << 8) | id_cache[RES3].bytes[1];
274 id2 = id_cache[RES3].bytes[3];
Stefan Tauner3f5e35d2013-04-19 01:58:33 +0000275 msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2);
276
277 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
278 return 0;
279
280 return 1;
281}
282
Stefan Tauner57794ac2012-12-29 15:04:20 +0000283/* Only used for some Atmel chips. */
284int probe_spi_at25f(struct flashctx *flash)
285{
286 static const unsigned char cmd[AT25F_RDID_OUTSIZE] = { AT25F_RDID };
287 unsigned char readarr[AT25F_RDID_INSIZE];
288 uint32_t id1;
289 uint32_t id2;
290
291 if (spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr))
292 return 0;
293
294 id1 = readarr[0];
295 id2 = readarr[1];
296
297 msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2);
298
299 if (id1 == flash->chip->manufacture_id && id2 == flash->chip->model_id)
300 return 1;
301
302 return 0;
303}
304
Nico Huber9dc3d8d2020-04-27 22:51:49 +0000305static int spi_poll_wip(struct flashctx *const flash, const unsigned int poll_delay)
Nico Huber0ecbacb2017-10-14 16:50:43 +0200306{
Nico Huber9dc3d8d2020-04-27 22:51:49 +0000307 /* FIXME: We can't tell if spi_read_status_register() failed. */
Nico Huber0ecbacb2017-10-14 16:50:43 +0200308 /* FIXME: We don't time out. */
Nico Huber9dc3d8d2020-04-27 22:51:49 +0000309 while (spi_read_status_register(flash) & SPI_SR_WIP)
Nico Huber0ecbacb2017-10-14 16:50:43 +0200310 programmer_delay(poll_delay);
Nico Huber9dc3d8d2020-04-27 22:51:49 +0000311 /* FIXME: Check the status register for errors. */
Nico Huber0ecbacb2017-10-14 16:50:43 +0200312 return 0;
313}
314
Nico Hubera3140d02017-10-15 11:20:58 +0200315/**
316 * Execute WREN plus another one byte `op`, optionally poll WIP afterwards.
317 *
318 * @param flash the flash chip's context
319 * @param op the operation to execute
320 * @param poll_delay interval in us for polling WIP, don't poll if zero
321 * @return 0 on success, non-zero otherwise
322 */
323static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, const unsigned int poll_delay)
Sean Nelson14ba6682010-02-26 05:48:29 +0000324{
Sean Nelson14ba6682010-02-26 05:48:29 +0000325 struct spi_command cmds[] = {
326 {
Richard Hughesdf490582018-12-19 11:57:15 +0000327 .readarr = 0,
Edward O'Callaghan53a99cd2020-10-30 11:32:28 +1100328 .writecnt = JEDEC_WREN_OUTSIZE,
Nico Hubera3140d02017-10-15 11:20:58 +0200329 .writearr = (const unsigned char[]){ JEDEC_WREN },
Sean Nelson14ba6682010-02-26 05:48:29 +0000330 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000331 .readarr = 0,
Nico Hubera3140d02017-10-15 11:20:58 +0200332 .writecnt = 1,
333 .writearr = (const unsigned char[]){ op },
334 },
335 NULL_SPI_CMD,
336 };
337
338 const int result = spi_send_multicommand(flash, cmds);
339 if (result)
340 msg_cerr("%s failed during command execution\n", __func__);
341
Nico Huber0ecbacb2017-10-14 16:50:43 +0200342 const int status = poll_delay ? spi_poll_wip(flash, poll_delay) : 0;
Nico Hubera3140d02017-10-15 11:20:58 +0200343
Nico Huber0ecbacb2017-10-14 16:50:43 +0200344 return result ? result : status;
345}
346
Nico Huber7e3c81a2017-10-14 18:56:50 +0200347static int spi_write_extended_address_register(struct flashctx *const flash, const uint8_t regdata)
348{
Nico Huber57dbd642018-03-13 18:01:05 +0100349 const uint8_t op = flash->chip->wrea_override ? : JEDEC_WRITE_EXT_ADDR_REG;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200350 struct spi_command cmds[] = {
351 {
Richard Hughesdf490582018-12-19 11:57:15 +0000352 .readarr = 0,
Nico Huber7e3c81a2017-10-14 18:56:50 +0200353 .writecnt = 1,
354 .writearr = (const unsigned char[]){ JEDEC_WREN },
355 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000356 .readarr = 0,
Nico Huber7e3c81a2017-10-14 18:56:50 +0200357 .writecnt = 2,
Nico Huber57dbd642018-03-13 18:01:05 +0100358 .writearr = (const unsigned char[]){ op, regdata },
Nico Huber7e3c81a2017-10-14 18:56:50 +0200359 },
360 NULL_SPI_CMD,
361 };
362
363 const int result = spi_send_multicommand(flash, cmds);
364 if (result)
365 msg_cerr("%s failed during command execution\n", __func__);
366 return result;
367}
368
Nico Huber7eb38aa2019-03-21 15:42:54 +0100369int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high)
Nico Huberf43c6542017-10-14 17:47:28 +0200370{
371 if (flash->address_high_byte != addr_high &&
372 spi_write_extended_address_register(flash, addr_high))
373 return -1;
374 flash->address_high_byte = addr_high;
375 return 0;
376}
377
Nico Hubera1672f82017-10-14 18:00:20 +0200378static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[],
379 const bool native_4ba, const unsigned int addr)
Nico Huber0ecbacb2017-10-14 16:50:43 +0200380{
Nico Hubera1672f82017-10-14 18:00:20 +0200381 if (native_4ba || flash->in_4ba_mode) {
Nico Huber1cf407b2017-11-10 20:18:23 +0100382 if (!spi_master_4ba(flash)) {
383 msg_cwarn("4-byte address requested but master can't handle 4-byte addresses.\n");
384 return -1;
385 }
Nico Huberf43c6542017-10-14 17:47:28 +0200386 cmd_buf[1] = (addr >> 24) & 0xff;
387 cmd_buf[2] = (addr >> 16) & 0xff;
388 cmd_buf[3] = (addr >> 8) & 0xff;
389 cmd_buf[4] = (addr >> 0) & 0xff;
390 return 4;
391 } else {
392 if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR) {
393 if (spi_set_extended_address(flash, addr >> 24))
394 return -1;
Nico Huber1cf407b2017-11-10 20:18:23 +0100395 } else if (addr >> 24) {
396 msg_cerr("Can't handle 4-byte address for opcode '0x%02x'\n"
397 "with this chip/programmer combination.\n", cmd_buf[0]);
398 return -1;
Nico Huberf43c6542017-10-14 17:47:28 +0200399 }
400 cmd_buf[1] = (addr >> 16) & 0xff;
401 cmd_buf[2] = (addr >> 8) & 0xff;
402 cmd_buf[3] = (addr >> 0) & 0xff;
403 return 3;
404 }
Nico Huber0ecbacb2017-10-14 16:50:43 +0200405}
406
407/**
408 * Execute WREN plus another `op` that takes an address and
409 * optional data, poll WIP afterwards.
410 *
411 * @param flash the flash chip's context
412 * @param op the operation to execute
Nico Hubera1672f82017-10-14 18:00:20 +0200413 * @param native_4ba whether `op` always takes a 4-byte address
Nico Huber0ecbacb2017-10-14 16:50:43 +0200414 * @param addr the address parameter to `op`
415 * @param out_bytes bytes to send after the address,
416 * may be NULL if and only if `out_bytes` is 0
417 * @param out_bytes number of bytes to send, 256 at most, may be zero
418 * @param poll_delay interval in us for polling WIP
419 * @return 0 on success, non-zero otherwise
420 */
Nico Hubera1672f82017-10-14 18:00:20 +0200421static int spi_write_cmd(struct flashctx *const flash, const uint8_t op,
422 const bool native_4ba, const unsigned int addr,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200423 const uint8_t *const out_bytes, const size_t out_len,
424 const unsigned int poll_delay)
425{
426 uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN + 256];
427 struct spi_command cmds[] = {
428 {
Richard Hughesdf490582018-12-19 11:57:15 +0000429 .readarr = 0,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200430 .writecnt = 1,
431 .writearr = (const unsigned char[]){ JEDEC_WREN },
432 }, {
Richard Hughesdf490582018-12-19 11:57:15 +0000433 .readarr = 0,
Nico Huber0ecbacb2017-10-14 16:50:43 +0200434 .writearr = cmd,
435 },
436 NULL_SPI_CMD,
437 };
438
439 cmd[0] = op;
Nico Hubera1672f82017-10-14 18:00:20 +0200440 const int addr_len = spi_prepare_address(flash, cmd, native_4ba, addr);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200441 if (addr_len < 0)
442 return 1;
443
444 if (1 + addr_len + out_len > sizeof(cmd)) {
445 msg_cerr("%s called for too long a write\n", __func__);
446 return 1;
447 }
Angel Pons2ee489d2020-03-31 15:32:10 +0200448 if (!out_bytes && out_len > 0)
449 return 1;
Nico Huber0ecbacb2017-10-14 16:50:43 +0200450
451 memcpy(cmd + 1 + addr_len, out_bytes, out_len);
452 cmds[1].writecnt = 1 + addr_len + out_len;
453
454 const int result = spi_send_multicommand(flash, cmds);
455 if (result)
456 msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr);
457
458 const int status = spi_poll_wip(flash, poll_delay);
459
460 return result ? result : status;
Nico Hubera3140d02017-10-15 11:20:58 +0200461}
462
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600463static int spi_chip_erase_60(struct flashctx *flash)
Nico Hubera3140d02017-10-15 11:20:58 +0200464{
465 /* This usually takes 1-85s, so wait in 1s steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100466 return spi_simple_write_cmd(flash, JEDEC_CE_60, 1000 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000467}
468
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600469static int spi_chip_erase_62(struct flashctx *flash)
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000470{
Nico Hubera3140d02017-10-15 11:20:58 +0200471 /* This usually takes 2-5s, so wait in 100ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100472 return spi_simple_write_cmd(flash, JEDEC_CE_62, 100 * 1000);
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000473}
474
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600475static int spi_chip_erase_c7(struct flashctx *flash)
Sean Nelson14ba6682010-02-26 05:48:29 +0000476{
Nico Hubera3140d02017-10-15 11:20:58 +0200477 /* This usually takes 1-85s, so wait in 1s steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100478 return spi_simple_write_cmd(flash, JEDEC_CE_C7, 1000 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000479}
480
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000481int spi_block_erase_52(struct flashctx *flash, unsigned int addr,
482 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000483{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200484 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100485 return spi_write_cmd(flash, JEDEC_BE_52, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000486}
487
488/* Block size is usually
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000489 * 32M (one die) for Micron
490 */
491int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
492{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200493 /* This usually takes 240-480s, so wait in 500ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100494 return spi_write_cmd(flash, JEDEC_BE_C4, false, addr, NULL, 0, 500 * 1000);
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000495}
496
497/* Block size is usually
Sean Nelson14ba6682010-02-26 05:48:29 +0000498 * 64k for Macronix
499 * 32k for SST
500 * 4-32k non-uniform for EON
501 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000502int spi_block_erase_d8(struct flashctx *flash, unsigned int addr,
503 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000504{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200505 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100506 return spi_write_cmd(flash, JEDEC_BE_D8, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000507}
508
509/* Block size is usually
510 * 4k for PMC
511 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000512int spi_block_erase_d7(struct flashctx *flash, unsigned int addr,
513 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000514{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200515 /* This usually takes 100-4000ms, so wait in 100ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100516 return spi_write_cmd(flash, JEDEC_BE_D7, false, addr, NULL, 0, 100 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000517}
518
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000519/* Page erase (usually 256B blocks) */
520int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
521{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200522 /* This takes up to 20ms usually (on worn out devices
523 up to the 0.5s range), so wait in 1ms steps. */
Nico Hubera1672f82017-10-14 18:00:20 +0200524 return spi_write_cmd(flash, 0xdb, false, addr, NULL, 0, 1 * 1000);
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000525}
526
Sean Nelson14ba6682010-02-26 05:48:29 +0000527/* Sector size is usually 4k, though Macronix eliteflash has 64k */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000528int spi_block_erase_20(struct flashctx *flash, unsigned int addr,
529 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000530{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200531 /* This usually takes 15-800ms, so wait in 10ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100532 return spi_write_cmd(flash, JEDEC_SE, false, addr, NULL, 0, 10 * 1000);
Sean Nelson14ba6682010-02-26 05:48:29 +0000533}
534
Stefan Tauner94b39b42012-10-27 00:06:02 +0000535int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
536{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200537 /* This usually takes 10ms, so wait in 1ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100538 return spi_write_cmd(flash, JEDEC_BE_50, false, addr, NULL, 0, 1 * 1000);
Stefan Tauner94b39b42012-10-27 00:06:02 +0000539}
540
541int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
542{
Nico Huber0ecbacb2017-10-14 16:50:43 +0200543 /* This usually takes 8ms, so wait in 1ms steps. */
Edward O'Callaghan8a9218b2020-10-30 11:41:01 +1100544 return spi_write_cmd(flash, JEDEC_BE_81, false, addr, NULL, 0, 1 * 1000);
Stefan Tauner94b39b42012-10-27 00:06:02 +0000545}
546
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000547int spi_block_erase_60(struct flashctx *flash, unsigned int addr,
548 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000549{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000550 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000551 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000552 __func__);
553 return -1;
554 }
555 return spi_chip_erase_60(flash);
556}
557
Stefan Tauner3c0fcd02012-09-21 12:46:56 +0000558int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
559{
560 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
561 msg_cerr("%s called with incorrect arguments\n",
562 __func__);
563 return -1;
564 }
565 return spi_chip_erase_62(flash);
566}
567
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000568int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,
569 unsigned int blocklen)
Sean Nelson14ba6682010-02-26 05:48:29 +0000570{
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000571 if ((addr != 0) || (blocklen != flash->chip->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000572 msg_cerr("%s called with incorrect arguments\n",
Sean Nelson14ba6682010-02-26 05:48:29 +0000573 __func__);
574 return -1;
575 }
576 return spi_chip_erase_c7(flash);
577}
578
Nico Huber7e3c81a2017-10-14 18:56:50 +0200579/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
580int spi_block_erase_21(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
581{
582 /* This usually takes 15-800ms, so wait in 10ms steps. */
583 return spi_write_cmd(flash, 0x21, true, addr, NULL, 0, 10 * 1000);
584}
585
586/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
587int spi_block_erase_5c(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
588{
589 /* This usually takes 100-4000ms, so wait in 100ms steps. */
590 return spi_write_cmd(flash, 0x5c, true, addr, NULL, 0, 100 * 1000);
591}
592
593/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) */
594int spi_block_erase_dc(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
595{
596 /* This usually takes 100-4000ms, so wait in 100ms steps. */
597 return spi_write_cmd(flash, 0xdc, true, addr, NULL, 0, 100 * 1000);
598}
599
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000600erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode)
601{
602 switch(opcode){
603 case 0xff:
604 case 0x00:
605 /* Not specified, assuming "not supported". */
606 return NULL;
607 case 0x20:
608 return &spi_block_erase_20;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200609 case 0x21:
610 return &spi_block_erase_21;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000611 case 0x50:
612 return &spi_block_erase_50;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000613 case 0x52:
614 return &spi_block_erase_52;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200615 case 0x5c:
616 return &spi_block_erase_5c;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000617 case 0x60:
618 return &spi_block_erase_60;
Stefan Tauner730e7e72013-05-01 14:04:19 +0000619 case 0x62:
620 return &spi_block_erase_62;
621 case 0x81:
622 return &spi_block_erase_81;
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +0000623 case 0xc4:
624 return &spi_block_erase_c4;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000625 case 0xc7:
626 return &spi_block_erase_c7;
627 case 0xd7:
628 return &spi_block_erase_d7;
629 case 0xd8:
630 return &spi_block_erase_d8;
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000631 case 0xdb:
632 return &spi_block_erase_db;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200633 case 0xdc:
634 return &spi_block_erase_dc;
Stefan Taunerac1b4c82012-02-17 14:51:04 +0000635 default:
636 msg_cinfo("%s: unknown erase opcode (0x%02x). Please report "
637 "this at flashrom@flashrom.org\n", __func__, opcode);
638 return NULL;
639 }
640}
641
Nico Huber0ecbacb2017-10-14 16:50:43 +0200642static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000643{
Nico Huber1cf407b2017-11-10 20:18:23 +0100644 const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_WRITE && spi_master_4ba(flash);
Nico Hubera1672f82017-10-14 18:00:20 +0200645 const uint8_t op = native_4ba ? JEDEC_BYTE_PROGRAM_4BA : JEDEC_BYTE_PROGRAM;
646 return spi_write_cmd(flash, op, native_4ba, addr, bytes, len, 10);
Sean Nelson14ba6682010-02-26 05:48:29 +0000647}
648
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000649int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes,
650 unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000651{
Edward O'Callaghanc64486b2020-10-16 12:15:08 +1100652 const bool native_4ba = flash->chip->feature_bits & FEATURE_4BA_READ && spi_master_4ba(flash);
Nico Hubera1672f82017-10-14 18:00:20 +0200653 uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { native_4ba ? JEDEC_READ_4BA : JEDEC_READ, };
Nico Huber0ecbacb2017-10-14 16:50:43 +0200654
Nico Hubera1672f82017-10-14 18:00:20 +0200655 const int addr_len = spi_prepare_address(flash, cmd, native_4ba, address);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200656 if (addr_len < 0)
657 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000658
659 /* Send Read */
Nico Huber0ecbacb2017-10-14 16:50:43 +0200660 return spi_send_command(flash, 1 + addr_len, len, cmd, bytes);
Sean Nelson14ba6682010-02-26 05:48:29 +0000661}
662
663/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000664 * Read a part of the flash chip.
Nico Huberd8b2e802019-06-18 23:39:56 +0200665 * Data is read in chunks with a maximum size of chunksize.
Sean Nelson14ba6682010-02-26 05:48:29 +0000666 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000667int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start,
668 unsigned int len, unsigned int chunksize)
Sean Nelson14ba6682010-02-26 05:48:29 +0000669{
Nico Huberd8b2e802019-06-18 23:39:56 +0200670 int ret;
671 size_t to_read;
672 for (; len; len -= to_read, buf += to_read, start += to_read) {
673 to_read = min(chunksize, len);
674 ret = spi_nbyte_read(flash, start, buf, to_read);
675 if (ret)
676 return ret;
Sean Nelson14ba6682010-02-26 05:48:29 +0000677 }
Nico Huberd8b2e802019-06-18 23:39:56 +0200678 return 0;
Sean Nelson14ba6682010-02-26 05:48:29 +0000679}
680
681/*
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000682 * Write a part of the flash chip.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000683 * FIXME: Use the chunk code from Michael Karcher instead.
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000684 * Each page is written separately in chunks with a maximum size of chunksize.
685 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000686int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000687 unsigned int len, unsigned int chunksize)
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000688{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000689 unsigned int i, j, starthere, lenhere, towrite;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000690 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000691 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000692 * spi_chip_write_256 have page_size set to max_writechunk_size, so
693 * we're OK for now.
694 */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000695 unsigned int page_size = flash->chip->page_size;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000696
697 /* Warning: This loop has a very unusual condition and body.
698 * The loop needs to go through each page with at least one affected
699 * byte. The lowest page number is (start / page_size) since that
700 * division rounds down. The highest page number we want is the page
701 * where the last byte of the range lives. That last byte has the
702 * address (start + len - 1), thus the highest page number is
703 * (start + len - 1) / page_size. Since we want to include that last
704 * page as well, the loop condition uses <=.
705 */
706 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
707 /* Byte position of the first byte in the range in this page. */
708 /* starthere is an offset to the base address of the chip. */
709 starthere = max(start, i * page_size);
710 /* Length of bytes in the range in this page. */
711 lenhere = min(start + len, (i + 1) * page_size) - starthere;
712 for (j = 0; j < lenhere; j += chunksize) {
Nico Huber7a077222017-10-14 18:18:30 +0200713 int rc;
714
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000715 towrite = min(chunksize, lenhere - j);
Nico Huber7a077222017-10-14 18:18:30 +0200716 rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite);
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000717 if (rc)
Nico Huber7a077222017-10-14 18:18:30 +0200718 return rc;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000719 }
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000720 }
721
Nico Huber7a077222017-10-14 18:18:30 +0200722 return 0;
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +0000723}
724
725/*
Sean Nelson14ba6682010-02-26 05:48:29 +0000726 * Program chip using byte programming. (SLOW!)
727 * This is for chips which can only handle one byte writes
728 * and for chips where memory mapped programming is impossible
729 * (e.g. due to size constraints in IT87* for over 512 kB)
730 */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000731/* real chunksize is 1, logical chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000732int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Sean Nelson14ba6682010-02-26 05:48:29 +0000733{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000734 unsigned int i;
Sean Nelson14ba6682010-02-26 05:48:29 +0000735
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000736 for (i = start; i < start + len; i++) {
Nico Huber7a077222017-10-14 18:18:30 +0200737 if (spi_nbyte_program(flash, i, buf + i - start, 1))
Sean Nelson14ba6682010-02-26 05:48:29 +0000738 return 1;
Sean Nelson14ba6682010-02-26 05:48:29 +0000739 }
Sean Nelson14ba6682010-02-26 05:48:29 +0000740 return 0;
741}
742
Mark Marshallf20b7be2014-05-09 21:16:21 +0000743int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000744{
745 uint32_t pos = start;
Sean Nelson14ba6682010-02-26 05:48:29 +0000746 int result;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000747 unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = {
748 JEDEC_AAI_WORD_PROGRAM,
749 };
Sean Nelson14ba6682010-02-26 05:48:29 +0000750
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000751 /* The even start address and even length requirements can be either
752 * honored outside this function, or we can call spi_byte_program
753 * for the first and/or last byte and use AAI for the rest.
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000754 * FIXME: Move this to generic code.
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000755 */
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000756 /* The data sheet requires a start address with the low bit cleared. */
Carl-Daniel Hailfinger9a795d82010-07-14 16:19:05 +0000757 if (start % 2) {
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000758 msg_cerr("%s: start address not even! Please report a bug at "
759 "flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000760 if (spi_chip_write_1(flash, buf, start, start % 2))
761 return SPI_GENERIC_ERROR;
762 pos += start % 2;
763 /* Do not return an error for now. */
764 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000765 }
766 /* The data sheet requires total AAI write length to be even. */
767 if (len % 2) {
768 msg_cerr("%s: total write length not even! Please report a "
769 "bug at flashrom@flashrom.org\n", __func__);
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000770 /* Do not return an error for now. */
771 //return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000772 }
773
Nico Hubera1672f82017-10-14 18:00:20 +0200774 result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, false, start, buf + pos - start, 2, 10);
Nico Huber0ecbacb2017-10-14 16:50:43 +0200775 if (result)
Stefan Reinauer87ace662014-04-26 16:12:55 +0000776 goto bailout;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000777
778 /* We already wrote 2 bytes in the multicommand step. */
779 pos += 2;
780
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000781 /* Are there at least two more bytes to write? */
782 while (pos < start + len - 1) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000783 cmd[1] = buf[pos++ - start];
784 cmd[2] = buf[pos++ - start];
Stefan Reinauer87ace662014-04-26 16:12:55 +0000785 result = spi_send_command(flash, JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL);
786 if (result != 0) {
787 msg_cerr("%s failed during followup AAI command execution: %d\n", __func__, result);
788 goto bailout;
789 }
Nico Huber0ecbacb2017-10-14 16:50:43 +0200790 if (spi_poll_wip(flash, 10))
791 goto bailout;
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000792 }
793
Stefan Tauner59c4d792014-04-26 16:13:09 +0000794 /* Use WRDI to exit AAI mode. This needs to be done before issuing any other non-AAI command. */
795 result = spi_write_disable(flash);
796 if (result != 0) {
797 msg_cerr("%s failed to disable AAI mode.\n", __func__);
798 return SPI_GENERIC_ERROR;
799 }
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000800
801 /* Write remaining byte (if any). */
802 if (pos < start + len) {
Carl-Daniel Hailfingerccfe0ac2010-10-27 22:07:11 +0000803 if (spi_chip_write_1(flash, buf + pos - start, pos, pos % 2))
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000804 return SPI_GENERIC_ERROR;
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000805 }
806
Sean Nelson14ba6682010-02-26 05:48:29 +0000807 return 0;
Stefan Reinauer87ace662014-04-26 16:12:55 +0000808
809bailout:
Stefan Tauner59c4d792014-04-26 16:13:09 +0000810 result = spi_write_disable(flash);
811 if (result != 0)
812 msg_cerr("%s failed to disable AAI mode.\n", __func__);
Stefan Reinauer87ace662014-04-26 16:12:55 +0000813 return SPI_GENERIC_ERROR;
Sean Nelson14ba6682010-02-26 05:48:29 +0000814}
Nico Huber7e3c81a2017-10-14 18:56:50 +0200815
Nico Huberfe34d2a2017-11-10 21:10:20 +0100816static int spi_enter_exit_4ba(struct flashctx *const flash, const bool enter)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200817{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100818 const unsigned char cmd = enter ? JEDEC_ENTER_4_BYTE_ADDR_MODE : JEDEC_EXIT_4_BYTE_ADDR_MODE;
819 int ret = 1;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200820
Nico Huberfe34d2a2017-11-10 21:10:20 +0100821 if (flash->chip->feature_bits & FEATURE_4BA_ENTER)
822 ret = spi_send_command(flash, sizeof(cmd), 0, &cmd, NULL);
823 else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_WREN)
824 ret = spi_simple_write_cmd(flash, cmd, 0);
Nico Huber86bddb52018-03-13 18:14:52 +0100825 else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_EAR7)
826 ret = spi_set_extended_address(flash, enter ? 0x80 : 0x00);
Nico Huberfe34d2a2017-11-10 21:10:20 +0100827
Nico Huber7e3c81a2017-10-14 18:56:50 +0200828 if (!ret)
Nico Huberfe34d2a2017-11-10 21:10:20 +0100829 flash->in_4ba_mode = enter;
Nico Huber7e3c81a2017-10-14 18:56:50 +0200830 return ret;
831}
832
Nico Huberfe34d2a2017-11-10 21:10:20 +0100833int spi_enter_4ba(struct flashctx *const flash)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200834{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100835 return spi_enter_exit_4ba(flash, true);
Nico Huber7e3c81a2017-10-14 18:56:50 +0200836}
837
Nico Huberfe34d2a2017-11-10 21:10:20 +0100838int spi_exit_4ba(struct flashctx *flash)
Nico Huber7e3c81a2017-10-14 18:56:50 +0200839{
Nico Huberfe34d2a2017-11-10 21:10:20 +0100840 return spi_enter_exit_4ba(flash, false);
Nico Huber7e3c81a2017-10-14 18:56:50 +0200841}