blob: ada615e77ad8ee876c09216af8462f16ad261277 [file] [log] [blame]
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2011 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000014 */
15
16/* Datasheet: http://download.intel.com/design/network/datashts/82559_Fast_Ethernet_Multifunction_PCI_Cardbus_Controller_Datasheet.pdf */
17
18#include <stdlib.h>
19#include "flash.h"
20#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000021#include "hwaccess.h"
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000022
Jacob Garberafc3ad62019-06-24 16:05:28 -060023static uint8_t *nicintel_bar;
24static uint8_t *nicintel_control_bar;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000025
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020026static const struct dev_entry nics_intel[] = {
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000027 {PCI_VENDOR_ID_INTEL, 0x1209, NT, "Intel", "8255xER/82551IT Fast Ethernet Controller"},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +000028 {PCI_VENDOR_ID_INTEL, 0x1229, OK, "Intel", "82557/8/9/0/1 Ethernet Pro 100"},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000029
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000030 {0},
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000031};
32
33/* Arbitrary limit, taken from the datasheet I just had lying around.
34 * 128 kByte on the 82559 device. Or not. Depends on whom you ask.
35 */
36#define NICINTEL_MEMMAP_SIZE (128 * 1024)
37#define NICINTEL_MEMMAP_MASK (NICINTEL_MEMMAP_SIZE - 1)
38
Elyes HAOUAS124ef382018-03-27 12:15:09 +020039#define NICINTEL_CONTROL_MEMMAP_SIZE 0x10
David Hendricks8bb20212011-06-14 01:35:36 +000040
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000041#define CSR_FCR 0x0c
42
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000043static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100044 chipaddr addr)
45{
46 pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
47}
48
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000049static uint8_t nicintel_chip_readb(const struct flashctx *flash,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100050 const chipaddr addr)
51{
52 return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
53}
54
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000055static const struct par_master par_master_nicintel = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000056 .chip_readb = nicintel_chip_readb,
57 .chip_readw = fallback_chip_readw,
58 .chip_readl = fallback_chip_readl,
59 .chip_readn = fallback_chip_readn,
60 .chip_writeb = nicintel_chip_writeb,
61 .chip_writew = fallback_chip_writew,
62 .chip_writel = fallback_chip_writel,
63 .chip_writen = fallback_chip_writen,
64};
65
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020066static int nicintel_init(void)
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000067{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000068 struct pci_dev *dev = NULL;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000069 uintptr_t addr;
70
71 /* Needed only for PCI accesses on some platforms.
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000072 * FIXME: Refactor that into get_mem_perms/rget_io_perms/get_pci_perms?
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000073 */
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000074 if (rget_io_perms())
75 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000076
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000077 /* FIXME: BAR2 is not available if the device uses the CardBus function. */
78 dev = pcidev_init(nics_intel, PCI_BASE_ADDRESS_2);
79 if (!dev)
80 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000081
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000082 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
Niklas Söderlund89edf362013-08-23 23:29:23 +000083 if (!addr)
84 return 1;
85
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000086 nicintel_bar = rphysmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000087 if (nicintel_bar == ERROR_PTR)
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000088 return 1;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000089
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000090 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000091 if (!addr)
92 return 1;
93
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000094 nicintel_control_bar = rphysmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000095 if (nicintel_control_bar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +000096 return 1;
97
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +000098 /* FIXME: This register is pretty undocumented in all publicly available
99 * documentation from Intel. Let me quote the complete info we have:
100 * "Flash Control Register: The Flash Control register allows the CPU to
101 * enable writes to an external Flash. The Flash Control Register is a
102 * 32-bit field that allows access to an external Flash device."
103 * Ah yes, we also know where it is, but we have absolutely _no_ idea
104 * what we should do with it. Write 0x0001 because we have nothing
105 * better to do with our time.
106 */
107 pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
108
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000109 max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000110 register_par_master(&par_master_nicintel, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000111
112 return 0;
Carl-Daniel Hailfingerb713d2e2011-05-08 00:24:18 +0000113}
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200114
115const struct programmer_entry programmer_nicintel = {
116 .name = "nicintel",
117 .type = PCI,
118 .devs.dev = nics_intel,
119 .init = nicintel_init,
120 .map_flash_region = fallback_map,
121 .unmap_flash_region = fallback_unmap,
122 .delay = internal_delay,
123};