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Joseph C. Lehnerc2644a32016-01-16 23:45:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2015 Joseph C. Lehner <joseph.c.lehner@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000015 */
16
17#if defined(__i386__) || defined(__x86_64__)
18
19#include <string.h>
20#include <stdlib.h>
21#include "flash.h"
22#include "programmer.h"
23#include "hwaccess.h"
24
25#define MAX_ROM_DECODE (32 * 1024)
26#define ADDR_MASK (MAX_ROM_DECODE - 1)
27
28/*
29 * In the absence of any public docs on the PDC2026x family, this programmer was created through a mix of
30 * reverse-engineering and trial and error.
31 *
32 * The only device tested is an Ultra100 controller, but the logic for programming the other 2026x controllers
33 * is the same, so it should, in theory, work for those as well.
34 *
35 * While the tested Ultra100 controller used a 128 kB MX29F001T chip, A16 and A15 showed continuity to ground,
36 * thus limiting the the programmer on this card to 32 kB. Without other controllers to test this programmer on,
37 * this is currently a hard limit. Note that ROM files for these controllers are 16 kB only.
38 *
39 * Since flashrom does not support accessing flash chips larger than the size limit of the programmer (the
40 * tested Ultra100 uses a 128 kB MX29F001T chip), the chip size is hackishly adjusted in atapromise_limit_chip.
41 */
42
43static uint32_t io_base_addr = 0;
44static uint32_t rom_base_addr = 0;
45
46static uint8_t *atapromise_bar = NULL;
47static size_t rom_size = 0;
48
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020049static const struct dev_entry ata_promise[] = {
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000050 {0x105a, 0x4d38, NT, "Promise", "PDC20262 (FastTrak66/Ultra66)"},
51 {0x105a, 0x0d30, NT, "Promise", "PDC20265 (FastTrak100 Lite/Ultra100)"},
52 {0x105a, 0x4d30, OK, "Promise", "PDC20267 (FastTrak100/Ultra100)"},
53 {0},
54};
55
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020056static void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len)
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000057{
58 /* In case fallback_map ever returns something other than NULL. */
59 return NULL;
60}
61
62static void atapromise_limit_chip(struct flashchip *chip)
63{
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000064 unsigned int i, size;
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000065 unsigned int usable_erasers = 0;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000066
67 size = chip->total_size * 1024;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000068
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000069 /* Chip is small enough or already limited. */
70 if (size <= rom_size)
71 return;
72
73 /* Undefine all block_erasers that don't operate on the whole chip,
74 * and adjust the eraseblock size of those which do.
75 */
76 for (i = 0; i < NUM_ERASEFUNCTIONS; ++i) {
77 if (chip->block_erasers[i].eraseblocks[0].size != size) {
78 chip->block_erasers[i].eraseblocks[0].count = 0;
79 chip->block_erasers[i].block_erase = NULL;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000080 } else {
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000081 chip->block_erasers[i].eraseblocks[0].size = rom_size;
82 usable_erasers++;
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000083 }
84 }
85
Carl-Daniel Hailfinger1c2d23a2016-02-18 23:11:52 +000086 if (usable_erasers) {
87 chip->total_size = rom_size / 1024;
88 if (chip->page_size > rom_size)
89 chip->page_size = rom_size;
90 } else {
91 msg_pdbg("Failed to adjust size of chip \"%s\" (%d kB).\n", chip->name, chip->total_size);
92 }
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +000093}
94
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100095static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
96{
97 uint32_t data;
98
99 atapromise_limit_chip(flash->chip);
100 data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val;
101 OUTL(data, io_base_addr + 0x14);
102}
103
104static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr)
105{
106 atapromise_limit_chip(flash->chip);
107 return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK));
108}
109
110static const struct par_master par_master_atapromise = {
111 .chip_readb = atapromise_chip_readb,
112 .chip_readw = fallback_chip_readw,
113 .chip_readl = fallback_chip_readl,
114 .chip_readn = fallback_chip_readn,
115 .chip_writeb = atapromise_chip_writeb,
116 .chip_writew = fallback_chip_writew,
117 .chip_writel = fallback_chip_writel,
118 .chip_writen = fallback_chip_writen,
119};
120
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200121static int atapromise_init(void)
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000122{
123 struct pci_dev *dev = NULL;
124
125 if (rget_io_perms())
126 return 1;
127
128 dev = pcidev_init(ata_promise, PCI_BASE_ADDRESS_4);
129 if (!dev)
130 return 1;
131
132 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4) & 0xfffe;
133 if (!io_base_addr) {
134 return 1;
135 }
136
137 /* Not exactly sure what this does, because flashing seems to work
138 * well without it. However, PTIFLASH does it, so we do it too.
139 */
140 OUTB(1, io_base_addr + 0x10);
141
142 rom_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5);
143 if (!rom_base_addr) {
144 msg_pdbg("Failed to read BAR5\n");
145 return 1;
146 }
147
148 rom_size = dev->rom_size > MAX_ROM_DECODE ? MAX_ROM_DECODE : dev->rom_size;
149 atapromise_bar = (uint8_t*)rphysmap("Promise", rom_base_addr, rom_size);
150 if (atapromise_bar == ERROR_PTR) {
151 return 1;
152 }
153
154 max_rom_decode.parallel = rom_size;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000155 register_par_master(&par_master_atapromise, BUS_PARALLEL, NULL);
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000156
157 msg_pwarn("Do not use this device as a generic programmer. It will leave anything outside\n"
158 "the first %zu kB of the flash chip in an undefined state. It works fine for the\n"
Elyes HAOUASe2c90c42018-08-18 09:04:41 +0200159 "purpose of updating the firmware of this device (padding may necessary).\n",
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000160 rom_size / 1024);
161
162 return 0;
163}
164
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200165const struct programmer_entry programmer_atapromise = {
166 .name = "atapromise",
167 .type = PCI,
168 .devs.dev = ata_promise,
169 .init = atapromise_init,
170 .map_flash_region = atapromise_map,
171 .unmap_flash_region = fallback_unmap,
172 .delay = internal_delay,
173};
174
Joseph C. Lehnerc2644a32016-01-16 23:45:25 +0000175#else
176#error PCI port I/O access is not supported on this architecture yet.
177#endif