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Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Joerg Fischer52a15492010-05-21 22:28:19 +000015 */
16
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000017#if defined(__i386__) || defined(__x86_64__)
18
Joerg Fischer52a15492010-05-21 22:28:19 +000019#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000020#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000021#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000022#include "hwaccess.h"
Joerg Fischer52a15492010-05-21 22:28:19 +000023
24#define PCI_VENDOR_ID_REALTEK 0x10ec
25#define PCI_VENDOR_ID_SMC1211 0x1113
26
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000027static uint32_t io_base_addr = 0;
Sergey Lichack98f47102012-08-27 01:24:15 +000028static int bios_rom_addr, bios_rom_data;
Joerg Fischer52a15492010-05-21 22:28:19 +000029
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000030const struct dev_entry nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000031 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Sergey Lichack98f47102012-08-27 01:24:15 +000032 {0x10ec, 0x8169, NT, "Realtek", "RTL8169"},
33 {0x1113, 0x1211, OK, "SMC", "1211TX"}, /* RTL8139 clone */
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000034
35 {0},
Joerg Fischer52a15492010-05-21 22:28:19 +000036};
37
Sergey Lichack98f47102012-08-27 01:24:15 +000038static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
39static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000040static const struct par_master par_master_nicrealtek = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000041 .chip_readb = nicrealtek_chip_readb,
42 .chip_readw = fallback_chip_readw,
43 .chip_readl = fallback_chip_readl,
44 .chip_readn = fallback_chip_readn,
45 .chip_writeb = nicrealtek_chip_writeb,
46 .chip_writew = fallback_chip_writew,
47 .chip_writel = fallback_chip_writel,
48 .chip_writen = fallback_chip_writen,
49};
50
David Hendricks8bb20212011-06-14 01:35:36 +000051static int nicrealtek_shutdown(void *data)
52{
53 /* FIXME: We forgot to disable software access again. */
David Hendricks8bb20212011-06-14 01:35:36 +000054 return 0;
55}
56
Joerg Fischer52a15492010-05-21 22:28:19 +000057int nicrealtek_init(void)
58{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000059 struct pci_dev *dev = NULL;
60
Stefan Taunerd7d423b2012-10-20 09:13:16 +000061 if (rget_io_perms())
62 return 1;
63
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000064 dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0);
65 if (!dev)
Stefan Taunerd7d423b2012-10-20 09:13:16 +000066 return 1;
67
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000068 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000069 if (!io_base_addr)
70 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000071
Sergey Lichack98f47102012-08-27 01:24:15 +000072 /* Beware, this ignores the vendor ID! */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000073 switch (dev->device_id) {
Sergey Lichack98f47102012-08-27 01:24:15 +000074 case 0x8139: /* RTL8139 */
75 case 0x1211: /* SMC 1211TX */
76 default:
77 bios_rom_addr = 0xD4;
78 bios_rom_data = 0xD7;
79 break;
80 case 0x8169: /* RTL8169 */
81 bios_rom_addr = 0x30;
82 bios_rom_data = 0x33;
83 break;
84 }
85
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000086 if (register_shutdown(nicrealtek_shutdown, NULL))
87 return 1;
88
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +100089 register_par_master(&par_master_nicrealtek, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000090
Joerg Fischer52a15492010-05-21 22:28:19 +000091 return 0;
92}
93
Sergey Lichack98f47102012-08-27 01:24:15 +000094static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000095{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000096 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
97 * enable software access.
98 */
Uwe Hermann829ed842010-05-24 17:39:14 +000099 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000100 io_base_addr + bios_rom_addr);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000101 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
102 * enable software access.
103 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000104 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000105 io_base_addr + bios_rom_addr);
Joerg Fischer52a15492010-05-21 22:28:19 +0000106}
107
Sergey Lichack98f47102012-08-27 01:24:15 +0000108static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +0000109{
Uwe Hermann829ed842010-05-24 17:39:14 +0000110 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000111
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000112 /* FIXME: Can we skip reading the old data and simply use 0? */
113 /* Read old data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000114 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000115 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
116 * enable software access.
117 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000118 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000119 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000120
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000121 /* Read new data. */
Sergey Lichack98f47102012-08-27 01:24:15 +0000122 val = INB(io_base_addr + bios_rom_data);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000123 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
124 * enable software access.
125 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000126 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
Sergey Lichack98f47102012-08-27 01:24:15 +0000127 io_base_addr + bios_rom_addr);
Uwe Hermann829ed842010-05-24 17:39:14 +0000128
129 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000130}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000131
132#else
133#error PCI port I/O access is not supported on this architecture yet.
134#endif