blob: 80fcff5eb848af316e5af59726da7aebbeee8e35 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Dominik Geyerb46acba2008-05-16 12:55:55 +000024#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000025#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000026#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000028#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000029#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000030#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000031
Nico Huberd2d39932019-01-18 16:49:37 +010032/* Apollo Lake */
33#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
34
Nico Huberd54e4f42017-03-23 23:45:47 +010035/* Sunrise Point */
36
37/* Added HSFS Status bits */
38#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
39#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
40#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
41#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
42/* HSFS_BERASE vanished */
43
44/*
45 * HSFC and HSFS 16-bit registers are combined into the 32-bit
46 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
47 * however we still treat them separately in order to reuse code.
48 */
49
50/* Changed HSFC Control bits */
51#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
52#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
53/* New HSFC Control bit */
54#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
55#define HSFC_WET (0x1 << HSFC_WET_OFF)
56
57#define PCH100_FADDR_FLA 0x07ffffff
58
59#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
60#define DLOCK_BMWAG_LOCKDN_OFF 0
61#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
62#define DLOCK_BMRAG_LOCKDN_OFF 1
63#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
64#define DLOCK_SBMWAG_LOCKDN_OFF 2
65#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
66#define DLOCK_SBMRAG_LOCKDN_OFF 3
67#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
68#define DLOCK_PR0_LOCKDN_OFF 8
69#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
70#define DLOCK_PR1_LOCKDN_OFF 9
71#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
72#define DLOCK_PR2_LOCKDN_OFF 10
73#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
74#define DLOCK_PR3_LOCKDN_OFF 11
75#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
76#define DLOCK_PR4_LOCKDN_OFF 12
77#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
78#define DLOCK_SSEQ_LOCKDN_OFF 16
79#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
80
81#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
82#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
83
84#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
85#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
86#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
87#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
88
Stefan Reinauera9424d52008-06-27 16:28:34 +000089/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000090#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
91#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
92#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
93#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
94#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
95#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
96#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
97#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
98#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
99#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
100#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
101 /* 6-12: reserved */
102#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
103#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
104#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
105#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
106#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
107#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
108
109#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
110#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
111#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
112#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
113#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
114 /* 3-7: reserved */
115#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
116#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
117 /* 14: reserved */
118#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
119#define HSFC_SME (0x1 << HSFC_SME_OFF)
120
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000121#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100122#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000123#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000124
Stefan Tauner29c80832011-06-12 08:14:10 +0000125#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
126#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
127
128#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000129#define PR_WP_OFF 31 /* 31: write protection enable */
130#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000131
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000132#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000133#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
134#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
135#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
136#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
137#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
138#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
139#define SSFS_AEL_OFF 4 /* Access Error Log */
140#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000141/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000142#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000143
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000146 * therefore SSFC bits are off by 8. */
147 /* 0: reserved */
148#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
149#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
150#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
151#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
152#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
153#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
154#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
155#define SSFC_COP (0x7 << SSFC_COP_OFF)
156 /* 7: reserved */
157#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
158#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
159#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
160#define SSFC_DS (0x1 << SSFC_DS_OFF)
161#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
162#define SSFC_SME (0x1 << SSFC_SME_OFF)
163#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
164#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
165#define SSFC_SCF_20MHZ 0x00000000
166#define SSFC_SCF_33MHZ 0x01000000
167 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000168#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000169
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000170#define ICH9_REG_PREOP 0x94 /* 16 Bits */
171#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
172#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000173
Stefan Tauner29c80832011-06-12 08:14:10 +0000174#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
175#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
176
Stefan Tauner1e146392011-09-15 23:52:55 +0000177#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
178#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
179#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
180/* The individual fields of the VSCC registers are defined in the file
181 * ich_descriptors.h. The reason is that the same layout is also used in the
182 * flash descriptor to define the properties of the different flash chips
183 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
184 * with the information from the descriptor on startup depending on the actual
185 * chip(s) detected. */
186
Stefan Taunerbd649e42011-07-01 00:39:16 +0000187#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
188#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
189#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
190
Dominik Geyerb46acba2008-05-16 12:55:55 +0000191// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000192#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
193#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
194#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
195#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000196
Stefan Reinauera9424d52008-06-27 16:28:34 +0000197// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000198#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000199#define SPIS_SCIP 0x0001
200#define SPIS_GRANT 0x0002
201#define SPIS_CDS 0x0004
202#define SPIS_FCERR 0x0008
203#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000204
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000205/* VIA SPI is compatible with ICH7, but maxdata
206 to transfer is 16 bytes.
207
208 DATA byte count on ICH7 is 8:13, on VIA 8:11
209
210 bit 12 is port select CS0 CS1
211 bit 13 is FAST READ enable
212 bit 7 is used with fast read and one shot controls CS de-assert?
213*/
214
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000215#define ICH7_REG_SPIC 0x02 /* 16 Bits */
216#define SPIC_SCGO 0x0002
217#define SPIC_ACS 0x0004
218#define SPIC_SPOP 0x0008
219#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000220
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000221#define ICH7_REG_SPIA 0x04 /* 32 Bits */
222#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
223#define ICH7_REG_PREOP 0x54 /* 16 Bits */
224#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
225#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000226
Nico Huber7590d1a2016-05-03 13:38:28 +0200227enum ich_access_protection {
228 NO_PROT = 0,
229 READ_PROT = 1,
230 WRITE_PROT = 2,
231 LOCKED = 3,
232};
233
FENG yu ningc05a2952008-12-08 18:16:58 +0000234/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000235static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000236
Stefan Taunera8d838d2011-11-06 23:51:09 +0000237static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200238static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000239
Michael Karchera4448d92010-07-22 18:04:15 +0000240static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000241
Dominik Geyerb46acba2008-05-16 12:55:55 +0000242typedef struct _OPCODE {
243 uint8_t opcode; //This commands spi opcode
244 uint8_t spi_type; //This commands spi type
245 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
246} OPCODE;
247
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000248/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000249 * Preop 1: Write Enable
250 * Preop 2: Write Status register enable
251 *
252 * OP 0: Write address
253 * OP 1: Read Address
254 * OP 2: ERASE block
255 * OP 3: Read Status register
256 * OP 4: Read ID
257 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000258 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 * OP 7: Chip erase
260 */
261typedef struct _OPCODES {
262 uint8_t preop[2];
263 OPCODE opcode[8];
264} OPCODES;
265
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000266static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000267
268/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000269static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000270{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000271 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000272}
273
Uwe Hermann09e04f72009-05-16 22:36:00 +0000274static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000275{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000276 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000277}
278
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000279static uint16_t REGREAD8(int X)
280{
281 return mmio_readb(ich_spibar + X);
282}
283
Stefan Taunerccd92a12011-07-01 00:39:01 +0000284#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
285#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
286#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000287
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288/* Common SPI functions */
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100289
290static int find_opcode(OPCODES *op, uint8_t opcode)
291{
292 int a;
293
294 if (op == NULL) {
295 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
296 return -1;
297 }
298
299 for (a = 0; a < 8; a++) {
300 if (op->opcode[a].opcode == opcode)
301 return a;
302 }
303
304 return -1;
305}
306
307static int find_preop(OPCODES *op, uint8_t preop)
308{
309 int a;
310
311 if (op == NULL) {
312 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
313 return -1;
314 }
315
316 for (a = 0; a < 2; a++) {
317 if (op->preop[a] == preop)
318 return a;
319 }
320
321 return -1;
322}
Dominik Geyerb46acba2008-05-16 12:55:55 +0000323
FENG yu ningf041e9b2008-12-15 02:32:11 +0000324/* for pairing opcodes with their required preop */
325struct preop_opcode_pair {
326 uint8_t preop;
327 uint8_t opcode;
328};
329
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000330/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000331const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000332 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
333 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
334 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
335 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
336 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
337 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000338 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
339 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000340 {JEDEC_EWSR, JEDEC_WRSR},
341 {0,}
342};
343
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000344/* Reasonable default configuration. Needs ad-hoc modifications if we
345 * encounter unlisted opcodes. Fun.
346 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000347static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000348 {
349 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000350 JEDEC_EWSR,
351 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000352 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000353 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000354 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
David Hendricks15f539c2010-08-26 21:27:17 -0700355 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000356 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000357 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000358 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000359 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000360 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
361 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000362};
363
Helge Wagner738e2522010-10-05 22:06:05 +0000364/* List of opcodes with their corresponding spi_type
365 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
366 * is needed which is currently not in the chipset OPCODE table
367 */
368static OPCODE POSSIBLE_OPCODES[] = {
369 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
370 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
371 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
372 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
373 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
374 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
375 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
376 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
377 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
378 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
379 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
380};
381
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000382static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000383
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000384/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000385static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000386{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000387 OPCODE oc;
388 const char *t;
389 const char *a;
390 uint8_t i;
391 static const char *const spi_type[4] = {
392 "read w/o addr",
393 "write w/o addr",
394 "read w/ addr",
395 "write w/ addr"
396 };
397 static const char *const atomic_type[3] = {
398 "none",
399 " 0 ",
400 " 1 "
401 };
402
403 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000404 return;
405
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000406 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000407 for (i = 0; i < 8; i++) {
408 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000409 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
410 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
411 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000412 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000413 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
414 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000415}
416
Nico Huberd54e4f42017-03-23 23:45:47 +0100417#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
418#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000419
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +1000420static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen)
Stefan Tauner55206942011-06-11 09:53:22 +0000421{
422 msg_pdbg("HSFS: ");
423 pprint_reg(HSFS, FDONE, reg_val, ", ");
424 pprint_reg(HSFS, FCERR, reg_val, ", ");
425 pprint_reg(HSFS, AEL, reg_val, ", ");
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +1000426 switch (ich_gen) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200427 case CHIPSET_100_SERIES_SUNRISE_POINT:
428 case CHIPSET_C620_SERIES_LEWISBURG:
429 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500430 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200431 break;
432 default:
Nico Huberd54e4f42017-03-23 23:45:47 +0100433 pprint_reg(HSFS, BERASE, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200434 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100435 }
Stefan Tauner55206942011-06-11 09:53:22 +0000436 pprint_reg(HSFS, SCIP, reg_val, ", ");
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +1000437 switch (ich_gen) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200438 case CHIPSET_100_SERIES_SUNRISE_POINT:
439 case CHIPSET_C620_SERIES_LEWISBURG:
440 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500441 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huberd54e4f42017-03-23 23:45:47 +0100442 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
443 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200444 break;
445 default:
446 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100447 }
Stefan Tauner55206942011-06-11 09:53:22 +0000448 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
449 pprint_reg(HSFS, FDV, reg_val, ", ");
450 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
451}
452
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +1000453static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen)
Stefan Tauner55206942011-06-11 09:53:22 +0000454{
455 msg_pdbg("HSFC: ");
456 pprint_reg(HSFC, FGO, reg_val, ", ");
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +1000457 switch (ich_gen) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200458 case CHIPSET_100_SERIES_SUNRISE_POINT:
459 case CHIPSET_C620_SERIES_LEWISBURG:
460 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500461 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huberd54e4f42017-03-23 23:45:47 +0100462 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
463 pprint_reg(HSFC, WET, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200464 break;
465 default:
466 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
467 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100468 }
Stefan Tauner55206942011-06-11 09:53:22 +0000469 pprint_reg(HSFC, FDBC, reg_val, ", ");
470 pprint_reg(HSFC, SME, reg_val, "\n");
471}
472
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000473static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
474{
475 msg_pdbg("SSFS: ");
476 pprint_reg(SSFS, SCIP, reg_val, ", ");
477 pprint_reg(SSFS, FDONE, reg_val, ", ");
478 pprint_reg(SSFS, FCERR, reg_val, ", ");
479 pprint_reg(SSFS, AEL, reg_val, "\n");
480}
481
482static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
483{
484 msg_pdbg("SSFC: ");
485 pprint_reg(SSFC, SCGO, reg_val, ", ");
486 pprint_reg(SSFC, ACS, reg_val, ", ");
487 pprint_reg(SSFC, SPOP, reg_val, ", ");
488 pprint_reg(SSFC, COP, reg_val, ", ");
489 pprint_reg(SSFC, DBC, reg_val, ", ");
490 pprint_reg(SSFC, SME, reg_val, ", ");
491 pprint_reg(SSFC, SCF, reg_val, "\n");
492}
493
Nico Huberd54e4f42017-03-23 23:45:47 +0100494static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
495{
496 msg_pdbg("DLOCK: ");
497 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
498 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
499 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
500 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
501 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
502 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
503 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
504 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
505 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
506 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
507}
508
509static struct {
510 size_t reg_ssfsc;
511 size_t reg_preop;
512 size_t reg_optype;
513 size_t reg_opmenu;
514} swseq_data;
515
Helge Wagner738e2522010-10-05 22:06:05 +0000516static uint8_t lookup_spi_type(uint8_t opcode)
517{
Nico Huber519be662018-12-23 20:03:35 +0100518 unsigned int a;
Helge Wagner738e2522010-10-05 22:06:05 +0000519
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000520 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000521 if (POSSIBLE_OPCODES[a].opcode == opcode)
522 return POSSIBLE_OPCODES[a].spi_type;
523 }
524
525 return 0xFF;
526}
527
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +1000528static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_gen)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000529{
530 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000531 uint16_t preop, optype;
532 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000533
534 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000535 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000536 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000537 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000538 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000539
Stefan Reinauera9424d52008-06-27 16:28:34 +0000540 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000541 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000542 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000543 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000544 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000545
Stefan Reinauera9424d52008-06-27 16:28:34 +0000546 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000547 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000548 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000549 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000550 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000551
Stefan Tauner92d6a862013-10-25 00:33:37 +0000552 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000553 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000554 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000555 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000556 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000557
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000558 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +1000559 switch (ich_gen) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000560 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000561 case CHIPSET_TUNNEL_CREEK:
562 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000563 /* Register undo only for enable_undo=1, i.e. first call. */
564 if (enable_undo) {
565 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
566 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
567 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
568 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
569 }
570 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
571 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
572 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
573 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000574 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000575 case CHIPSET_ICH8:
576 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000577 /* Register undo only for enable_undo=1, i.e. first call. */
578 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100579 rmmio_valw(ich_spibar + swseq_data.reg_preop);
580 rmmio_valw(ich_spibar + swseq_data.reg_optype);
581 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
582 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000583 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100584 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
585 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
586 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
587 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000588 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000589 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000590
591 return 0;
592}
593
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100594static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
595{
596 uint8_t spi_type;
597
598 spi_type = lookup_spi_type(opcode);
599 if (spi_type > 3) {
600 /* Try to guess spi type from read/write sizes.
601 * The following valid writecnt/readcnt combinations exist:
602 * writecnt = 4, readcnt >= 0
603 * writecnt = 1, readcnt >= 0
604 * writecnt >= 4, readcnt = 0
605 * writecnt >= 1, readcnt = 0
606 * writecnt >= 1 is guaranteed for all commands.
607 */
608 if (readcnt == 0)
609 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
610 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
611 * bytes are actual the address, they go to the bus anyhow
612 */
613 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
614 else if (writecnt == 1) // and readcnt is > 0
615 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
616 else if (writecnt == 4) // and readcnt is > 0
617 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
618 else // we have an invalid case
619 return SPI_INVALID_LENGTH;
620 }
621 int oppos = 2; // use original JEDEC_BE_D8 offset
622 curopcodes->opcode[oppos].opcode = opcode;
623 curopcodes->opcode[oppos].spi_type = spi_type;
624 program_opcodes(curopcodes, 0, ich_generation);
625 oppos = find_opcode(curopcodes, opcode);
626 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
627 return oppos;
628}
629
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000630/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000631 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
632 * FIXME: this should also check for
633 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
634 * - at least one erasing opcode (lots.)
635 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
636 * - necessary preops? (EWSR, WREN, ...?)
637 */
Richard Hughes93e16252018-12-19 11:54:47 +0000638static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000639{
640 uint8_t ops[] = {
641 JEDEC_READ,
642 JEDEC_RDSR,
643 0
644 };
645 int i = 0;
646 while (ops[i] != 0) {
647 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
648 if (find_opcode(curopcodes, ops[i]) == -1)
649 return -1;
650 i++;
651 }
652 return 0;
653}
654
655/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000656 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
657 * it didn't stick.
658 */
Edward O'Callaghan4c9b4162020-07-16 15:37:26 +1000659static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000660{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000661 int bbar_off;
Edward O'Callaghan4c9b4162020-07-16 15:37:26 +1000662 switch (ich_gen) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000663 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000664 case CHIPSET_TUNNEL_CREEK:
665 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000666 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000667 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000668 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000669 case CHIPSET_BAYTRAIL:
670 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000671 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000672 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000673 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000674 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000675 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000676 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200677
Stefan Taunere27b2d42011-07-01 00:39:09 +0000678 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
679 if (ichspi_bbar) {
680 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
681 ichspi_bbar);
682 }
683 min_addr &= BBAR_MASK;
684 ichspi_bbar |= min_addr;
685 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
686 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
687
688 /* We don't have any option except complaining. And if the write
689 * failed, the restore will fail as well, so no problem there.
690 */
691 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000692 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
693 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000694}
695
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100696/* Create a struct OPCODES based on what we find in the locked down chipset. */
697static int generate_opcodes(OPCODES * op, enum ich_chipset ich_gen)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200698{
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100699 int a;
700 uint16_t preop, optype;
701 uint32_t opmenu[2];
Stefan Tauner8b391b82011-08-09 01:49:34 +0000702
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100703 if (op == NULL) {
704 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
705 return -1;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000706 }
Stefan Tauner8b391b82011-08-09 01:49:34 +0000707
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100708 switch (ich_gen) {
709 case CHIPSET_ICH7:
710 case CHIPSET_TUNNEL_CREEK:
711 case CHIPSET_CENTERTON:
712 preop = REGREAD16(ICH7_REG_PREOP);
713 optype = REGREAD16(ICH7_REG_OPTYPE);
714 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
715 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
716 break;
717 case CHIPSET_ICH8:
718 default: /* Future version might behave the same */
719 preop = REGREAD16(swseq_data.reg_preop);
720 optype = REGREAD16(swseq_data.reg_optype);
721 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
722 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
723 break;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000724 }
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100725
726 op->preop[0] = (uint8_t) preop;
727 op->preop[1] = (uint8_t) (preop >> 8);
728
729 for (a = 0; a < 8; a++) {
730 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
731 optype >>= 2;
732 }
733
734 for (a = 0; a < 4; a++) {
735 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
736 opmenu[0] >>= 8;
737 }
738
739 for (a = 4; a < 8; a++) {
740 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
741 opmenu[1] >>= 8;
742 }
743
744 /* No preopcodes used by default. */
745 for (a = 0; a < 8; a++)
746 op->opcode[a].atomic = 0;
747
748 return 0;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000749}
750
FENG yu ningf041e9b2008-12-15 02:32:11 +0000751/* This function generates OPCODES from or programs OPCODES to ICH according to
752 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000753 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000754 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000755 */
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +1000756static int ich_init_opcodes(enum ich_chipset ich_gen)
FENG yu ningc05a2952008-12-08 18:16:58 +0000757{
758 int rc = 0;
759 OPCODES *curopcodes_done;
760
761 if (curopcodes)
762 return 0;
763
764 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000765 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000766 curopcodes_done = &O_EXISTING;
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +1000767 rc = generate_opcodes(curopcodes_done, ich_gen);
FENG yu ningc05a2952008-12-08 18:16:58 +0000768 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000769 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000770 curopcodes_done = &O_ST_M25P;
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +1000771 rc = program_opcodes(curopcodes_done, 1, ich_gen);
FENG yu ningc05a2952008-12-08 18:16:58 +0000772 }
773
774 if (rc) {
775 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000776 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000777 return 1;
778 } else {
779 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000780 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000781 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000782 return 0;
783 }
784}
785
Anastasia Klimchukf1391c72021-02-15 15:04:20 +1100786/* Fill len bytes from the data array into the fdata/spid registers.
787 *
788 * Note that using len > flash->mst->spi.max_data_write will trash the registers
789 * following the data registers.
790 */
791static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
792{
793 uint32_t temp32 = 0;
794 int i;
795
796 if (len <= 0)
797 return;
798
799 for (i = 0; i < len; i++) {
800 if ((i % 4) == 0)
801 temp32 = 0;
802
803 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
804
805 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
806 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
807 }
808 i--;
809 if ((i % 4) != 3) /* Write remaining data to regs. */
810 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
811}
812
813/* Read len bytes from the fdata/spid register into the data array.
814 *
815 * Note that using len > flash->mst->spi.max_data_read will return garbage or
816 * may even crash.
817 */
818static void ich_read_data(uint8_t *data, int len, int reg0_off)
819{
820 int i;
821 uint32_t temp32 = 0;
822
823 for (i = 0; i < len; i++) {
824 if ((i % 4) == 0)
825 temp32 = REGREAD32(reg0_off + i);
826
827 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
828 }
829}
830
Stefan Reinauer43119562008-11-02 19:51:50 +0000831static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000832 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000833{
834 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000835 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000836 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000837 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000838 uint64_t opmenu;
839 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000840
841 /* Is it a write command? */
842 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
843 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
844 write_cmd = 1;
845 }
846
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000847 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
848 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
849 programmer_delay(10);
850 }
851 if (!timeout) {
852 msg_perr("Error: SCIP never cleared!\n");
853 return 1;
854 }
855
Stefan Tauner10b3e222011-07-01 00:39:23 +0000856 /* Program offset in flash into SPIA while preserving reserved bits. */
857 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
858 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000859
Stefan Tauner10b3e222011-07-01 00:39:23 +0000860 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000861 if (write_cmd && (datalength != 0))
862 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000863
864 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000865 temp16 = REGREAD16(ICH7_REG_SPIS);
866 /* keep reserved bits */
867 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000868 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000869 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000870 REGWRITE16(ICH7_REG_SPIS, temp16);
871
872 /* Assemble SPIC */
873 temp16 = 0;
874
875 if (datalength != 0) {
876 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000877 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000878 }
879
880 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000881 opmenu = REGREAD32(ICH7_REG_OPMENU);
882 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
883
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000884 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
885 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000886 break;
887 }
888 opmenu >>= 8;
889 }
890 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000891 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000892 return 1;
893 }
894 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000895
Michael Karcher136125a2011-04-29 22:11:36 +0000896 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
897 /* Handle Atomic. Atomic commands include three steps:
898 - sending the preop (mainly EWSR or WREN)
899 - sending the main command
900 - waiting for the busy bit (WIP) to be cleared
901 This means the timeout must be sufficient for chip erase
902 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000903 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000904 switch (op.atomic) {
905 case 2:
906 /* Select second preop. */
907 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000908 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000909 case 1:
910 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000911 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000912 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000913 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000914 }
915
916 /* Start */
917 temp16 |= SPIC_SCGO;
918
919 /* write it */
920 REGWRITE16(ICH7_REG_SPIC, temp16);
921
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000922 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000923 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
924 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000925 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000926 }
927 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000928 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
929 REGREAD16(ICH7_REG_SPIS));
930 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000931 }
932
Sean Nelson316a29f2010-05-07 20:09:04 +0000933 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000934 temp16 = REGREAD16(ICH7_REG_SPIS);
935 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000936 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000937 /* keep reserved bits */
938 temp16 &= SPIS_RESERVED_MASK;
939 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000940 return 1;
941 }
942
Stefan Tauner8b391b82011-08-09 01:49:34 +0000943 if ((!write_cmd) && (datalength != 0))
944 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000945
946 return 0;
947}
948
Stefan Reinauer43119562008-11-02 19:51:50 +0000949static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000950 uint8_t datalength, uint8_t * data)
951{
952 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000953 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000954 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000955 uint64_t opmenu;
956 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000957
958 /* Is it a write command? */
959 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
960 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
961 write_cmd = 1;
962 }
963
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000964 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100965 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000966 programmer_delay(10);
967 }
968 if (!timeout) {
969 msg_perr("Error: SCIP never cleared!\n");
970 return 1;
971 }
972
Stefan Tauner10b3e222011-07-01 00:39:23 +0000973 /* Program offset in flash into FADDR while preserve the reserved bits
974 * and clearing the 25. address bit which is only useable in hwseq. */
975 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
976 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000977
978 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000979 if (write_cmd && (datalength != 0))
980 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000981
982 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100983 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000984 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000985 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000986 /* Clear cycle done and cycle error status registers */
987 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100988 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000989
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000990 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000991 temp32 |= SSFC_SCF_20MHZ;
992
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000993 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000994 if (datalength != 0) {
995 uint32_t datatemp;
996 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000997 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
998 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000999 temp32 |= datatemp;
1000 }
1001
1002 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +02001003 opmenu = REGREAD32(swseq_data.reg_opmenu);
1004 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +00001005
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001006 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
1007 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +00001008 break;
1009 }
1010 opmenu >>= 8;
1011 }
1012 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001013 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001014 return 1;
1015 }
1016 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001017
Michael Karcher136125a2011-04-29 22:11:36 +00001018 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1019 /* Handle Atomic. Atomic commands include three steps:
1020 - sending the preop (mainly EWSR or WREN)
1021 - sending the main command
1022 - waiting for the busy bit (WIP) to be cleared
1023 This means the timeout must be sufficient for chip erase
1024 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001025 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001026 switch (op.atomic) {
1027 case 2:
1028 /* Select second preop. */
1029 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001030 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001031 case 1:
1032 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001033 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001034 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001035 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001036 }
1037
1038 /* Start */
1039 temp32 |= SSFC_SCGO;
1040
1041 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001042 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001043
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001044 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001045 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001046 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001047 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001048 }
1049 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001050 msg_perr("timeout, REG_SSFS=0x%08x\n",
1051 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001052 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001053 }
1054
Sean Nelson316a29f2010-05-07 20:09:04 +00001055 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001056 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001057 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001058 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001059 prettyprint_ich9_reg_ssfs(temp32);
1060 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001061 /* keep reserved bits */
1062 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1063 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001064 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001065 return 1;
1066 }
1067
Stefan Tauner8b391b82011-08-09 01:49:34 +00001068 if ((!write_cmd) && (datalength != 0))
1069 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001070
1071 return 0;
1072}
1073
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001074static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001075 uint8_t datalength, uint8_t * data)
1076{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001077 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001078 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001079
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001080 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001081 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001082 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001083 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001084
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001085 if (datalength > maxlength) {
1086 msg_perr("%s: Internal command size error for "
1087 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1088 __func__, op.opcode, datalength, maxlength);
1089 return SPI_INVALID_LENGTH;
1090 }
1091
Stefan Taunera8d838d2011-11-06 23:51:09 +00001092 switch (ich_generation) {
1093 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001094 case CHIPSET_TUNNEL_CREEK:
1095 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001096 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001097 case CHIPSET_ICH8:
1098 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001099 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001100 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001101}
1102
Edward O'Callaghane4ddc362020-04-12 17:27:53 +10001103static int ich_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001104 unsigned int readcnt,
1105 const unsigned char *writearr,
1106 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001107{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001108 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001109 int opcode_index = -1;
1110 const unsigned char cmd = *writearr;
1111 OPCODE *opcode;
1112 uint32_t addr = 0;
1113 uint8_t *data;
1114 int count;
1115
Dominik Geyerb46acba2008-05-16 12:55:55 +00001116 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001117 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001118 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001119 if (!ichspi_lock)
1120 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001121 if (opcode_index == SPI_INVALID_LENGTH) {
1122 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1123 return SPI_INVALID_LENGTH;
1124 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001125 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1126 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001127 return SPI_INVALID_OPCODE;
1128 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001129 }
1130
1131 opcode = &(curopcodes->opcode[opcode_index]);
1132
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001133 /* The following valid writecnt/readcnt combinations exist:
1134 * writecnt = 4, readcnt >= 0
1135 * writecnt = 1, readcnt >= 0
1136 * writecnt >= 4, readcnt = 0
1137 * writecnt >= 1, readcnt = 0
1138 * writecnt >= 1 is guaranteed for all commands.
1139 */
1140 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1141 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001142 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001143 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1144 writecnt);
1145 return SPI_INVALID_LENGTH;
1146 }
1147 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1148 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001149 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001150 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1151 writecnt);
1152 return SPI_INVALID_LENGTH;
1153 }
1154 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1155 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001156 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001157 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1158 writecnt);
1159 return SPI_INVALID_LENGTH;
1160 }
1161 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1162 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1163 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001164 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001165 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1166 readcnt);
1167 return SPI_INVALID_LENGTH;
1168 }
1169
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001170 /* Translate read/write array/count.
1171 * The maximum data length is identical for the maximum read length and
1172 * for the maximum write length excluding opcode and address. Opcode and
1173 * address are stored in separate registers, not in the data registers
1174 * and are thus not counted towards data length. The only exception
1175 * applies if the opcode definition (un)intentionally classifies said
1176 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001177 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001178 data = (uint8_t *) (writearr + 1);
1179 count = writecnt - 1;
1180 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1181 data = (uint8_t *) (writearr + 4);
1182 count = writecnt - 4;
1183 } else {
1184 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001185 count = readcnt;
1186 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001187
Nico Hubered098d62017-04-21 23:47:08 +02001188 /* if opcode-type requires an address */
1189 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1190 addr = ichspi_bbar;
1191 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1192 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1193 /* BBAR may cut part of the chip off at the lower end. */
1194 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1195 const uint32_t addr_offset = ichspi_bbar - valid_base;
1196 /* Highest address we can program is (2^24 - 1). */
1197 const uint32_t valid_end = (1 << 24) - addr_offset;
1198
1199 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1200 const uint32_t addr_end = addr + count;
1201
1202 if (addr < valid_base ||
1203 addr_end < addr || /* integer overflow check */
1204 addr_end > valid_end) {
1205 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1206 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1207 return SPI_INVALID_ADDRESS;
1208 }
1209 addr += addr_offset;
1210 }
1211
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001212 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001213 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001214 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1215 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1216 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1217 msg_pdbg("at address 0x%06x ", addr);
1218 }
1219 msg_pdbg("(payload length was %d).\n", count);
1220
1221 /* Print out the data array if it contains data to write.
1222 * Errors are detected before the received data is read back into
1223 * the array so it won't make sense to print it then. */
1224 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1225 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1226 int i;
1227 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001228 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001229 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1230 }
1231 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001232 }
1233
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001234 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001235}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001236
Stefan Tauner50e7c602011-11-08 10:55:54 +00001237static struct hwseq_data {
1238 uint32_t size_comp0;
1239 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001240 uint32_t addr_mask;
1241 bool only_4k;
1242 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001243} hwseq_data;
1244
Nico Huberd54e4f42017-03-23 23:45:47 +01001245/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001246static void ich_hwseq_set_addr(uint32_t addr)
1247{
Nico Huberd54e4f42017-03-23 23:45:47 +01001248 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1249 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001250}
1251
1252/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1253 * of the block containing this address. May return nonsense if the address is
1254 * not valid. The erase block size for a specific address depends on the flash
1255 * partition layout as specified by FPB and the partition properties as defined
1256 * by UVSCC and LVSCC respectively. An alternative to implement this method
1257 * would be by querying FPB and the respective VSCC register directly.
1258 */
1259static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1260{
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001261 uint8_t enc_berase;
1262 static const uint32_t dec_berase[4] = {
1263 256,
1264 4 * 1024,
1265 8 * 1024,
1266 64 * 1024
1267 };
1268
Nico Huberd54e4f42017-03-23 23:45:47 +01001269 if (hwseq_data.only_4k) {
1270 return 4 * 1024;
Nico Huberd54e4f42017-03-23 23:45:47 +01001271 }
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001272
1273 ich_hwseq_set_addr(addr);
1274 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1275 return dec_berase[enc_berase];
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001276}
1277
1278/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1279 Resets all error flags in HSFS.
1280 Returns 0 if the cycle completes successfully without errors within
1281 timeout us, 1 on errors. */
1282static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001283 unsigned int len,
1284 enum ich_chipset ich_gen)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001285{
1286 uint16_t hsfs;
1287 uint32_t addr;
1288
1289 timeout /= 8; /* scale timeout duration to counter */
1290 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1291 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1292 --timeout) {
1293 programmer_delay(8);
1294 }
1295 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1296 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001297 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001298 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001299 "0x%08x (= 0x%08x + %d)!\n",
1300 addr, addr + len - 1, addr, len - 1);
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001301 prettyprint_ich9_reg_hsfs(hsfs, ich_gen);
1302 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001303 return 1;
1304 }
1305
1306 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001307 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001308 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001309 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001310 addr, addr + len - 1, addr, len - 1);
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001311 prettyprint_ich9_reg_hsfs(hsfs, ich_gen);
1312 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001313 return 1;
1314 }
1315 return 0;
1316}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001317
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001318static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001319{
1320 uint32_t total_size, boundary;
1321 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1322 struct block_eraser *eraser;
1323
1324 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001325 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001326 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1327 if (hwseq_data.size_comp1 != 0)
1328 msg_cdbg("s with a combined");
1329 else
1330 msg_cdbg(" with a");
1331 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001332 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001333
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001334 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001335 if (!hwseq_data.only_4k)
1336 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1337 else
1338 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001339 size_high = total_size - boundary;
1340 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1341
1342 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001343 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001344 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1345 eraser->eraseblocks[0].size = erase_size_high;
1346 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001347 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001348 size_high / erase_size_high, erase_size_high);
1349 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001350 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001351 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001352 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001353 size_low = total_size - size_high;
1354 erase_size_low = ich_hwseq_get_erase_block_size(0);
1355
1356 eraser->eraseblocks[0].size = erase_size_low;
1357 eraser->eraseblocks[0].count = size_low / erase_size_low;
1358 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1359 0, size_low-1);
1360 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1361 size_low / erase_size_low, erase_size_low);
1362
1363 eraser->eraseblocks[1].size = erase_size_high;
1364 eraser->eraseblocks[1].count = size_high / erase_size_high;
1365 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001366 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001367 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1368 size_high / erase_size_high, erase_size_high);
1369 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001370 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001371 return 1;
1372}
1373
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001374static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1375 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001376{
1377 uint32_t erase_block;
1378 uint16_t hsfc;
1379 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1380
1381 erase_block = ich_hwseq_get_erase_block_size(addr);
1382 if (len != erase_block) {
1383 msg_cerr("Erase block size for address 0x%06x is %d B, "
1384 "but requested erase block size is %d B. "
1385 "Not erasing anything.\n", addr, erase_block, len);
1386 return -1;
1387 }
1388
1389 /* Although the hardware supports this (it would erase the whole block
1390 * containing the address) we play safe here. */
1391 if (addr % erase_block != 0) {
1392 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1393 "block boundary (any multiple of %d). "
1394 "Not erasing anything.\n", addr, erase_block);
1395 return -1;
1396 }
1397
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001398 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001399 msg_perr("Request to erase some inaccessible memory address(es)"
1400 " (addr=0x%x, len=%d). "
1401 "Not erasing anything.\n", addr, len);
1402 return -1;
1403 }
1404
1405 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001406 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001407
1408 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1409 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1410
1411 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001412 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001413 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1414 hsfc |= HSFC_FGO; /* start */
1415 msg_pdbg("HSFC used for block erasing: ");
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001416 prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001417 REGWRITE16(ICH9_REG_HSFC, hsfc);
1418
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001419 if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001420 return -1;
1421 return 0;
1422}
1423
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001424static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1425 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001426{
1427 uint16_t hsfc;
1428 uint16_t timeout = 100 * 60;
1429 uint8_t block_len;
1430
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001431 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001432 msg_perr("Request to read from an inaccessible memory address "
1433 "(addr=0x%x, len=%d).\n", addr, len);
1434 return -1;
1435 }
1436
1437 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1438 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1439 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1440
1441 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001442 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001443 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001444 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1445 block_len = min(block_len, 256 - (addr & 0xFF));
1446
Stefan Tauner50e7c602011-11-08 10:55:54 +00001447 ich_hwseq_set_addr(addr);
1448 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001449 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001450 hsfc &= ~HSFC_FDBC; /* clear byte count */
1451 /* set byte count */
1452 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1453 hsfc |= HSFC_FGO; /* start */
1454 REGWRITE16(ICH9_REG_HSFC, hsfc);
1455
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001456 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001457 return 1;
1458 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1459 addr += block_len;
1460 buf += block_len;
1461 len -= block_len;
1462 }
1463 return 0;
1464}
1465
Mark Marshallf20b7be2014-05-09 21:16:21 +00001466static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001467{
1468 uint16_t hsfc;
1469 uint16_t timeout = 100 * 60;
1470 uint8_t block_len;
1471
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001472 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001473 msg_perr("Request to write to an inaccessible memory address "
1474 "(addr=0x%x, len=%d).\n", addr, len);
1475 return -1;
1476 }
1477
1478 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1479 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1480 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1481
1482 while (len > 0) {
1483 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001484 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001485 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001486 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1487 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001488 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1489 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001490 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001491 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1492 hsfc &= ~HSFC_FDBC; /* clear byte count */
1493 /* set byte count */
1494 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1495 hsfc |= HSFC_FGO; /* start */
1496 REGWRITE16(ICH9_REG_HSFC, hsfc);
1497
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001498 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001499 return -1;
1500 addr += block_len;
1501 buf += block_len;
1502 len -= block_len;
1503 }
1504 return 0;
1505}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001506
Edward O'Callaghane4ddc362020-04-12 17:27:53 +10001507static int ich_spi_send_multicommand(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001508 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001509{
1510 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001511 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001512 int oppos, preoppos;
1513 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001514 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001515 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001516 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1517 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001518 if ((oppos == -1) && (preoppos != -1)) {
1519 /* Current command is listed as preopcode in
1520 * ICH struct OPCODES, but next command is not
1521 * listed as opcode in that struct.
1522 * Check for command sanity, then
1523 * try to reprogram the ICH opcode list.
1524 */
1525 if (find_preop(curopcodes,
1526 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001527 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001528 "preopcodes 0x%02x and 0x%02x, "
1529 "ignoring the first.\n",
1530 __func__, cmds->writearr[0],
1531 (cmds + 1)->writearr[0]);
1532 continue;
1533 }
1534 /* If the chipset is locked down, we'll fail
1535 * during execution of the next command anyway.
1536 * No need to bother with fixups.
1537 */
1538 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001539 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1540 if (oppos == -1)
1541 continue;
1542 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001543 continue;
1544 }
1545 }
1546 if ((oppos != -1) && (preoppos != -1)) {
1547 /* Current command is listed as preopcode in
1548 * ICH struct OPCODES and next command is listed
1549 * as opcode in that struct. Match them up.
1550 */
1551 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001552 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001553 }
1554 /* If none of the above if-statements about oppos or
1555 * preoppos matched, this is a normal opcode.
1556 */
1557 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001558 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001559 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001560 /* Reset the type of all opcodes to non-atomic. */
1561 for (i = 0; i < 8; i++)
1562 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001563 }
1564 return ret;
1565}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001566
Michael Karchera4448d92010-07-22 18:04:15 +00001567#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1568#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1569#define ICH_BRWA(x) ((x >> 8) & 0xff)
1570#define ICH_BRRA(x) ((x >> 0) & 0xff)
1571
Nico Huber7590d1a2016-05-03 13:38:28 +02001572static const enum ich_access_protection access_perms_to_protection[] = {
1573 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1574};
1575static const char *const access_names[] = {
1576 "locked", "read-only", "write-only", "read-write"
1577};
1578
Nico Huber519be662018-12-23 20:03:35 +01001579static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001580{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001581 const int rwperms_unknown = ARRAY_SIZE(access_names);
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001582 static const char *const region_names[] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001583 "Flash Descriptor", "BIOS", "Management Engine",
Nico Huberd2d39932019-01-18 16:49:37 +01001584 "Gigabit Ethernet", "Platform Data", "Device Expansion",
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001585 "BIOS2", "unknown", "EC/BMC",
Michael Karchera4448d92010-07-22 18:04:15 +00001586 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001587 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1588
Michael Karchera4448d92010-07-22 18:04:15 +00001589 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001590 int rwperms;
Nico Huberd2d39932019-01-18 16:49:37 +01001591 const int offset = i < 12
1592 ? ICH9_REG_FREG0 + i * 4
1593 : APL_REG_FREG12 + (i - 12) * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001594 uint32_t freg = mmio_readl(ich_spibar + offset);
1595
Nico Huberaa91d5c2017-08-19 17:04:21 +02001596 if (i < 8) {
1597 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1598 (((ICH_BRRA(frap) >> i) & 1) << 0);
1599 } else {
1600 /* Datasheets don't define any access bits for regions > 7. We
1601 can't rely on the actual descriptor settings either as there
1602 are several overrides for them (those by other masters are
1603 not even readable by us, *shrug*). */
1604 rwperms = rwperms_unknown;
1605 }
1606
Michael Karchera4448d92010-07-22 18:04:15 +00001607 base = ICH_FREG_BASE(freg);
1608 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001609 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001610 /* this FREG is disabled */
Nico Huber519be662018-12-23 20:03:35 +01001611 msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001612 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001613 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001614 }
1615 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1616 if (rwperms == 0x3) {
Nico Huber519be662018-12-23 20:03:35 +01001617 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001618 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001619 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001620 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001621 if (rwperms == rwperms_unknown) {
Nico Huber519be662018-12-23 20:03:35 +01001622 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n",
Nico Huberaa91d5c2017-08-19 17:04:21 +02001623 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001624 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001625 }
Michael Karchera4448d92010-07-22 18:04:15 +00001626
Nico Huber519be662018-12-23 20:03:35 +01001627 msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001628 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001629 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001630}
1631
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001632 /* In contrast to FRAP and the master section of the descriptor the bits
1633 * in the PR registers have an inverted meaning. The bits in FRAP
1634 * indicate read and write access _grant_. Here they indicate read
1635 * and write _protection_ respectively. If both bits are 0 the address
1636 * bits are ignored.
1637 */
1638#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1639 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1640
Nico Huber519be662018-12-23 20:03:35 +01001641static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001642{
Nico Huberd54e4f42017-03-23 23:45:47 +01001643 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001644 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001645 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001646
Nico Huberd54e4f42017-03-23 23:45:47 +01001647 /* From 5 on we have GPR registers and start from 0 again. */
1648 const char *const prefix = i >= 5 ? "G" : "";
1649 if (i >= 5)
1650 i -= 5;
1651
Stefan Tauner5210e722012-02-16 01:13:00 +00001652 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001653 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001654 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001655 }
1656
1657 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001658 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001659 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001660 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001661}
1662
Stefan Tauner75da80c2011-09-17 22:21:55 +00001663/* Set/Clear the read and write protection enable bits of PR register @i
1664 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001665static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001666{
Nico Huberd54e4f42017-03-23 23:45:47 +01001667 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001668 uint32_t old = mmio_readl(addr);
1669 uint32_t new;
1670
1671 msg_gspew("PR%u is 0x%08x", i, old);
1672 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1673 if (read_prot)
1674 new |= (1 << PR_RP_OFF);
1675 if (write_prot)
1676 new |= (1 << PR_WP_OFF);
1677 if (old == new) {
1678 msg_gspew(" already.\n");
1679 return;
1680 }
1681 msg_gspew(", trying to set it to 0x%08x ", new);
1682 rmmio_writel(new, addr);
1683 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1684}
1685
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001686static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001687 .max_data_read = 64,
1688 .max_data_write = 64,
1689 .command = ich_spi_send_command,
1690 .multicommand = ich_spi_send_multicommand,
1691 .read = default_spi_read,
1692 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001693 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001694};
1695
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001696static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001697 .max_data_read = 64,
1698 .max_data_write = 64,
1699 .command = ich_spi_send_command,
1700 .multicommand = ich_spi_send_multicommand,
1701 .read = default_spi_read,
1702 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001703 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001704};
1705
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001706static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001707 .max_data_read = 64,
1708 .max_data_write = 64,
1709 .probe = ich_hwseq_probe,
1710 .read = ich_hwseq_read,
1711 .write = ich_hwseq_write,
1712 .erase = ich_hwseq_block_erase,
1713};
1714
Nico Huber560111e2017-04-26 12:27:17 +02001715int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001716{
Nico Huber519be662018-12-23 20:03:35 +01001717 unsigned int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001718 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001719 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001720 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001721 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001722 int desc_valid = 0;
Richard Hughese2cbb122019-01-02 21:11:08 +00001723 struct ich_descriptors desc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001724 enum ich_spi_mode {
1725 ich_auto,
1726 ich_hwseq,
1727 ich_swseq
1728 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001729 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001730
Stefan Taunera8d838d2011-11-06 23:51:09 +00001731 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001732 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001733
Richard Hughese2cbb122019-01-02 21:11:08 +00001734 memset(&desc, 0x00, sizeof(struct ich_descriptors));
1735
Nico Huberd54e4f42017-03-23 23:45:47 +01001736 /* Moving registers / bits */
Edward O'Callaghan2ffc1e42020-07-16 15:25:37 +10001737 switch (ich_gen) {
Nico Huberd2d39932019-01-18 16:49:37 +01001738 case CHIPSET_100_SERIES_SUNRISE_POINT:
1739 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001740 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -05001741 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001742 case CHIPSET_APOLLO_LAKE:
Angel Pons11a35982020-07-10 17:04:10 +02001743 case CHIPSET_GEMINI_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -07001744 num_pr = 6; /* Includes GPR0 */
1745 reg_pr0 = PCH100_REG_FPR0;
1746 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1747 swseq_data.reg_preop = PCH100_REG_PREOP;
1748 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1749 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1750 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1751 hwseq_data.only_4k = true;
1752 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001753 break;
1754 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001755 num_pr = 5;
1756 reg_pr0 = ICH9_REG_PR0;
1757 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1758 swseq_data.reg_preop = ICH9_REG_PREOP;
1759 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1760 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1761 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1762 hwseq_data.only_4k = false;
1763 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001764 break;
1765 }
Edward O'Callaghan2ffc1e42020-07-16 15:25:37 +10001766 switch (ich_gen) {
Nico Huberd2d39932019-01-18 16:49:37 +01001767 case CHIPSET_100_SERIES_SUNRISE_POINT:
1768 num_freg = 10;
1769 break;
1770 case CHIPSET_C620_SERIES_LEWISBURG:
1771 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1772 break;
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001773 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -05001774 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001775 case CHIPSET_APOLLO_LAKE:
Angel Pons11a35982020-07-10 17:04:10 +02001776 case CHIPSET_GEMINI_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001777 num_freg = 16;
1778 break;
1779 default:
1780 num_freg = 5;
1781 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001782 }
1783
Edward O'Callaghan2ffc1e42020-07-16 15:25:37 +10001784 switch (ich_gen) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001785 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001786 case CHIPSET_TUNNEL_CREEK:
1787 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001788 msg_pdbg("0x00: 0x%04x (SPIS)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001789 mmio_readw(spibar + 0));
Michael Karchera4448d92010-07-22 18:04:15 +00001790 msg_pdbg("0x02: 0x%04x (SPIC)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001791 mmio_readw(spibar + 2));
Michael Karchera4448d92010-07-22 18:04:15 +00001792 msg_pdbg("0x04: 0x%08x (SPIA)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001793 mmio_readl(spibar + 4));
1794 ichspi_bbar = mmio_readl(spibar + 0x50);
Michael Karchera4448d92010-07-22 18:04:15 +00001795 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1796 ichspi_bbar);
1797 msg_pdbg("0x54: 0x%04x (PREOP)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001798 mmio_readw(spibar + 0x54));
Michael Karchera4448d92010-07-22 18:04:15 +00001799 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001800 mmio_readw(spibar + 0x56));
Michael Karchera4448d92010-07-22 18:04:15 +00001801 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001802 mmio_readl(spibar + 0x58));
Michael Karchera4448d92010-07-22 18:04:15 +00001803 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001804 mmio_readl(spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001805 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001806 int offs;
1807 offs = 0x60 + (i * 4);
Nico Huber519be662018-12-23 20:03:35 +01001808 msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001809 mmio_readl(spibar + offs), i);
Michael Karchera4448d92010-07-22 18:04:15 +00001810 }
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001811 if (mmio_readw(spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001812 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001813 ichspi_lock = 1;
1814 }
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +10001815 ich_init_opcodes(ich_gen);
Edward O'Callaghan4c9b4162020-07-16 15:37:26 +10001816 ich_set_bbar(0, ich_gen);
Nico Huber7e496852021-05-11 17:38:14 +02001817 register_spi_master(&spi_master_ich7, NULL);
Michael Karchera4448d92010-07-22 18:04:15 +00001818 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001819 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001820 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001821 arg = extract_programmer_param("ich_spi_mode");
1822 if (arg && !strcmp(arg, "hwseq")) {
1823 ich_spi_mode = ich_hwseq;
1824 msg_pspew("user selected hwseq\n");
1825 } else if (arg && !strcmp(arg, "swseq")) {
1826 ich_spi_mode = ich_swseq;
1827 msg_pspew("user selected swseq\n");
1828 } else if (arg && !strcmp(arg, "auto")) {
1829 msg_pspew("user selected auto\n");
1830 ich_spi_mode = ich_auto;
1831 } else if (arg && !strlen(arg)) {
1832 msg_perr("Missing argument for ich_spi_mode.\n");
1833 free(arg);
1834 return ERROR_FATAL;
1835 } else if (arg) {
1836 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1837 arg);
1838 free(arg);
1839 return ERROR_FATAL;
1840 }
1841 free(arg);
1842
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001843 tmp2 = mmio_readw(spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001844 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001845 prettyprint_ich9_reg_hsfs(tmp2, ich_gen);
Stefan Tauner29c80832011-06-12 08:14:10 +00001846 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001847 msg_pinfo("SPI Configuration is locked down.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001848 ichspi_lock = 1;
1849 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001850 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001851 desc_valid = 1;
1852 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001853 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1854 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1855 "that Protected Range (PR) restrictions still apply.\n");
Edward O'Callaghan556fe8d2020-07-16 15:35:00 +10001856 ich_init_opcodes(ich_gen);
Stefan Tauner55206942011-06-11 09:53:22 +00001857
Stefan Taunerf382e352011-11-08 11:55:24 +00001858 if (desc_valid) {
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001859 tmp2 = mmio_readw(spibar + ICH9_REG_HSFC);
Stefan Taunerf382e352011-11-08 11:55:24 +00001860 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
Edward O'Callaghan68ba2ad2020-07-16 15:39:19 +10001861 prettyprint_ich9_reg_hsfc(tmp2, ich_gen);
Stefan Taunerf382e352011-11-08 11:55:24 +00001862 }
Michael Karchera4448d92010-07-22 18:04:15 +00001863
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001864 tmp = mmio_readl(spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001865 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001866
Nico Huberd2d39932019-01-18 16:49:37 +01001867 switch (ich_gen) {
1868 case CHIPSET_100_SERIES_SUNRISE_POINT:
1869 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001870 case CHIPSET_300_SERIES_CANNON_POINT:
Matt DeVillierb1f858f2020-08-12 12:48:06 -05001871 case CHIPSET_400_SERIES_COMET_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001872 case CHIPSET_APOLLO_LAKE:
Angel Pons11a35982020-07-10 17:04:10 +02001873 case CHIPSET_GEMINI_LAKE:
Edward O'Callaghan75cb1872020-07-16 17:14:01 +10001874 tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
Nico Huberd2d39932019-01-18 16:49:37 +01001875 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
1876 prettyprint_pch100_reg_dlock(tmp);
1877 break;
1878 default:
1879 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100