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Uwe Hermann2bc98f62009-09-30 18:29:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermann2bc98f62009-09-30 18:29:55 +000015 */
16
17#include <stdlib.h>
18#include <string.h>
Uwe Hermann2bc98f62009-09-30 18:29:55 +000019#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000020#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000021#include "hwaccess.h"
Uwe Hermann2bc98f62009-09-30 18:29:55 +000022
23#define PCI_VENDOR_ID_NVIDIA 0x10de
24
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +000025/* Mask to restrict flash accesses to a 128kB memory window.
26 * FIXME: Is this size a one-fits-all or card dependent?
27 */
28#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
David Hendricks8bb20212011-06-14 01:35:36 +000029#define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +000030
Jacob Garberafc3ad62019-06-24 16:05:28 -060031static uint8_t *nvidia_bar;
Uwe Hermann2bc98f62009-09-30 18:29:55 +000032
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000033const struct dev_entry gfx_nvidia[] = {
Michael Karcher84486392010-02-24 00:04:40 +000034 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
35 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
36 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
37 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
38 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
39 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
40 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
41 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
42 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
43 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
44 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
45 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
46 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
47 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
48 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
49 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
50 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
51 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
52 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
53 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
54 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
55 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
56 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
Uwe Hermann2bc98f62009-09-30 18:29:55 +000057
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000058 {0},
Uwe Hermann2bc98f62009-09-30 18:29:55 +000059};
60
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000061static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
62 chipaddr addr);
63static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
64 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000065static const struct par_master par_master_gfxnvidia = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000066 .chip_readb = gfxnvidia_chip_readb,
67 .chip_readw = fallback_chip_readw,
68 .chip_readl = fallback_chip_readl,
69 .chip_readn = fallback_chip_readn,
70 .chip_writeb = gfxnvidia_chip_writeb,
71 .chip_writew = fallback_chip_writew,
72 .chip_writel = fallback_chip_writel,
73 .chip_writen = fallback_chip_writen,
74};
75
Uwe Hermann2bc98f62009-09-30 18:29:55 +000076int gfxnvidia_init(void)
77{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000078 struct pci_dev *dev = NULL;
Uwe Hermann2bc98f62009-09-30 18:29:55 +000079 uint32_t reg32;
80
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000081 if (rget_io_perms())
82 return 1;
Uwe Hermann2bc98f62009-09-30 18:29:55 +000083
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000084 dev = pcidev_init(gfx_nvidia, PCI_BASE_ADDRESS_0);
85 if (!dev)
86 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000087
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000088 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000089 if (!io_base_addr)
90 return 1;
91
Uwe Hermann2bc98f62009-09-30 18:29:55 +000092 io_base_addr += 0x300000;
Sean Nelson8e5e73e2010-01-09 23:54:05 +000093 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
Uwe Hermann2bc98f62009-09-30 18:29:55 +000094
Stefan Tauner7fb5aa02013-08-14 15:48:44 +000095 nvidia_bar = rphysmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
96 if (nvidia_bar == ERROR_PTR)
David Hendricks8bb20212011-06-14 01:35:36 +000097 return 1;
98
Uwe Hermann2bc98f62009-09-30 18:29:55 +000099 /* Allow access to flash interface (will disable screen). */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000100 reg32 = pci_read_long(dev, 0x50);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000101 reg32 &= ~(1 << 0);
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000102 rpci_write_long(dev, 0x50, reg32);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000103
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000104 /* Write/erase doesn't work. */
105 programmer_may_write = 0;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000106 register_par_master(&par_master_gfxnvidia, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000107
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000108 return 0;
109}
110
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000111static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
112 chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000113{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000114 pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000115}
116
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000117static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
118 const chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000119{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000120 return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000121}